36 tmp.
replace(it.first, it.second);
45 bool found_init =
false;
47 for (
auto &sync : proc->
syncs)
53 for (
auto &action : sync->actions)
64 for (
auto &lhs_c : lhs.
chunks()) {
65 if (lhs_c.wire !=
NULL) {
67 if (value.
size() != lhs_c.wire->width)
70 lhs_c.wire->attributes[
"\\init"] = value.
as_const();
72 offset += lhs_c.width;
78 std::vector<RTLIL::SyncRule*> new_syncs;
79 for (
auto &sync : proc->
syncs)
83 new_syncs.push_back(sync);
84 proc->
syncs.swap(new_syncs);
94 log(
" proc_init [selection]\n");
96 log(
"This pass extracts the 'init' actions from processes (generated from verilog\n");
97 log(
"'initial' blocks) and sets the initial value to the 'init' attribute on the\n");
98 log(
"respective wire.\n");
103 log_header(
"Executing PROC_INIT pass (extract init attributes).\n");
107 for (
auto mod : design->
modules())
109 for (
auto &proc_it : mod->processes)
110 if (design->
selected(mod, proc_it.second))
const char * c_str() const
bool selected(T1 *module) const
void log_header(const char *format,...)
RTLIL::Const as_const() const
const char * log_signal(const RTLIL::SigSpec &sig, bool autoint)
USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN void proc_get_const(RTLIL::SigSpec &sig, RTLIL::CaseRule &rule)
std::vector< RTLIL::SigSpec > compare
#define PRIVATE_NAMESPACE_BEGIN
#define log_assert(_assert_expr_)
bool is_fully_const() const
#define PRIVATE_NAMESPACE_END
void log_cmd_error(const char *format,...)
#define USING_YOSYS_NAMESPACE
RTLIL::ObjRange< RTLIL::Module * > modules()
void proc_init(RTLIL::Module *mod, RTLIL::Process *proc)
void replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with)
virtual void execute(std::vector< std::string > args, RTLIL::Design *design)
void log(const char *format,...)
std::vector< RTLIL::SyncRule * > syncs
ProcInitPass ProcInitPass
RTLIL::SigSpec extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other=NULL) const
std::vector< RTLIL::SigSig > actions
void extra_args(std::vector< std::string > args, size_t argidx, RTLIL::Design *design, bool select=true)
const std::vector< RTLIL::SigChunk > & chunks() const
RTLIL_ATTRIBUTE_MEMBERS RTLIL::CaseRule root_case