ILANG_BACKEND Namespace Reference

Functions
void	dump_const (std::ostream &f, const RTLIL::Const &data, int width=-1, int offset=0, bool autoint=true)
void	dump_sigchunk (std::ostream &f, const RTLIL::SigChunk &chunk, bool autoint=true)
void	dump_sigspec (std::ostream &f, const RTLIL::SigSpec &sig, bool autoint=true)
void	dump_wire (std::ostream &f, std::string indent, const RTLIL::Wire *wire)
void	dump_memory (std::ostream &f, std::string indent, const RTLIL::Memory *memory)
void	dump_cell (std::ostream &f, std::string indent, const RTLIL::Cell *cell)
void	dump_proc_case_body (std::ostream &f, std::string indent, const RTLIL::CaseRule *cs)
void	dump_proc_switch (std::ostream &f, std::string indent, const RTLIL::SwitchRule *sw)
void	dump_proc_sync (std::ostream &f, std::string indent, const RTLIL::SyncRule *sy)
void	dump_proc (std::ostream &f, std::string indent, const RTLIL::Process *proc)
void	dump_conn (std::ostream &f, std::string indent, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right)
void	dump_module (std::ostream &f, std::string indent, RTLIL::Module *module, RTLIL::Design *design, bool only_selected, bool flag_m=true, bool flag_n=false)
void	dump_design (std::ostream &f, RTLIL::Design *design, bool only_selected, bool flag_m=true, bool flag_n=false)

Function Documentation

void ILANG_BACKEND::dump_cell	(	std::ostream &	f,
		std::string	indent,
		const RTLIL::Cell *	cell
	)

Definition at line 156 of file ilang_backend.cc.

{
    std::map<RTLIL::IdString, RTLIL::Const, RTLIL::sort_by_id_str> sorted_attributes(cell->attributes.begin(), cell->attributes.end());
    std::map<RTLIL::IdString, RTLIL::Const, RTLIL::sort_by_id_str> sorted_parameters(cell->parameters.begin(), cell->parameters.end());
    std::map<RTLIL::IdString, RTLIL::SigSpec, RTLIL::sort_by_id_str> sorted_connections(cell->connections().begin(), cell->connections().end());

    for (auto it = sorted_attributes.begin(); it != sorted_attributes.end(); it++) {
        f << stringf("%s" "attribute %s ", indent.c_str(), it->first.c_str());
        dump_const(f, it->second);
        f << stringf("\n");
    }
    f << stringf("%s" "cell %s %s\n", indent.c_str(), cell->type.c_str(), cell->name.c_str());
    for (auto it = sorted_parameters.begin(); it != sorted_parameters.end(); it++) {
        f << stringf("%s  parameter%s %s ", indent.c_str(), (it->second.flags & RTLIL::CONST_FLAG_SIGNED) != 0 ? " signed" : "", it->first.c_str());
        dump_const(f, it->second);
        f << stringf("\n");
    }
    for (auto it = sorted_connections.begin(); it != sorted_connections.end(); it++) {
        f << stringf("%s  connect %s ", indent.c_str(), it->first.c_str());
        dump_sigspec(f, it->second);
        f << stringf("\n");
    }
    f << stringf("%s" "end\n", indent.c_str());
}

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void ILANG_BACKEND::dump_conn	(	std::ostream &	f,
		std::string	indent,
		const RTLIL::SigSpec &	left,
		const RTLIL::SigSpec &	right
	)

Definition at line 263 of file ilang_backend.cc.

{
    f << stringf("%s" "connect ", indent.c_str());
    dump_sigspec(f, left);
    f << stringf(" ");
    dump_sigspec(f, right);
    f << stringf("\n");
}

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YOSYS_NAMESPACE_BEGIN void ILANG_BACKEND::dump_const	(	std::ostream &	f,
		const RTLIL::Const &	data,
		int	width = -1,
		int	offset = 0,
		bool	autoint = true
	)

Definition at line 33 of file ilang_backend.cc.

{
    if (width < 0)
        width = data.bits.size() - offset;
    if ((data.flags & RTLIL::CONST_FLAG_STRING) == 0 || width != (int)data.bits.size()) {
        if (width == 32 && autoint) {
            int32_t val = 0;
            for (int i = 0; i < width; i++) {
                log_assert(offset+i < (int)data.bits.size());
                switch (data.bits[offset+i]) {
                case RTLIL::S0: break;
                case RTLIL::S1: val |= 1 << i; break;
                default: val = -1; break;
                }
            }
            if (val >= 0) {
                f << stringf("%d", val);
                return;
            }
        }
        f << stringf("%d'", width);
        for (int i = offset+width-1; i >= offset; i--) {
            log_assert(i < (int)data.bits.size());
            switch (data.bits[i]) {
            case RTLIL::S0: f << stringf("0"); break;
            case RTLIL::S1: f << stringf("1"); break;
            case RTLIL::Sx: f << stringf("x"); break;
            case RTLIL::Sz: f << stringf("z"); break;
            case RTLIL::Sa: f << stringf("-"); break;
            case RTLIL::Sm: f << stringf("m"); break;
            }
        }
    } else {
        f << stringf("\"");
        std::string str = data.decode_string();
        for (size_t i = 0; i < str.size(); i++) {
            if (str[i] == '\n')
                f << stringf("\\n");
            else if (str[i] == '\t')
                f << stringf("\\t");
            else if (str[i] < 32)
                f << stringf("\\%03o", str[i]);
            else if (str[i] == '"')
                f << stringf("\\\"");
            else if (str[i] == '\\')
                f << stringf("\\\\");
            else
                f << str[i];
        }
        f << stringf("\"");
    }
}

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void ILANG_BACKEND::dump_design	(	std::ostream &	f,
		RTLIL::Design *	design,
		bool	only_selected,
		bool	flag_m = true,
		bool	flag_n = false
	)

Definition at line 363 of file ilang_backend.cc.

{
    int init_autoidx = autoidx;

    if (!flag_m) {
        int count_selected_mods = 0;
        for (auto it = design->modules_.begin(); it != design->modules_.end(); it++) {
            if (design->selected_whole_module(it->first))
                flag_m = true;
            if (design->selected(it->second))
                count_selected_mods++;
        }
        if (count_selected_mods > 1)
            flag_m = true;
    }

    if (!only_selected || flag_m) {
        if (only_selected)
            f << stringf("\n");
        f << stringf("autoidx %d\n", autoidx);
    }

    for (auto it = design->modules_.begin(); it != design->modules_.end(); it++) {
        if (!only_selected || design->selected(it->second)) {
            if (only_selected)
                f << stringf("\n");
            dump_module(f, "", it->second, design, only_selected, flag_m, flag_n);
        }
    }

    log_assert(init_autoidx == autoidx);
}

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void ILANG_BACKEND::dump_memory	(	std::ostream &	f,
		std::string	indent,
		const RTLIL::Memory *	memory
	)

Definition at line 139 of file ilang_backend.cc.

{
    std::map<RTLIL::IdString, RTLIL::Const, RTLIL::sort_by_id_str> sorted_attributes(memory->attributes.begin(), memory->attributes.end());

    for (auto it = sorted_attributes.begin(); it != sorted_attributes.end(); it++) {
        f << stringf("%s" "attribute %s ", indent.c_str(), it->first.c_str());
        dump_const(f, it->second);
        f << stringf("\n");
    }
    f << stringf("%s" "memory ", indent.c_str());
    if (memory->width != 1)
        f << stringf("width %d ", memory->width);
    if (memory->size != 0)
        f << stringf("size %d ", memory->size);
    f << stringf("%s\n", memory->name.c_str());
}

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void ILANG_BACKEND::dump_module	(	std::ostream &	f,
		std::string	indent,
		RTLIL::Module *	module,
		RTLIL::Design *	design,
		bool	only_selected,
		bool	flag_m = true,
		bool	flag_n = false
	)

Definition at line 272 of file ilang_backend.cc.

{
    bool print_header = flag_m || design->selected_whole_module(module->name);
    bool print_body = !flag_n || !design->selected_whole_module(module->name);

    if (print_header)
    {
        for (auto it = module->attributes.begin(); it != module->attributes.end(); it++) {
            f << stringf("%s" "attribute %s ", indent.c_str(), it->first.c_str());
            dump_const(f, it->second);
            f << stringf("\n");
        }

        f << stringf("%s" "module %s\n", indent.c_str(), module->name.c_str());
    }

    if (print_body)
    {
        std::vector<RTLIL::Wire*> sorted_wires;
        for (auto it : module->wires())
            sorted_wires.push_back(it);
        std::sort(sorted_wires.begin(), sorted_wires.end(), RTLIL::sort_by_name_str<RTLIL::Wire>());

        std::vector<RTLIL::Memory*> sorted_memories;
        for (auto it : module->memories)
            sorted_memories.push_back(it.second);
        std::sort(sorted_memories.begin(), sorted_memories.end(), RTLIL::sort_by_name_str<RTLIL::Memory>());

        std::vector<RTLIL::Cell*> sorted_cells;
        for (auto it : module->cells())
            sorted_cells.push_back(it);
        std::sort(sorted_cells.begin(), sorted_cells.end(), RTLIL::sort_by_name_str<RTLIL::Cell>());

        std::vector<RTLIL::Process*> sorted_processes;
        for (auto it : module->processes)
            sorted_processes.push_back(it.second);
        std::sort(sorted_processes.begin(), sorted_processes.end(), RTLIL::sort_by_name_str<RTLIL::Process>());

        for (auto it : sorted_wires)
            if (!only_selected || design->selected(module, it)) {
                if (only_selected)
                    f << stringf("\n");
                dump_wire(f, indent + "  ", it);
            }

        for (auto it : sorted_memories)
            if (!only_selected || design->selected(module, it)) {
                if (only_selected)
                    f << stringf("\n");
                dump_memory(f, indent + "  ", it);
            }

        for (auto it : sorted_cells)
            if (!only_selected || design->selected(module, it)) {
                if (only_selected)
                    f << stringf("\n");
                dump_cell(f, indent + "  ", it);
            }

        for (auto it : sorted_processes)
            if (!only_selected || design->selected(module, it)) {
                if (only_selected)
                    f << stringf("\n");
                dump_proc(f, indent + "  ", it);
            }

        bool first_conn_line = true;
        for (auto it = module->connections().begin(); it != module->connections().end(); it++) {
            bool show_conn = !only_selected;
            if (only_selected) {
                RTLIL::SigSpec sigs = it->first;
                sigs.append(it->second);
                for (auto &c : sigs.chunks()) {
                    if (c.wire == NULL || !design->selected(module, c.wire))
                        continue;
                    show_conn = true;
                }
            }
            if (show_conn) {
                if (only_selected && first_conn_line)
                    f << stringf("\n");
                dump_conn(f, indent + "  ", it->first, it->second);
                first_conn_line = false;
            }
        }
    }

    if (print_header)
        f << stringf("%s" "end\n", indent.c_str());
}

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void ILANG_BACKEND::dump_proc	(	std::ostream &	f,
		std::string	indent,
		const RTLIL::Process *	proc
	)

Definition at line 249 of file ilang_backend.cc.

{
    for (auto it = proc->attributes.begin(); it != proc->attributes.end(); it++) {
        f << stringf("%s" "attribute %s ", indent.c_str(), it->first.c_str());
        dump_const(f, it->second);
        f << stringf("\n");
    }
    f << stringf("%s" "process %s\n", indent.c_str(), proc->name.c_str());
    dump_proc_case_body(f, indent + "  ", &proc->root_case);
    for (auto it = proc->syncs.begin(); it != proc->syncs.end(); it++)
        dump_proc_sync(f, indent + "  ", *it);
    f << stringf("%s" "end\n", indent.c_str());
}

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void ILANG_BACKEND::dump_proc_case_body	(	std::ostream &	f,
		std::string	indent,
		const RTLIL::CaseRule *	cs
	)

Definition at line 181 of file ilang_backend.cc.

{
    for (auto it = cs->actions.begin(); it != cs->actions.end(); it++)
    {
        f << stringf("%s" "assign ", indent.c_str());
        dump_sigspec(f, it->first);
        f << stringf(" ");
        dump_sigspec(f, it->second);
        f << stringf("\n");
    }

    for (auto it = cs->switches.begin(); it != cs->switches.end(); it++)
        dump_proc_switch(f, indent, *it);
}

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void ILANG_BACKEND::dump_proc_switch	(	std::ostream &	f,
		std::string	indent,
		const RTLIL::SwitchRule *	sw
	)

Definition at line 196 of file ilang_backend.cc.

{
    for (auto it = sw->attributes.begin(); it != sw->attributes.end(); it++) {
        f << stringf("%s" "attribute %s ", indent.c_str(), it->first.c_str());
        dump_const(f, it->second);
        f << stringf("\n");
    }

    f << stringf("%s" "switch ", indent.c_str());
    dump_sigspec(f, sw->signal);
    f << stringf("\n");

    for (auto it = sw->cases.begin(); it != sw->cases.end(); it++)
    {
        f << stringf("%s  case ", indent.c_str());
        for (size_t i = 0; i < (*it)->compare.size(); i++) {
            if (i > 0)
                f << stringf(", ");
            dump_sigspec(f, (*it)->compare[i]);
        }
        f << stringf("\n");

        dump_proc_case_body(f, indent + "    ", *it);
    }

    f << stringf("%s" "end\n", indent.c_str());
}

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void ILANG_BACKEND::dump_proc_sync	(	std::ostream &	f,
		std::string	indent,
		const RTLIL::SyncRule *	sy
	)

Definition at line 224 of file ilang_backend.cc.

{
    f << stringf("%s" "sync ", indent.c_str());
    switch (sy->type) {
    if (0) case RTLIL::ST0: f << stringf("low ");
    if (0) case RTLIL::ST1: f << stringf("high ");
    if (0) case RTLIL::STp: f << stringf("posedge ");
    if (0) case RTLIL::STn: f << stringf("negedge ");
    if (0) case RTLIL::STe: f << stringf("edge ");
        dump_sigspec(f, sy->signal);
        f << stringf("\n");
        break;
    case RTLIL::STa: f << stringf("always\n"); break;
    case RTLIL::STi: f << stringf("init\n"); break;
    }

    for (auto it = sy->actions.begin(); it != sy->actions.end(); it++) {
        f << stringf("%s  update ", indent.c_str());
        dump_sigspec(f, it->first);
        f << stringf(" ");
        dump_sigspec(f, it->second);
        f << stringf("\n");
    }
}

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void ILANG_BACKEND::dump_sigchunk	(	std::ostream &	f,
		const RTLIL::SigChunk &	chunk,
		bool	autoint = true
	)

Definition at line 86 of file ilang_backend.cc.

{
    if (chunk.wire == NULL) {
        dump_const(f, chunk.data, chunk.width, chunk.offset, autoint);
    } else {
        if (chunk.width == chunk.wire->width && chunk.offset == 0)
            f << stringf("%s", chunk.wire->name.c_str());
        else if (chunk.width == 1)
            f << stringf("%s [%d]", chunk.wire->name.c_str(), chunk.offset);
        else
            f << stringf("%s [%d:%d]", chunk.wire->name.c_str(), chunk.offset+chunk.width-1, chunk.offset);
    }
}

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void ILANG_BACKEND::dump_sigspec	(	std::ostream &	f,
		const RTLIL::SigSpec &	sig,
		bool	autoint = true
	)

Definition at line 100 of file ilang_backend.cc.

{
    if (sig.is_chunk()) {
        dump_sigchunk(f, sig.as_chunk(), autoint);
    } else {
        f << stringf("{ ");
        for (auto it = sig.chunks().rbegin(); it != sig.chunks().rend(); it++) {
            dump_sigchunk(f, *it, false);
            f << stringf(" ");
        }
        f << stringf("}");
    }
}

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void ILANG_BACKEND::dump_wire	(	std::ostream &	f,
		std::string	indent,
		const RTLIL::Wire *	wire
	)

Definition at line 114 of file ilang_backend.cc.

{
    std::map<RTLIL::IdString, RTLIL::Const, RTLIL::sort_by_id_str> sorted_attributes(wire->attributes.begin(), wire->attributes.end());

    for (auto it = sorted_attributes.begin(); it != sorted_attributes.end(); it++) {
        f << stringf("%s" "attribute %s ", indent.c_str(), it->first.c_str());
        dump_const(f, it->second);
        f << stringf("\n");
    }
    f << stringf("%s" "wire ", indent.c_str());
    if (wire->width != 1)
        f << stringf("width %d ", wire->width);
    if (wire->upto)
        f << stringf("upto ");
    if (wire->start_offset != 0)
        f << stringf("offset %d ", wire->start_offset);
    if (wire->port_input && !wire->port_output)
        f << stringf("input %d ", wire->port_id);
    if (!wire->port_input && wire->port_output)
        f << stringf("output %d ", wire->port_id);
    if (wire->port_input && wire->port_output)
        f << stringf("inout %d ", wire->port_id);
    f << stringf("%s\n", wire->name.c_str());
}

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