Inheritance diagram for TestCellPass:

Collaboration diagram for TestCellPass:

Public Member Functions
	TestCellPass ()

virtual void	help ()

virtual void	execute (std::vector< std::string > args, RTLIL::Design *)

pre_post_exec_state_t	pre_execute ()

void	post_execute (pre_post_exec_state_t state)

void	cmd_log_args (const std::vector< std::string > &args)

void	cmd_error (const std::vector< std::string > &args, size_t argidx, std::string msg)

void	extra_args (std::vector< std::string > args, size_t argidx, RTLIL::Design *design, bool select=true)

virtual void	run_register ()

Static Public Member Functions
static void	call (RTLIL::Design *design, std::string command)

static void	call (RTLIL::Design *design, std::vector< std::string > args)

static void	call_on_selection (RTLIL::Design *design, const RTLIL::Selection &selection, std::string command)

static void	call_on_selection (RTLIL::Design *design, const RTLIL::Selection &selection, std::vector< std::string > args)

static void	call_on_module (RTLIL::Design design, RTLIL::Module module, std::string command)

static void	call_on_module (RTLIL::Design design, RTLIL::Module module, std::vector< std::string > args)

static void	init_register ()

static void	done_register ()

Data Fields
std::string	pass_name

std::string	short_help

int	call_counter

int64_t	runtime_ns

Pass *	next_queued_pass

Detailed Description

Definition at line 499 of file test_cell.cc.

Constructor & Destructor Documentation

TestCellPass::TestCellPass ( )

inline

Definition at line 500 of file test_cell.cc.

500 : Pass("test_cell", "automatically test the implementation of a cell type") { }

Pass::Pass

Pass(std::string name, std::string short_help="** document me **")

Definition: register.cc:40

Member Function Documentation

void Pass::call	(	RTLIL::Design *	design,
		std::string	command
	)

staticinherited

Definition at line 146 of file register.cc.

 {
     std::vector<std::string> args;
 
     std::string cmd_buf = command;
     std::string tok = next_token(cmd_buf, " \t\r\n");
 
     if (tok.empty() || tok[0] == '#')
         return;
 
     if (tok[0] == '!') {
         cmd_buf = command.substr(command.find('!') + 1);
         while (!cmd_buf.empty() && (cmd_buf.back() == ' ' || cmd_buf.back() == '\t' ||
                 cmd_buf.back() == '\r' || cmd_buf.back() == '\n'))
             cmd_buf.resize(cmd_buf.size()-1);
         log_header("Shell command: %s\n", cmd_buf.c_str());
         int retCode = run_command(cmd_buf);
         if (retCode != 0)
             log_cmd_error("Shell command returned error code %d.\n", retCode);
         return;
     }
 
     while (!tok.empty()) {
         if (tok == "#")
             break;
         if (tok.back() == ';') {
             int num_semikolon = 0;
             while (!tok.empty() && tok.back() == ';')
                 tok.resize(tok.size()-1), num_semikolon++;
             if (!tok.empty())
                 args.push_back(tok);
             call(design, args);
             args.clear();
             if (num_semikolon == 2)
                 call(design, "clean");
             if (num_semikolon == 3)
                 call(design, "clean -purge");
         } else
             args.push_back(tok);
         tok = next_token(cmd_buf, " \t\r\n");
     }
 
     call(design, args);
 }

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void Pass::call	(	RTLIL::Design *	design,
		std::vector< std::string >	args
	)

staticinherited

Definition at line 191 of file register.cc.

 {
     if (args.size() == 0 || args[0][0] == '#')
         return;
 
     if (echo_mode) {
         log("%s", create_prompt(design, 0));
         for (size_t i = 0; i < args.size(); i++)
             log("%s%s", i ? " " : "", args[i].c_str());
         log("\n");
     }
 
     if (pass_register.count(args[0]) == 0)
         log_cmd_error("No such command: %s (type 'help' for a command overview)\n", args[0].c_str());
 
     size_t orig_sel_stack_pos = design->selection_stack.size();
     auto state = pass_register[args[0]]->pre_execute();
     pass_register[args[0]]->execute(args, design);
     pass_register[args[0]]->post_execute(state);
     while (design->selection_stack.size() > orig_sel_stack_pos)
         design->selection_stack.pop_back();
 
     design->check();
 }

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void Pass::call_on_module	(	RTLIL::Design *	design,
		RTLIL::Module *	module,
		std::string	command
	)

staticinherited

Definition at line 240 of file register.cc.

 {
     std::string backup_selected_active_module = design->selected_active_module;
     design->selected_active_module = module->name.str();
     design->selection_stack.push_back(RTLIL::Selection(false));
     design->selection_stack.back().select(module);
 
     Pass::call(design, command);
 
     design->selection_stack.pop_back();
     design->selected_active_module = backup_selected_active_module;
 }

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void Pass::call_on_module	(	RTLIL::Design *	design,
		RTLIL::Module *	module,
		std::vector< std::string >	args
	)

staticinherited

Definition at line 253 of file register.cc.

 {
     std::string backup_selected_active_module = design->selected_active_module;
     design->selected_active_module = module->name.str();
     design->selection_stack.push_back(RTLIL::Selection(false));
     design->selection_stack.back().select(module);
 
     Pass::call(design, args);
 
     design->selection_stack.pop_back();
     design->selected_active_module = backup_selected_active_module;
 }

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void Pass::call_on_selection	(	RTLIL::Design *	design,
		const RTLIL::Selection &	selection,
		std::string	command
	)

staticinherited

Definition at line 216 of file register.cc.

 {
     std::string backup_selected_active_module = design->selected_active_module;
     design->selected_active_module.clear();
     design->selection_stack.push_back(selection);
 
     Pass::call(design, command);
 
     design->selection_stack.pop_back();
     design->selected_active_module = backup_selected_active_module;
 }

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void Pass::call_on_selection	(	RTLIL::Design *	design,
		const RTLIL::Selection &	selection,
		std::vector< std::string >	args
	)

staticinherited

Definition at line 228 of file register.cc.

 {
     std::string backup_selected_active_module = design->selected_active_module;
     design->selected_active_module.clear();
     design->selection_stack.push_back(selection);
 
     Pass::call(design, args);
 
     design->selection_stack.pop_back();
     design->selected_active_module = backup_selected_active_module;
 }

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void Pass::cmd_error	(	const std::vector< std::string > &	args,
		size_t	argidx,
		std::string	msg
	)

inherited

Definition at line 110 of file register.cc.

 {
     std::string command_text;
     int error_pos = 0;
 
     for (size_t i = 0; i < args.size(); i++) {
         if (i < argidx)
             error_pos += args[i].size() + 1;
         command_text = command_text + (command_text.empty() ? "" : " ") + args[i];
     }
 
     log("\nSyntax error in command `%s':\n", command_text.c_str());
     help();
 
     log_cmd_error("Command syntax error: %s\n> %s\n> %*s^\n",
             msg.c_str(), command_text.c_str(), error_pos, "");
 }

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void Pass::cmd_log_args ( const std::vector< std::string > & args )

inherited

Definition at line 100 of file register.cc.

 {
     if (args.size() <= 1)
         return;
     log("Full command line:");
     for (size_t i = 0; i < args.size(); i++)
         log(" %s", args[i].c_str());
     log("\n");
 }

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void Pass::done_register ( )

staticinherited

Definition at line 62 of file register.cc.

 {
     frontend_register.clear();
     pass_register.clear();
     backend_register.clear();
     log_assert(first_queued_pass == NULL);
 }

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virtual void TestCellPass::execute	(	std::vector< std::string >	args,
		RTLIL::Design *
	)

inlinevirtual

Implements Pass.

Definition at line 544 of file test_cell.cc.

     {
         int num_iter = 100;
         std::string techmap_cmd = "techmap -assert";
         std::string ilang_file;
         xorshift32_state = 0;
         std::ofstream vlog_file;
         bool verbose = false;
         bool constmode = false;
         bool nosat = false;
 
         int argidx;
         for (argidx = 1; argidx < GetSize(args); argidx++)
         {
             if (args[argidx] == "-n" && argidx+1 < GetSize(args)) {
                 num_iter = atoi(args[++argidx].c_str());
                 continue;
             }
             if (args[argidx] == "-s" && argidx+1 < GetSize(args)) {
                 xorshift32_state = atoi(args[++argidx].c_str());
                 continue;
             }
             if (args[argidx] == "-map" && argidx+1 < GetSize(args)) {
                 techmap_cmd += " -map " + args[++argidx];
                 continue;
             }
             if (args[argidx] == "-f" && argidx+1 < GetSize(args)) {
                 ilang_file = args[++argidx];
                 num_iter = 1;
                 continue;
             }
             if (args[argidx] == "-script" && argidx+1 < GetSize(args)) {
                 techmap_cmd = "script " + args[++argidx];
                 continue;
             }
             if (args[argidx] == "-simlib") {
                 techmap_cmd = "techmap -map +/simlib.v -max_iter 2 -autoproc";
                 continue;
             }
             if (args[argidx] == "-const") {
                 constmode = true;
                 continue;
             }
             if (args[argidx] == "-nosat") {
                 nosat = true;
                 continue;
             }
             if (args[argidx] == "-v") {
                 verbose = true;
                 continue;
             }
             if (args[argidx] == "-vlog" && argidx+1 < GetSize(args)) {
                 vlog_file.open(args[++argidx], std::ios_base::trunc);
                 if (!vlog_file.is_open())
                     log_cmd_error("Failed to open output file `%s'.\n", args[argidx].c_str());
                 continue;
             }
             break;
         }
 
         if (xorshift32_state == 0) {
             xorshift32_state = time(NULL) & 0x7fffffff;
             log("Rng seed value: %d\n", int(xorshift32_state));
         }
 
         std::map<std::string, std::string> cell_types;
         std::vector<std::string> selected_cell_types;
 
         cell_types["$not"] = "ASY";
         cell_types["$pos"] = "ASY";
         cell_types["$neg"] = "ASY";
 
         cell_types["$and"]  = "ABSY";
         cell_types["$or"]   = "ABSY";
         cell_types["$xor"]  = "ABSY";
         cell_types["$xnor"] = "ABSY";
 
         cell_types["$reduce_and"]  = "ASY";
         cell_types["$reduce_or"]   = "ASY";
         cell_types["$reduce_xor"]  = "ASY";
         cell_types["$reduce_xnor"] = "ASY";
         cell_types["$reduce_bool"] = "ASY";
 
         cell_types["$shl"]    = "ABshY";
         cell_types["$shr"]    = "ABshY";
         cell_types["$sshl"]   = "ABshY";
         cell_types["$sshr"]   = "ABshY";
         cell_types["$shift"]  = "ABshY";
         cell_types["$shiftx"] = "ABshY";
 
         cell_types["$lt"]  = "ABSY";
         cell_types["$le"]  = "ABSY";
         cell_types["$eq"]  = "ABSY";
         cell_types["$ne"]  = "ABSY";
         // cell_types["$eqx"] = "ABSY";
         // cell_types["$nex"] = "ABSY";
         cell_types["$ge"]  = "ABSY";
         cell_types["$gt"]  = "ABSY";
 
         cell_types["$add"] = "ABSY";
         cell_types["$sub"] = "ABSY";
         cell_types["$mul"] = "ABSY";
         cell_types["$div"] = "ABSY";
         cell_types["$mod"] = "ABSY";
         // cell_types["$pow"] = "ABsY";
 
         cell_types["$logic_not"] = "ASY";
         cell_types["$logic_and"] = "ABSY";
         cell_types["$logic_or"]  = "ABSY";
 
         // cell_types["$mux"] = "A";
         // cell_types["$pmux"] = "A";
         // cell_types["$slice"] = "A";
         // cell_types["$concat"] = "A";
         // cell_types["$assert"] = "A";
 
         cell_types["$lut"] = "*";
         cell_types["$alu"] = "ABSY";
         cell_types["$lcu"] = "*";
         cell_types["$macc"] = "*";
         cell_types["$fa"] = "*";
 
         for (; argidx < GetSize(args); argidx++)
         {
             if (args[argidx].rfind("-", 0) == 0)
                 log_cmd_error("Unexpected option: %s\n", args[argidx].c_str());
 
             if (args[argidx] == "all") {
                 for (auto &it : cell_types)
                     if (std::count(selected_cell_types.begin(), selected_cell_types.end(), it.first) == 0)
                         selected_cell_types.push_back(it.first);
                 continue;
             }
 
             if (cell_types.count(args[argidx]) == 0) {
                 std::string cell_type_list;
                 int charcount = 100;
                 for (auto &it : cell_types) {
                     if (charcount > 60) {
                         cell_type_list += "\n" + it.first;
                         charcount = 0;
                     } else
                         cell_type_list += " " + it.first;
                     charcount += GetSize(it.first);
                 }
                 log_cmd_error("The cell type `%s' is currently not supported. Try one of these:%s\n",
                         args[argidx].c_str(), cell_type_list.c_str());
             }
 
             if (std::count(selected_cell_types.begin(), selected_cell_types.end(), args[argidx]) == 0)
                 selected_cell_types.push_back(args[argidx]);
         }
 
         if (!ilang_file.empty()) {
             if (!selected_cell_types.empty())
                 log_cmd_error("Do not specify any cell types when using -f.\n");
             selected_cell_types.push_back("ilang");
         }
 
         if (selected_cell_types.empty())
             log_cmd_error("No cell type to test specified.\n");
 
         std::vector<std::string> uut_names;
 
         for (auto cell_type : selected_cell_types)
             for (int i = 0; i < num_iter; i++)
             {
                 RTLIL::Design *design = new RTLIL::Design;
                 if (cell_type == "ilang")
                     Frontend::frontend_call(design, NULL, std::string(), "ilang " + ilang_file);
                 else
                     create_gold_module(design, cell_type, cell_types.at(cell_type), constmode);
                 Pass::call(design, stringf("copy gold gate; cd gate; %s; cd ..; opt -fast gate", techmap_cmd.c_str()));
                 if (!nosat)
                     Pass::call(design, "miter -equiv -flatten -make_outputs -ignore_gold_x gold gate miter");
                 if (verbose)
                     Pass::call(design, "dump gate");
                 Pass::call(design, "dump gold");
                 if (!nosat)
                     Pass::call(design, "sat -verify -enable_undef -prove trigger 0 -show-inputs -show-outputs miter");
                 std::string uut_name = stringf("uut_%s_%d", cell_type.substr(1).c_str(), i);
                 if (vlog_file.is_open()) {
                     Pass::call(design, stringf("copy gold %s_expr; select %s_expr", uut_name.c_str(), uut_name.c_str()));
                     Backend::backend_call(design, &vlog_file, "<test_cell -vlog>", "verilog -selected");
                     Pass::call(design, stringf("copy gold %s_noexpr; select %s_noexpr", uut_name.c_str(), uut_name.c_str()));
                     Backend::backend_call(design, &vlog_file, "<test_cell -vlog>", "verilog -selected -noexpr");
                     uut_names.push_back(uut_name);
                 }
                 run_eval_test(design, verbose, nosat, uut_name, vlog_file);
                 delete design;
             }
 
         if (vlog_file.is_open()) {
             vlog_file << "\nmodule testbench;\n";
             for (auto &uut : uut_names)
                 vlog_file << stringf("  %s %s ();\n", uut.c_str(), uut.c_str());
             vlog_file << "  initial begin\n";
             for (auto &uut : uut_names)
                 vlog_file << "    " << uut << ".run;\n";
             vlog_file << "  end\n";
             vlog_file << "endmodule\n";
         }
     }

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void Pass::extra_args	(	std::vector< std::string >	args,
		size_t	argidx,
		RTLIL::Design *	design,
		bool	select = `true`
	)

inherited

Definition at line 128 of file register.cc.

 {
     for (; argidx < args.size(); argidx++)
     {
         std::string arg = args[argidx];
 
         if (arg.substr(0, 1) == "-")
             cmd_error(args, argidx, "Unknown option or option in arguments.");
 
         if (!select)
             cmd_error(args, argidx, "Extra argument.");
 
         handle_extra_select_args(this, args, argidx, args.size(), design);
         break;
     }
     // cmd_log_args(args);
 }

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virtual void TestCellPass::help ( )

inlinevirtual

Reimplemented from Pass.

Definition at line 501 of file test_cell.cc.

     {
         //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
         log("\n");
         log("    test_cell [options] {cell-types}\n");
         log("\n");
         log("Tests the internal implementation of the given cell type (for example '$add')\n");
         log("by comparing SAT solver, EVAL and TECHMAP implementations of the cell types..\n");
         log("\n");
         log("Run with 'all' instead of a cell type to run the test on all supported\n");
         log("cell types.\n");
         log("\n");
         log("    -n {integer}\n");
         log("        create this number of cell instances and test them (default = 100).\n");
         log("\n");
         log("    -s {positive_integer}\n");
         log("        use this value as rng seed value (default = unix time).\n");
         log("\n");
         log("    -f {ilang_file}\n");
         log("        don't generate circuits. instead load the specified ilang file.\n");
         log("\n");
         log("    -map {filename}\n");
         log("        pass this option to techmap.\n");
         log("\n");
         log("    -simlib\n");
         log("        use \"techmap -map +/simlib.v -max_iter 2 -autoproc\"\n");
         log("\n");
         log("    -script {script_file}\n");
         log("        instead of calling \"techmap\", call \"script {script_file}\".\n");
         log("\n");
         log("    -const\n");
         log("        set some input bits to random constant values\n");
         log("\n");
         log("    -nosat\n");
         log("        do not check SAT model or run SAT equivalence checking\n");
         log("\n");
         log("    -v\n");
         log("        print additional debug information to the console\n");
         log("\n");
         log("    -vlog {filename}\n");
         log("        create a verilog test bench to test simlib and write_verilog\n");
         log("\n");
     }

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void Pass::init_register ( )

staticinherited

Definition at line 54 of file register.cc.

 {
     while (first_queued_pass) {
         first_queued_pass->run_register();
         first_queued_pass = first_queued_pass->next_queued_pass;
     }
 }

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void Pass::post_execute ( Pass::pre_post_exec_state_t state )

inherited

Definition at line 84 of file register.cc.

 {
     int64_t time_ns = PerformanceTimer::query() - state.begin_ns;
     runtime_ns += time_ns;
     current_pass = state.parent_pass;
     if (current_pass)
         current_pass->runtime_ns -= time_ns;
 }

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Pass::pre_post_exec_state_t Pass::pre_execute ( )

inherited

Definition at line 74 of file register.cc.

 {
     pre_post_exec_state_t state;
     call_counter++;
     state.begin_ns = PerformanceTimer::query();
     state.parent_pass = current_pass;
     current_pass = this;
     return state;
 }

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void Pass::run_register ( )

virtualinherited

Reimplemented in Backend, and Frontend.

Definition at line 48 of file register.cc.

 {
     log_assert(pass_register.count(pass_name) == 0);
     pass_register[pass_name] = this;
 }

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Field Documentation

int Pass::call_counter

inherited

Definition at line 36 of file register.h.

Pass* Pass::next_queued_pass

inherited

Definition at line 60 of file register.h.

std::string Pass::pass_name

inherited

Definition at line 29 of file register.h.

int64_t Pass::runtime_ns

inherited

Definition at line 37 of file register.h.

std::string Pass::short_help

inherited

Definition at line 29 of file register.h.

The documentation for this struct was generated from the following file:

test_cell.cc

Public Member Functions

Static Public Member Functions

Data Fields

Detailed Description

Constructor & Destructor Documentation

Member Function Documentation

Field Documentation