#include "kernel/register.h"
#include "kernel/log.h"
#include <stdlib.h>
#include <stdio.h>
Go to the source code of this file.
Definition at line 122 of file proc_clean.cc.
126 for (
size_t i = 0; i < proc->
syncs.size(); i++) {
127 for (
size_t j = 0; j < proc->
syncs[i]->actions.size(); j++)
128 if (proc->
syncs[i]->actions[j].first.size() == 0)
129 proc->
syncs[i]->actions.erase(proc->
syncs[i]->actions.begin() + (j--));
130 if (proc->
syncs[i]->actions.size() == 0) {
131 delete proc->
syncs[i];
132 proc->
syncs.erase(proc->
syncs.begin() + (i--));
135 while (did_something) {
136 did_something =
false;
140 log(
"Found and cleaned up %d empty switch%s in `%s.%s'.\n", count, count == 1 ?
"" :
"es", mod->
name.
c_str(), proc->
name.
c_str());
141 total_count += count;
const char * c_str() const
USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN bool did_something
YOSYS_NAMESPACE_BEGIN void proc_clean_case(RTLIL::CaseRule *cs, bool &did_something, int &count, int max_depth)
void log(const char *format,...)
std::vector< RTLIL::SyncRule * > syncs
RTLIL_ATTRIBUTE_MEMBERS RTLIL::CaseRule root_case
Definition at line 99 of file proc_clean.cc.
101 for (
size_t i = 0; i < cs->
actions.size(); i++) {
102 if (cs->
actions[i].first.size() == 0) {
107 for (
size_t i = 0; i < cs->
switches.size(); i++) {
109 if (sw->
cases.size() == 0) {
114 }
else if (max_depth != 0)
YOSYS_NAMESPACE_END USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN void proc_clean_switch(RTLIL::SwitchRule *sw, RTLIL::CaseRule *parent, bool &did_something, int &count, int max_depth)
RTLIL_ATTRIBUTE_MEMBERS std::vector< RTLIL::CaseRule * > cases
USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN bool did_something
std::vector< RTLIL::SigSig > actions
std::vector< RTLIL::SwitchRule * > switches
Definition at line 32 of file proc_clean.cc.
36 int found_matching_case_idx = -1;
37 for (
int i = 0; i < int(sw->
cases.size()) && found_matching_case_idx < 0; i++)
42 for (
int j = 0; j < int(cs->
compare.size()); j++) {
48 found_matching_case_idx = i;
53 if (cs->
compare.size() == 0 && found_matching_case_idx < 0) {
58 while (found_matching_case_idx >= 0 &&
int(sw->
cases.size()) > found_matching_case_idx+1) {
59 delete sw->
cases.back();
62 if (found_matching_case_idx == 0)
66 if (parent->
switches.front() == sw && sw->
cases.size() == 1 &&
70 for (
auto &action : sw->
cases[0]->actions)
71 parent->
actions.push_back(action);
72 for (
auto sw2 : sw->
cases[0]->switches)
74 sw->
cases[0]->switches.clear();
80 bool all_cases_are_empty =
true;
81 for (
auto cs : sw->
cases) {
83 all_cases_are_empty =
false;
87 if (all_cases_are_empty) {
89 for (
auto cs : sw->
cases)
RTLIL_ATTRIBUTE_MEMBERS std::vector< RTLIL::CaseRule * > cases
std::vector< RTLIL::SigSpec > compare
USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN bool did_something
YOSYS_NAMESPACE_BEGIN void proc_clean_case(RTLIL::CaseRule *cs, bool &did_something, int &count, int max_depth)
bool is_fully_const() const
std::vector< RTLIL::SigSig > actions
std::vector< RTLIL::SwitchRule * > switches