88 bool got_mode =
false;
89 bool reset_mode =
false;
90 bool push_mode =
false;
91 bool pop_mode =
false;
93 std::string save_name, load_name, as_name;
94 std::vector<RTLIL::Module*> copy_src_modules;
97 for (argidx = 1; argidx <
args.size(); argidx++)
99 std::string arg =
args[argidx];
100 if (!got_mode &&
args[argidx] ==
"-reset") {
105 if (!got_mode &&
args[argidx] ==
"-push") {
110 if (!got_mode &&
args[argidx] ==
"-pop") {
115 if (!got_mode &&
args[argidx] ==
"-save" && argidx+1 <
args.size()) {
117 save_name =
args[++argidx];
120 if (!got_mode &&
args[argidx] ==
"-stash" && argidx+1 <
args.size()) {
122 save_name =
args[++argidx];
126 if (!got_mode &&
args[argidx] ==
"-load" && argidx+1 <
args.size()) {
128 load_name =
args[++argidx];
130 log_cmd_error(
"No saved design '%s' found!\n", load_name.c_str());
133 if (!got_mode &&
args[argidx] ==
"-copy-from" && argidx+1 <
args.size()) {
138 copy_to_design = design;
141 if (!got_mode &&
args[argidx] ==
"-copy-to" && argidx+1 <
args.size()) {
146 copy_from_design = design;
149 if (copy_from_design !=
NULL &&
args[argidx] ==
"-as" && argidx+1 <
args.size()) {
151 as_name =
args[++argidx];
157 if (copy_from_design !=
NULL)
159 if (copy_from_design != design && argidx ==
args.size())
163 if (argidx !=
args.size()) {
167 argidx =
args.size();
170 for (
auto &it : copy_from_design->
modules_) {
171 if (sel.selected_whole_module(it.first)) {
172 copy_src_modules.push_back(it.second);
175 if (sel.selected_module(it.first))
188 if (copy_to_design !=
NULL)
190 if (!as_name.empty() && copy_src_modules.size() > 1)
191 log_cmd_error(
"Only one module can be selected in combination with -as.\n");
193 for (
auto mod : copy_src_modules)
195 std::string trg_name = as_name.empty() ? mod->name.str() :
RTLIL::escape_id(as_name);
197 if (copy_to_design->modules_.count(trg_name))
198 delete copy_to_design->modules_.at(trg_name);
199 copy_to_design->modules_[trg_name] = mod->clone();
200 copy_to_design->modules_[trg_name]->name = trg_name;
201 copy_to_design->modules_[trg_name]->design = copy_to_design;
205 if (!save_name.empty() || push_mode)
210 design_copy->
add(it.second->clone());
225 if (reset_mode || !load_name.empty() || push_mode || pop_mode)
238 if (!load_name.empty() || pop_mode)
245 for (
auto &it : saved_design->
modules_)
246 design->
add(it.second->clone());
void cmd_error(const std::vector< std::string > &args, size_t argidx, std::string msg)
std::vector< RTLIL::Selection > selection_stack
void handle_extra_select_args(Pass *pass, std::vector< std::string > args, size_t argidx, size_t args_size, RTLIL::Design *design)
void add(RTLIL::Module *module)
static std::string escape_id(std::string str)
std::map< RTLIL::IdString, RTLIL::Selection > selection_vars
std::vector< RTLIL::Design * > pushed_designs
YOSYS_NAMESPACE_BEGIN std::map< std::string, RTLIL::Design * > saved_designs
static const char * id2cstr(const RTLIL::IdString &str)
void log_cmd_error(const char *format,...)
std::map< RTLIL::IdString, RTLIL::Module * > modules_
std::string selected_active_module
void extra_args(std::vector< std::string > args, size_t argidx, RTLIL::Design *design, bool select=true)