SynthXilinxPass Struct Reference

Inheritance diagram for SynthXilinxPass:

Collaboration diagram for SynthXilinxPass:

Public Member Functions
	SynthXilinxPass ()
virtual void	help ()
virtual void	execute (std::vector< std::string > args, RTLIL::Design *design)
pre_post_exec_state_t	pre_execute ()
void	post_execute (pre_post_exec_state_t state)
void	cmd_log_args (const std::vector< std::string > &args)
void	cmd_error (const std::vector< std::string > &args, size_t argidx, std::string msg)
void	extra_args (std::vector< std::string > args, size_t argidx, RTLIL::Design *design, bool select=true)
virtual void	run_register ()

Static Public Member Functions
static void	call (RTLIL::Design *design, std::string command)
static void	call (RTLIL::Design *design, std::vector< std::string > args)
static void	call_on_selection (RTLIL::Design *design, const RTLIL::Selection &selection, std::string command)
static void	call_on_selection (RTLIL::Design *design, const RTLIL::Selection &selection, std::vector< std::string > args)
static void	call_on_module (RTLIL::Design *design, RTLIL::Module *module, std::string command)
static void	call_on_module (RTLIL::Design *design, RTLIL::Module *module, std::vector< std::string > args)
static void	init_register ()
static void	done_register ()

Data Fields
std::string	pass_name
std::string	short_help
int	call_counter
int64_t	runtime_ns
Pass *	next_queued_pass

Detailed Description

Definition at line 37 of file synth_xilinx.cc.

Constructor & Destructor Documentation

SynthXilinxPass::SynthXilinxPass ( )

inline

Definition at line 38 of file synth_xilinx.cc.

: Pass("synth_xilinx", "synthesis for Xilinx FPGAs") { }

Member Function Documentation

void Pass::call ( RTLIL::Design *  design, std::string  command  )

staticinherited

Definition at line 146 of file register.cc.

{
    std::vector<std::string> args;

    std::string cmd_buf = command;
    std::string tok = next_token(cmd_buf, " \t\r\n");

    if (tok.empty() || tok[0] == '#')
        return;

    if (tok[0] == '!') {
        cmd_buf = command.substr(command.find('!') + 1);
        while (!cmd_buf.empty() && (cmd_buf.back() == ' ' || cmd_buf.back() == '\t' ||
                cmd_buf.back() == '\r' || cmd_buf.back() == '\n'))
            cmd_buf.resize(cmd_buf.size()-1);
        log_header("Shell command: %s\n", cmd_buf.c_str());
        int retCode = run_command(cmd_buf);
        if (retCode != 0)
            log_cmd_error("Shell command returned error code %d.\n", retCode);
        return;
    }

    while (!tok.empty()) {
        if (tok == "#")
            break;
        if (tok.back() == ';') {
            int num_semikolon = 0;
            while (!tok.empty() && tok.back() == ';')
                tok.resize(tok.size()-1), num_semikolon++;
            if (!tok.empty())
                args.push_back(tok);
            call(design, args);
            args.clear();
            if (num_semikolon == 2)
                call(design, "clean");
            if (num_semikolon == 3)
                call(design, "clean -purge");
        } else
            args.push_back(tok);
        tok = next_token(cmd_buf, " \t\r\n");
    }

    call(design, args);
}

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void Pass::call ( RTLIL::Design *  design, std::vector< std::string >  args  )

staticinherited

Definition at line 191 of file register.cc.

{
    if (args.size() == 0 || args[0][0] == '#')
        return;

    if (echo_mode) {
        log("%s", create_prompt(design, 0));
        for (size_t i = 0; i < args.size(); i++)
            log("%s%s", i ? " " : "", args[i].c_str());
        log("\n");
    }

    if (pass_register.count(args[0]) == 0)
        log_cmd_error("No such command: %s (type 'help' for a command overview)\n", args[0].c_str());

    size_t orig_sel_stack_pos = design->selection_stack.size();
    auto state = pass_register[args[0]]->pre_execute();
    pass_register[args[0]]->execute(args, design);
    pass_register[args[0]]->post_execute(state);
    while (design->selection_stack.size() > orig_sel_stack_pos)
        design->selection_stack.pop_back();

    design->check();
}

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void Pass::call_on_module ( RTLIL::Design *  design, RTLIL::Module *  module, std::string  command  )

staticinherited

Definition at line 240 of file register.cc.

{
    std::string backup_selected_active_module = design->selected_active_module;
    design->selected_active_module = module->name.str();
    design->selection_stack.push_back(RTLIL::Selection(false));
    design->selection_stack.back().select(module);

    Pass::call(design, command);

    design->selection_stack.pop_back();
    design->selected_active_module = backup_selected_active_module;
}

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void Pass::call_on_module ( RTLIL::Design *  design, RTLIL::Module *  module, std::vector< std::string >  args  )

staticinherited

Definition at line 253 of file register.cc.

{
    std::string backup_selected_active_module = design->selected_active_module;
    design->selected_active_module = module->name.str();
    design->selection_stack.push_back(RTLIL::Selection(false));
    design->selection_stack.back().select(module);

    Pass::call(design, args);

    design->selection_stack.pop_back();
    design->selected_active_module = backup_selected_active_module;
}

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void Pass::call_on_selection ( RTLIL::Design *  design, const RTLIL::Selection &  selection, std::string  command  )

staticinherited

Definition at line 216 of file register.cc.

{
    std::string backup_selected_active_module = design->selected_active_module;
    design->selected_active_module.clear();
    design->selection_stack.push_back(selection);

    Pass::call(design, command);

    design->selection_stack.pop_back();
    design->selected_active_module = backup_selected_active_module;
}

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void Pass::call_on_selection ( RTLIL::Design *  design, const RTLIL::Selection &  selection, std::vector< std::string >  args  )

staticinherited

Definition at line 228 of file register.cc.

{
    std::string backup_selected_active_module = design->selected_active_module;
    design->selected_active_module.clear();
    design->selection_stack.push_back(selection);

    Pass::call(design, args);

    design->selection_stack.pop_back();
    design->selected_active_module = backup_selected_active_module;
}

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void Pass::cmd_error ( const std::vector< std::string > &  args, size_t  argidx, std::string  msg  )

inherited

Definition at line 110 of file register.cc.

{
    std::string command_text;
    int error_pos = 0;

    for (size_t i = 0; i < args.size(); i++) {
        if (i < argidx)
            error_pos += args[i].size() + 1;
        command_text = command_text + (command_text.empty() ? "" : " ") + args[i];
    }

    log("\nSyntax error in command `%s':\n", command_text.c_str());
    help();

    log_cmd_error("Command syntax error: %s\n> %s\n> %*s^\n",
            msg.c_str(), command_text.c_str(), error_pos, "");
}

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void Pass::cmd_log_args ( const std::vector< std::string > &  args )

inherited

Definition at line 100 of file register.cc.

{
    if (args.size() <= 1)
        return;
    log("Full command line:");
    for (size_t i = 0; i < args.size(); i++)
        log(" %s", args[i].c_str());
    log("\n");
}

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void Pass::done_register ( )

staticinherited

Definition at line 62 of file register.cc.

{
    frontend_register.clear();
    pass_register.clear();
    backend_register.clear();
    log_assert(first_queued_pass == NULL);
}

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virtual void SynthXilinxPass::execute ( std::vector< std::string >  args, RTLIL::Design *  design  )

inlinevirtual

Implements Pass.

Definition at line 103 of file synth_xilinx.cc.

    {
        std::string top_module = "top";
        std::string arch_name = "spartan6";
        std::string edif_file;
        std::string run_from, run_to;

        size_t argidx;
        for (argidx = 1; argidx < args.size(); argidx++)
        {
            if (args[argidx] == "-top" && argidx+1 < args.size()) {
                top_module = args[++argidx];
                continue;
            }
            if (args[argidx] == "-arch" && argidx+1 < args.size()) {
                arch_name = args[++argidx];
                continue;
            }
            if (args[argidx] == "-edif" && argidx+1 < args.size()) {
                edif_file = args[++argidx];
                continue;
            }
            if (args[argidx] == "-run" && argidx+1 < args.size()) {
                size_t pos = args[argidx+1].find(':');
                if (pos == std::string::npos)
                    break;
                run_from = args[++argidx].substr(0, pos);
                run_to = args[argidx].substr(pos+1);
                continue;
            }
            break;
        }
        extra_args(args, argidx, design);

        if (!design->full_selection())
            log_cmd_error("This comannd only operates on fully selected designs!\n");

        if (arch_name == "spartan6") {
            /* set flags */
        } else
        if (arch_name == "artix7") {
            /* set flags */
        } else
        if (arch_name == "kintex7") {
            /* set flags */
        } else
        if (arch_name == "zynq7000") {
            /* set flags */
        } else
            log_cmd_error("Architecture '%s' is not supported!\n", arch_name.c_str());

        bool active = run_from.empty();

        log_header("Executing SYNTH_XILINX pass.\n");
        log_push();

        if (check_label(active, run_from, run_to, "begin"))
        {
            Pass::call(design, stringf("hierarchy -check -top %s", top_module.c_str()));
        }

        if (check_label(active, run_from, run_to, "coarse"))
        {
            Pass::call(design, "proc");
            Pass::call(design, "opt");
            Pass::call(design, "memory");
            Pass::call(design, "clean");
            Pass::call(design, "fsm");
            Pass::call(design, "opt");
        }

        if (check_label(active, run_from, run_to, "fine"))
        {
            Pass::call(design, "techmap");
            Pass::call(design, "opt");
        }

        if (check_label(active, run_from, run_to, "map_luts"))
        {
            Pass::call(design, "abc -lut 6");
            Pass::call(design, "clean");
        }

        if (check_label(active, run_from, run_to, "map_cells"))
        {
            Pass::call(design, "techmap -share_map xilinx/cells.v");
            Pass::call(design, "clean");
        }

        if (check_label(active, run_from, run_to, "clkbuf"))
        {
            Pass::call(design, stringf("select -set xilinx_clocks %s/t:FDRE %%x:+FDRE[C] %s/t:FDRE %%d", top_module.c_str(), top_module.c_str()));
            Pass::call(design, "iopadmap -inpad BUFGP O:I @xilinx_clocks");
        }

        if (check_label(active, run_from, run_to, "iobuf"))
        {
            Pass::call(design, stringf("select -set xilinx_nonclocks %s/w:* %s/t:BUFGP %%x:+BUFGP[I] %%d", top_module.c_str(), top_module.c_str()));
            Pass::call(design, "iopadmap -outpad OBUF I:O -inpad IBUF O:I @xilinx_nonclocks");
        }

        if (check_label(active, run_from, run_to, "edif"))
        {
            if (!edif_file.empty())
                Pass::call(design, stringf("write_edif %s", edif_file.c_str()));
        }

        log_pop();
    }

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void Pass::extra_args ( std::vector< std::string >  args, size_t  argidx, RTLIL::Design *  design, bool  select = true  )

inherited

Definition at line 128 of file register.cc.

{
    for (; argidx < args.size(); argidx++)
    {
        std::string arg = args[argidx];

        if (arg.substr(0, 1) == "-")
            cmd_error(args, argidx, "Unknown option or option in arguments.");

        if (!select)
            cmd_error(args, argidx, "Extra argument.");

        handle_extra_select_args(this, args, argidx, args.size(), design);
        break;
    }
    // cmd_log_args(args);
}

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virtual void SynthXilinxPass::help ( )

inlinevirtual

Reimplemented from Pass.

Definition at line 39 of file synth_xilinx.cc.

    {
        //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
        log("\n");
        log("    synth_xilinx [options]\n");
        log("\n");
        log("This command runs synthesis for Xilinx FPGAs. This command does not operate on\n");
        log("partly selected designs.\n");
        log("\n");
        log("    -top <module>\n");
        log("        use the specified module as top module (default='top')\n");
        log("\n");
        log("    -arch <arch>\n");
        log("        select architecture. the following architectures are supported:\n");
        log("            spartan6 (default), artix7, kintex7, virtex7, zynq7000\n");
        log("            (this parameter is not used by the command at the moment)\n");
        log("\n");
        log("    -edif <file>\n");
        log("        write the design to the specified edif file. writing of an output file\n");
        log("        is omitted if this parameter is not specified.\n");
        log("\n");
        log("    -run <from_label>:<to_label>\n");
        log("        only run the commands between the labels (see below). an empty\n");
        log("        from label is synonymous to 'begin', and empty to label is\n");
        log("        synonymous to the end of the command list.\n");
        log("\n");
        log("\n");
        log("The following commands are executed by this synthesis command:\n");
        log("\n");
        log("    begin:\n");
        log("        hierarchy -check -top <top>\n");
        log("\n");
        log("    coarse:\n");
        log("        proc\n");
        log("        opt\n");
        log("        memory\n");
        log("        clean\n");
        log("        fsm\n");
        log("        opt\n");
        log("\n");
        log("    fine:\n");
        log("        techmap\n");
        log("        opt\n");
        log("\n");
        log("    map_luts:\n");
        log("        abc -lut 6\n");
        log("        clean\n");
        log("\n");
        log("    map_cells:\n");
        log("        techmap -share_map xilinx/cells.v\n");
        log("        clean\n");
        log("\n");
        log("    clkbuf:\n");
        log("        select -set xilinx_clocks <top>/t:FDRE %%x:+FDRE[C] <top>/t:FDRE %%d\n");
        log("        iopadmap -inpad BUFGP O:I @xilinx_clocks\n");
        log("\n");
        log("    iobuf:\n");
        log("        select -set xilinx_nonclocks <top>/w:* <top>/t:BUFGP %%x:+BUFGP[I] %%d\n");
        log("        iopadmap -outpad OBUF I:O -inpad IBUF O:I @xilinx_nonclocks\n");
        log("\n");
        log("    edif:\n");
        log("        write_edif synth.edif\n");
        log("\n");
    }

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void Pass::init_register ( )

staticinherited

Definition at line 54 of file register.cc.

{
    while (first_queued_pass) {
        first_queued_pass->run_register();
        first_queued_pass = first_queued_pass->next_queued_pass;
    }
}

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void Pass::post_execute ( Pass::pre_post_exec_state_t  state )

inherited

Definition at line 84 of file register.cc.

{
    int64_t time_ns = PerformanceTimer::query() - state.begin_ns;
    runtime_ns += time_ns;
    current_pass = state.parent_pass;
    if (current_pass)
        current_pass->runtime_ns -= time_ns;
}

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Pass::pre_post_exec_state_t Pass::pre_execute ( )

inherited

Definition at line 74 of file register.cc.

{
    pre_post_exec_state_t state;
    call_counter++;
    state.begin_ns = PerformanceTimer::query();
    state.parent_pass = current_pass;
    current_pass = this;
    return state;
}

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void Pass::run_register ( )

virtualinherited

Reimplemented in Backend, and Frontend.

Definition at line 48 of file register.cc.

{
    log_assert(pass_register.count(pass_name) == 0);
    pass_register[pass_name] = this;
}

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Field Documentation

int Pass::call_counter

inherited

Definition at line 36 of file register.h.

Pass* Pass::next_queued_pass

inherited

Definition at line 60 of file register.h.

std::string Pass::pass_name

inherited

Definition at line 29 of file register.h.

int64_t Pass::runtime_ns

inherited

Definition at line 37 of file register.h.

std::string Pass::short_help

inherited

Definition at line 29 of file register.h.

---

The documentation for this struct was generated from the following file:

• synth_xilinx.cc