Inheritance diagram for Vhdl2verilogPass:

Collaboration diagram for Vhdl2verilogPass:

Public Member Functions
	Vhdl2verilogPass ()

virtual void	help ()

virtual void	execute (std::vector< std::string > args, RTLIL::Design *design)

pre_post_exec_state_t	pre_execute ()

void	post_execute (pre_post_exec_state_t state)

void	cmd_log_args (const std::vector< std::string > &args)

void	cmd_error (const std::vector< std::string > &args, size_t argidx, std::string msg)

void	extra_args (std::vector< std::string > args, size_t argidx, RTLIL::Design *design, bool select=true)

virtual void	run_register ()

Static Public Member Functions
static void	call (RTLIL::Design *design, std::string command)

static void	call (RTLIL::Design *design, std::vector< std::string > args)

static void	call_on_selection (RTLIL::Design *design, const RTLIL::Selection &selection, std::string command)

static void	call_on_selection (RTLIL::Design *design, const RTLIL::Selection &selection, std::vector< std::string > args)

static void	call_on_module (RTLIL::Design design, RTLIL::Module module, std::string command)

static void	call_on_module (RTLIL::Design design, RTLIL::Module module, std::vector< std::string > args)

static void	init_register ()

static void	done_register ()

Data Fields
std::string	pass_name

std::string	short_help

int	call_counter

int64_t	runtime_ns

Pass *	next_queued_pass

Detailed Description

Definition at line 36 of file vhdl2verilog.cc.

Constructor & Destructor Documentation

Vhdl2verilogPass::Vhdl2verilogPass ( )

inline

Definition at line 37 of file vhdl2verilog.cc.

37 : Pass("vhdl2verilog", "importing VHDL designs using vhdl2verilog") { }

Pass::Pass

Pass(std::string name, std::string short_help="** document me **")

Definition: register.cc:40

Member Function Documentation

void Pass::call	(	RTLIL::Design *	design,
		std::string	command
	)

staticinherited

Definition at line 146 of file register.cc.

 {
     std::vector<std::string> args;
 
     std::string cmd_buf = command;
     std::string tok = next_token(cmd_buf, " \t\r\n");
 
     if (tok.empty() || tok[0] == '#')
         return;
 
     if (tok[0] == '!') {
         cmd_buf = command.substr(command.find('!') + 1);
         while (!cmd_buf.empty() && (cmd_buf.back() == ' ' || cmd_buf.back() == '\t' ||
                 cmd_buf.back() == '\r' || cmd_buf.back() == '\n'))
             cmd_buf.resize(cmd_buf.size()-1);
         log_header("Shell command: %s\n", cmd_buf.c_str());
         int retCode = run_command(cmd_buf);
         if (retCode != 0)
             log_cmd_error("Shell command returned error code %d.\n", retCode);
         return;
     }
 
     while (!tok.empty()) {
         if (tok == "#")
             break;
         if (tok.back() == ';') {
             int num_semikolon = 0;
             while (!tok.empty() && tok.back() == ';')
                 tok.resize(tok.size()-1), num_semikolon++;
             if (!tok.empty())
                 args.push_back(tok);
             call(design, args);
             args.clear();
             if (num_semikolon == 2)
                 call(design, "clean");
             if (num_semikolon == 3)
                 call(design, "clean -purge");
         } else
             args.push_back(tok);
         tok = next_token(cmd_buf, " \t\r\n");
     }
 
     call(design, args);
 }

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void Pass::call	(	RTLIL::Design *	design,
		std::vector< std::string >	args
	)

staticinherited

Definition at line 191 of file register.cc.

 {
     if (args.size() == 0 || args[0][0] == '#')
         return;
 
     if (echo_mode) {
         log("%s", create_prompt(design, 0));
         for (size_t i = 0; i < args.size(); i++)
             log("%s%s", i ? " " : "", args[i].c_str());
         log("\n");
     }
 
     if (pass_register.count(args[0]) == 0)
         log_cmd_error("No such command: %s (type 'help' for a command overview)\n", args[0].c_str());
 
     size_t orig_sel_stack_pos = design->selection_stack.size();
     auto state = pass_register[args[0]]->pre_execute();
     pass_register[args[0]]->execute(args, design);
     pass_register[args[0]]->post_execute(state);
     while (design->selection_stack.size() > orig_sel_stack_pos)
         design->selection_stack.pop_back();
 
     design->check();
 }

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void Pass::call_on_module	(	RTLIL::Design *	design,
		RTLIL::Module *	module,
		std::string	command
	)

staticinherited

Definition at line 240 of file register.cc.

 {
     std::string backup_selected_active_module = design->selected_active_module;
     design->selected_active_module = module->name.str();
     design->selection_stack.push_back(RTLIL::Selection(false));
     design->selection_stack.back().select(module);
 
     Pass::call(design, command);
 
     design->selection_stack.pop_back();
     design->selected_active_module = backup_selected_active_module;
 }

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void Pass::call_on_module	(	RTLIL::Design *	design,
		RTLIL::Module *	module,
		std::vector< std::string >	args
	)

staticinherited

Definition at line 253 of file register.cc.

 {
     std::string backup_selected_active_module = design->selected_active_module;
     design->selected_active_module = module->name.str();
     design->selection_stack.push_back(RTLIL::Selection(false));
     design->selection_stack.back().select(module);
 
     Pass::call(design, args);
 
     design->selection_stack.pop_back();
     design->selected_active_module = backup_selected_active_module;
 }

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void Pass::call_on_selection	(	RTLIL::Design *	design,
		const RTLIL::Selection &	selection,
		std::string	command
	)

staticinherited

Definition at line 216 of file register.cc.

 {
     std::string backup_selected_active_module = design->selected_active_module;
     design->selected_active_module.clear();
     design->selection_stack.push_back(selection);
 
     Pass::call(design, command);
 
     design->selection_stack.pop_back();
     design->selected_active_module = backup_selected_active_module;
 }

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void Pass::call_on_selection	(	RTLIL::Design *	design,
		const RTLIL::Selection &	selection,
		std::vector< std::string >	args
	)

staticinherited

Definition at line 228 of file register.cc.

 {
     std::string backup_selected_active_module = design->selected_active_module;
     design->selected_active_module.clear();
     design->selection_stack.push_back(selection);
 
     Pass::call(design, args);
 
     design->selection_stack.pop_back();
     design->selected_active_module = backup_selected_active_module;
 }

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void Pass::cmd_error	(	const std::vector< std::string > &	args,
		size_t	argidx,
		std::string	msg
	)

inherited

Definition at line 110 of file register.cc.

 {
     std::string command_text;
     int error_pos = 0;
 
     for (size_t i = 0; i < args.size(); i++) {
         if (i < argidx)
             error_pos += args[i].size() + 1;
         command_text = command_text + (command_text.empty() ? "" : " ") + args[i];
     }
 
     log("\nSyntax error in command `%s':\n", command_text.c_str());
     help();
 
     log_cmd_error("Command syntax error: %s\n> %s\n> %*s^\n",
             msg.c_str(), command_text.c_str(), error_pos, "");
 }

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void Pass::cmd_log_args ( const std::vector< std::string > & args )

inherited

Definition at line 100 of file register.cc.

 {
     if (args.size() <= 1)
         return;
     log("Full command line:");
     for (size_t i = 0; i < args.size(); i++)
         log(" %s", args[i].c_str());
     log("\n");
 }

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void Pass::done_register ( )

staticinherited

Definition at line 62 of file register.cc.

 {
     frontend_register.clear();
     pass_register.clear();
     backend_register.clear();
     log_assert(first_queued_pass == NULL);
 }

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virtual void Vhdl2verilogPass::execute	(	std::vector< std::string >	args,
		RTLIL::Design *	design
	)

inlinevirtual

Implements Pass.

Definition at line 75 of file vhdl2verilog.cc.

     {
         log_header("Executing VHDL2VERILOG (importing VHDL designs using vhdl2verilog).\n");
         log_push();
 
         std::string out_file, top_entity;
         std::string vhdl2verilog_dir;
         std::string extra_opts;
 
         size_t argidx;
         for (argidx = 1; argidx < args.size(); argidx++) {
             if (args[argidx] == "-out" && argidx+1 < args.size()) {
                 out_file = args[++argidx];
                 continue;
             }
             if (args[argidx] == "-top" && argidx+1 < args.size()) {
                 top_entity = args[++argidx];
                 continue;
             }
             if (args[argidx] == "-vhdl2verilog_dir" && argidx+1 < args.size()) {
                 vhdl2verilog_dir = args[++argidx];
                 continue;
             }
             if ((args[argidx] == "-arch" || args[argidx] == "-suppress" || args[argidx] == "-mapfile") && argidx+1 < args.size()) {
                 if (args[argidx] == "-mapfile" && !args[argidx+1].empty() && args[argidx+1][0] != '/') {
                     char pwd[PATH_MAX];
                     if (!getcwd(pwd, sizeof(pwd))) {
                         log_cmd_error("getcwd failed: %s", strerror(errno));
                         log_abort();
                     }
                     args[argidx+1] = pwd + ("/" + args[argidx+1]);
                 }
                 extra_opts += std::string(" ") + args[argidx];
                 extra_opts += std::string(" '") + args[++argidx] + std::string("'");
                 continue;
             }
             if (args[argidx] == "-unroll_generate" || args[argidx] == "-nogenericeval" || args[argidx] == "-nouniquify" ||
                     args[argidx] == "-oldparser" || args[argidx] == "-quiet" || args[argidx] == "-nobanner") {
                 extra_opts += std::string(" ") + args[argidx];
                 continue;
             }
             break;
         }
 
         if (argidx == args.size())
             cmd_error(args, argidx, "Missing filenames.");
         if (args[argidx].substr(0, 1) == "-")
             cmd_error(args, argidx, "Unknown option.");
         if (top_entity.empty())
             log_cmd_error("Missing -top option.\n");
 
         std::string tempdir_name = make_temp_dir("/tmp/yosys-vhdl2verilog-XXXXXX");
         log("Using temp directory %s.\n", tempdir_name.c_str());
 
         if (!out_file.empty() && out_file[0] != '/') {
             char pwd[PATH_MAX];
             if (!getcwd(pwd, sizeof(pwd))) {
                 log_cmd_error("getcwd failed: %s", strerror(errno));
                 log_abort();
             }
             out_file = pwd + ("/" + out_file);
         }
 
         FILE *f = fopen(stringf("%s/files.list", tempdir_name.c_str()).c_str(), "wt");
         while (argidx < args.size()) {
             std::string file = args[argidx++];
             if (file.empty())
                 continue;
             if (file[0] != '/') {
                 char pwd[PATH_MAX];
                 if (!getcwd(pwd, sizeof(pwd))) {
                     log_cmd_error("getcwd failed: %s", strerror(errno));
                     log_abort();
                 }
                 file = pwd + ("/" + file);
             }
             fprintf(f, "%s\n", file.c_str());
             log("Adding '%s' to the file list.\n", file.c_str());
         }
         fclose(f);
 
         std::string command = "exec 2>&1; ";
         if (!vhdl2verilog_dir.empty())
             command += stringf("cd '%s'; . ./setup_env.sh; ", vhdl2verilog_dir.c_str());
         command += stringf("cd '%s'; vhdl2verilog -out '%s' -filelist files.list -top '%s'%s", tempdir_name.c_str(),
                 out_file.empty() ? "vhdl2verilog_output.v" : out_file.c_str(), top_entity.c_str(), extra_opts.c_str());
 
         log("Running '%s'..\n", command.c_str());
 
         int ret = run_command(command, [](const std::string &line) { log("%s", line.c_str()); });
         if (ret != 0)
             log_error("Execution of command \"%s\" failed: return code %d.\n", command.c_str(), ret);
 
         if (out_file.empty()) {
             std::ifstream ff;
             ff.open(stringf("%s/vhdl2verilog_output.v", tempdir_name.c_str()).c_str());
             if (ff.fail())
                 log_error("Can't open vhdl2verilog output file `vhdl2verilog_output.v'.\n");
             Frontend::frontend_call(design, &ff, stringf("%s/vhdl2verilog_output.v", tempdir_name.c_str()), "verilog");
         }
 
         log_header("Removing temp directory `%s':\n", tempdir_name.c_str());
         remove_directory(tempdir_name);
         log_pop();
     }

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void Pass::extra_args	(	std::vector< std::string >	args,
		size_t	argidx,
		RTLIL::Design *	design,
		bool	select = `true`
	)

inherited

Definition at line 128 of file register.cc.

 {
     for (; argidx < args.size(); argidx++)
     {
         std::string arg = args[argidx];
 
         if (arg.substr(0, 1) == "-")
             cmd_error(args, argidx, "Unknown option or option in arguments.");
 
         if (!select)
             cmd_error(args, argidx, "Extra argument.");
 
         handle_extra_select_args(this, args, argidx, args.size(), design);
         break;
     }
     // cmd_log_args(args);
 }

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virtual void Vhdl2verilogPass::help ( )

inlinevirtual

Reimplemented from Pass.

Definition at line 38 of file vhdl2verilog.cc.

     {
         //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
         log("\n");
         log("    vhdl2verilog [options] <vhdl-file>..\n");
         log("\n");
         log("This command reads VHDL source files using the 'vhdl2verilog' tool and the\n");
         log("Yosys Verilog frontend.\n");
         log("\n");
         log("    -out <out_file>\n");
         log("        do not import the vhdl2verilog output. instead write it to the\n");
         log("        specified file.\n");
         log("\n");
         log("    -vhdl2verilog_dir <directory>\n");
         log("        do use the specified vhdl2verilog installation. this is the directory\n");
         log("        that contains the setup_env.sh file. when this option is not present,\n");
         log("        it is assumed that vhdl2verilog is in the PATH environment variable.\n");
         log("\n");
         log("    -top <top-entity-name>\n");
         log("        The name of the top entity. This option is mandatory.\n");
         log("\n");
         log("The following options are passed as-is to vhdl2verilog:\n");
         log("\n");
         log("    -arch <architecture_name>\n");
         log("    -unroll_generate\n");
         log("    -nogenericeval\n");
         log("    -nouniquify\n");
         log("    -oldparser\n");
         log("    -suppress <list>\n");
         log("    -quiet\n");
         log("    -nobanner\n");
         log("    -mapfile <file>\n");
         log("\n");
         log("vhdl2verilog can be obtained from:\n");
         log("http://www.edautils.com/vhdl2verilog.html\n");
         log("\n");
     }

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void Pass::init_register ( )

staticinherited

Definition at line 54 of file register.cc.

 {
     while (first_queued_pass) {
         first_queued_pass->run_register();
         first_queued_pass = first_queued_pass->next_queued_pass;
     }
 }

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void Pass::post_execute ( Pass::pre_post_exec_state_t state )

inherited

Definition at line 84 of file register.cc.

 {
     int64_t time_ns = PerformanceTimer::query() - state.begin_ns;
     runtime_ns += time_ns;
     current_pass = state.parent_pass;
     if (current_pass)
         current_pass->runtime_ns -= time_ns;
 }

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Pass::pre_post_exec_state_t Pass::pre_execute ( )

inherited

Definition at line 74 of file register.cc.

 {
     pre_post_exec_state_t state;
     call_counter++;
     state.begin_ns = PerformanceTimer::query();
     state.parent_pass = current_pass;
     current_pass = this;
     return state;
 }

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void Pass::run_register ( )

virtualinherited

Reimplemented in Backend, and Frontend.

Definition at line 48 of file register.cc.

 {
     log_assert(pass_register.count(pass_name) == 0);
     pass_register[pass_name] = this;
 }

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Field Documentation

int Pass::call_counter

inherited

Definition at line 36 of file register.h.

Pass* Pass::next_queued_pass

inherited

Definition at line 60 of file register.h.

std::string Pass::pass_name

inherited

Definition at line 29 of file register.h.

int64_t Pass::runtime_ns

inherited

Definition at line 37 of file register.h.

std::string Pass::short_help

inherited

Definition at line 29 of file register.h.

The documentation for this struct was generated from the following file:

vhdl2verilog.cc

Public Member Functions

Static Public Member Functions

Data Fields

Detailed Description

Constructor & Destructor Documentation

Member Function Documentation

Field Documentation