torc::bitstream::Virtex7LibGen Class Reference

#include <Virtex7LibGen.hpp>

Inheritance diagram for torc::bitstream::Virtex7LibGen:

Collaboration diagram for torc::bitstream::Virtex7LibGen:

Public Types
typedef std::string	string
	Imported type name. More...
typedef boost::filesystem::path	path
	Imported type name. More...
typedef torc::architecture::DDB	DDB
	Imported type name. More...
typedef torc::architecture::Sites	Sites
	Imported type name. More...
typedef torc::architecture::Site	Site
	Imported type name. More...
typedef torc::architecture::Tiles	Tiles
	Imported type name. More...
typedef torc::architecture::TileInfo	TileInfo
	Imported type name. More...
typedef torc::architecture::xilinx::TileIndex	TileIndex
	Imported type name. More...
typedef torc::architecture::Tilewire	Tilewire
	Imported type name. More...
typedef torc::architecture::ExtendedWireInfo	ExtendedWireInfo
	Imported type name. More...
typedef torc::architecture::PrimitiveElement	PrimitiveElement
	Imported type name. More...
typedef torc::architecture::PrimitiveElementArray	PrimitiveElementArray
	Imported type name. More...
typedef torc::physical::DesignSharedPtr	DesignSharedPtr
	Imported type name. More...
typedef torc::physical::InstanceSharedPtr	InstanceSharedPtr
	Imported type name. More...
typedef torc::physical::NetSharedPtr	NetSharedPtr
	Imported type name. More...
typedef torc::packer::PrimitiveStructureSharedPtr	PrimitiveStructureSharedPtr
	Imported type name. More...
typedef torc::bitstream::BitstreamSharedPtr	BitstreamSharedPtr
	Imported type name. More...
typedef torc::bitstream::Assembler::ConfigValuesToBits	ConfigValuesToBits
typedef torc::bitstream::Assembler::ConfigSettingsToValues	ConfigSettingsToValues
typedef torc::bitstream::Assembler::SiteTypeToConfigSettings	SiteTypeToConfigSettings
typedef torc::bitstream::Assembler::TileTypeToSiteType	TileTypeToSiteType
typedef torc::bitstream::Assembler::CompoundSettingMap	CompoundSettingMap
	Map from one setting to vector of related setings. More...
typedef std::map< std::string, std::set< std::string > >	TileTypeToSiteTypeSet
	Typedef of map from tile type to set of site type. More...
typedef std::map< std::string, PrimitiveStructureSharedPtr >	PrimitiveStructuresSharedPtrMap
	Typedef of map from primitive name to primitive structure shared pointer. More...

Public Member Functions
	Virtex7LibGen (string inDevice, path inHarnessFolder, path inXdlGenerationFolder)
	Constructor. More...
virtual	~Virtex7LibGen ()
	Destructor. More...
void	generateLogicXdls ()
	Generrate Xdls for logic sites. More...
void	generateWireXdls ()
	Generate Xdls for routing pips. More...
void	generateLogicAndWireXdl ()
	Generate Xdls for both logic sites and routing pips. More...
void	generateBitstreams ()
	Generate bitstream for all Xdls in mXdlGenerationFolder and mXdlGenerationReferenceFolder. More...
void	compressBitFiles ()
	Compress all Xilinx bitfiles in mXdlGenerationFolder. More...
void	stitchMicroBitstreams ()
	Stitch micro-bitstreams in mXdlGenerationFolder. More...
TileTypeToSiteTypeSet	getTileTypeToSiteTypeMap (void)
	Populate map of tile type to set of include site types. More...
void	printTileTypeToSiteTypeMapInfo (TileTypeToSiteTypeSet tileTypeToSiteType)
	Print the tile type to site type information. More...

Static Public Member Functions
static CompoundSettingMap	getCompoundSettingsMap ()
	Returns map of coumpound settings. More...

Protected Member Functions
virtual bool	isSiteTypeSupported (const string &inSiteType)
	Returns true if site type is supported. More...
virtual std::vector< std::string >	getTilesSupportedForPips ()
	Returns list of supported tiles. Assumes last tile is "LAST_TILE". More...
virtual std::string	getRambPrimaryPrimitive ()
	Returns primary primitive for Ramb site type. More...
void	initialize ()
	Do architecture specific part of initialization. More...
std::map< string, string >	getReferenceConfigMap ()
	Get a map from config setting to reference value. More...
virtual string	getParentFamilyName ()
	Get parent family name. More...
virtual void	compressBitFile (path primaryFile, path referenceFile)
	Compress given bitstream file against reference bitstream file. More...
virtual uint32_t	getWordOffsetFromTileLocation (TileRow tileRow, TileCol tileCol, BitstreamSharedPtr inBitstreamPtr)
	Get word offset from tile row and col. More...
virtual PrimitiveStructuresSharedPtrMap	getPrimitiveNameToStructreMap ()
	Populate primitive name to primitive structure map. More...
virtual void	generateMemoryMicroBitstream ()
	Generate micro-bitstreams for memory elements like LUT in RAM mode. More...
void	exportTileSinks (TileIndex inTileIndex)
	Export all pips within the specified tile. More...
void	exportSink (Tilewire &inSource, Tilewire &inSink)
	Export a single pip. More...
bool	isSlicelType (const string &inSiteType)
	Return true if site type is SLICEL. More...
DesignSharedPtr	getHarnessDesignForSiteType (const string &inSiteType)
	Returns harness design pointer for the given site type. More...
string	getReferenceConfigValue (const string &inConfigSetting)
	Return config value which results in off bit in bitstream. More...
DesignSharedPtr	createEmptyDesignWithSameMetadata (DesignSharedPtr inDesignPtr)
	Create an empty design with same metadata. Does not copy configurations. More...
bool	isRambSite (const string &inSiteType)
	Returns true if input is a RAMB site. More...
bool	isDspSite (const string &inSiteType)
	Returns true is input is a DSP site. More...
bool	isCompoundSettingHead (const string &inSetting)
	Is given setting head of compound setting group. More...
void	createXdlsForConfigSetting (const torc::architecture::PrimitiveElement &inElement, PrimitiveStructureSharedPtr const inPrimitiveStructurePtr, const string &inSiteType, DesignSharedPtr inHarnessDesignPtr)
	Create Xdls for each config value of the config setting More...
void	createXdlForGeneralConfigSetting (const string &inConfigSetting, const string &inConfigVal, const string &inXdlFileNamePartial, DesignSharedPtr inHarnessDesignPtr)
	Set config value and create Xdl. More...
void	createRambBaseXdl (const string &inSiteType, DesignSharedPtr inHarnessDesignPtr)
	Create Xdl with a Ramb instane and no configuration. More...
void	createHexConfigXdl (const string &inConfigSetting, const string &inSiteType, int numHexChars, DesignSharedPtr inHarnessDesignPtr)
	Create Xdl for configurations which hex string values. More...
void	createXdlForCompoundSettings (const PrimitiveElement &inElement, const string &inSiteType, PrimitiveStructureSharedPtr inPrimitiveStructurePtr, DesignSharedPtr inHarnessDesignPtr)
	Create Xdls for compound settings. More...
void	createXdlForOrphanElements (const torc::architecture::PrimitiveElement &inElement, const string &inXdlFileNamePartial, DesignSharedPtr inHarnessDesignPtr)
	Create Xdls for orphan elements with empty reference Xdl. More...
void	createXdlForLut (const torc::architecture::PrimitiveElement &inElement, const string &inXdlFileNamePartial, DesignSharedPtr inHarnessDesignPtr)
	Create Xdl for Lut. More...
void	createReferenceXdlForConfigSetting (const string &inConfigSetting, DesignSharedPtr outHarnessDesignPtr, const string &inXdlFileNamePartial)
	Create reference Xdl for given config setting. More...
void	setConfigAndGenerateXdl (const string &inConfigSetting, const string &inConfigValue, const string &inXdlFileName, DesignSharedPtr inOutDesignPtr)
	Set given config and generate Xdl. More...
uint32_t	getWordOffsetFromXdlFile (path inBitstreamPath, BitstreamSharedPtr inBitstreamPtr)
	Get word offset in frame for the site/pip in corresponding Xdl. More...
int	getElementIndexFromName (const string inElementName, PrimitiveStructureSharedPtr inPrimitiveStructurePtr)
	Get index in Element array. More...
void	saveLibraryMapToFile (TileTypeToSiteType &inLibrary)
	Save library map to file. More...
std::map< string, string >	getDeviceToPackageMap ()
	Get a map from device to default package. More...

Protected Attributes
DDB &	mDB
	Database object. More...
const Sites &	mSites
	Sites from the database object. More...
const Tiles &	mTiles
	Tiles from the database object. More...
path	mHarnessFolder
	Harness folder. More...
path	mXdlGenerationFolder
	Folder in which Xdls will be generated. More...
path	mXdlGenerationReferenceFolder
	Folder in which reference Xdls will be genered. More...
path	mLibraryFolder
	Path to library folder. More...
CompoundSettingMap	mCompoundSettingMap
	Map from one compound setting to vector of other related settings. More...
std::map< string, string >	mDeviceToPackageMap
	Map from device to pakcage. More...
std::map< string, string >	mReferenceConfigMap
	Map from config setting to reference config value. More...
string	mCurTileType
	Tile type for which Xdl are being generated currently. More...

Static Protected Attributes
static const int	sCrcWordIndex = 50
	This have to be changed for different Family. More...
static const string	sTilesSupportedForPips []
	Array of supported routing tiles. More...
static const char *	sNameSeparator = "-"
	Symbol to separate out parts of file name. More...
static const char *	sConfigValueOff = "#OFF"
	Config value to switch off element (#OFF) More...
static const char *	sXdlExtension = ".xdl"
	.xdl More...
static const char *	sLibExtension = ".ldb"
	.ldb More...

Detailed Description

Definition at line 27 of file Virtex7LibGen.hpp.

Member Typedef Documentation

typedef torc::bitstream::BitstreamSharedPtr torc::bitstream::AssemblerLibGen::BitstreamSharedPtr

inherited

Imported type name.

Definition at line 73 of file AssemblerLibGen.hpp.

typedef torc::bitstream::Assembler::CompoundSettingMap torc::bitstream::AssemblerLibGen::CompoundSettingMap

inherited

Map from one setting to vector of related setings.

Definition at line 80 of file AssemblerLibGen.hpp.

typedef torc::bitstream::Assembler::ConfigSettingsToValues torc::bitstream::AssemblerLibGen::ConfigSettingsToValues

inherited

Definition at line 76 of file AssemblerLibGen.hpp.

typedef torc::bitstream::Assembler::ConfigValuesToBits torc::bitstream::AssemblerLibGen::ConfigValuesToBits

inherited

Definition at line 75 of file AssemblerLibGen.hpp.

typedef torc::architecture::DDB torc::bitstream::AssemblerLibGen::DDB

inherited

Imported type name.

Definition at line 45 of file AssemblerLibGen.hpp.

typedef torc::physical::DesignSharedPtr torc::bitstream::AssemblerLibGen::DesignSharedPtr

inherited

Imported type name.

Definition at line 65 of file AssemblerLibGen.hpp.

typedef torc::architecture::ExtendedWireInfo torc::bitstream::AssemblerLibGen::ExtendedWireInfo

inherited

Imported type name.

Definition at line 59 of file AssemblerLibGen.hpp.

typedef torc::physical::InstanceSharedPtr torc::bitstream::AssemblerLibGen::InstanceSharedPtr

inherited

Imported type name.

Definition at line 67 of file AssemblerLibGen.hpp.

typedef torc::physical::NetSharedPtr torc::bitstream::AssemblerLibGen::NetSharedPtr

inherited

Imported type name.

Definition at line 69 of file AssemblerLibGen.hpp.

typedef boost::filesystem::path torc::bitstream::AssemblerLibGen::path

inherited

Imported type name.

Definition at line 43 of file AssemblerLibGen.hpp.

typedef torc::architecture::PrimitiveElement torc::bitstream::AssemblerLibGen::PrimitiveElement

inherited

Imported type name.

Definition at line 61 of file AssemblerLibGen.hpp.

typedef torc::architecture::PrimitiveElementArray torc::bitstream::AssemblerLibGen::PrimitiveElementArray

inherited

Imported type name.

Definition at line 63 of file AssemblerLibGen.hpp.

typedef torc::packer::PrimitiveStructureSharedPtr torc::bitstream::AssemblerLibGen::PrimitiveStructureSharedPtr

inherited

Imported type name.

Definition at line 71 of file AssemblerLibGen.hpp.

typedef std::map<std::string, PrimitiveStructureSharedPtr> torc::bitstream::AssemblerLibGen::PrimitiveStructuresSharedPtrMap

inherited

Typedef of map from primitive name to primitive structure shared pointer.

Definition at line 86 of file AssemblerLibGen.hpp.

typedef torc::architecture::Site torc::bitstream::AssemblerLibGen::Site

inherited

Imported type name.

Definition at line 49 of file AssemblerLibGen.hpp.

typedef torc::architecture::Sites torc::bitstream::AssemblerLibGen::Sites

inherited

Imported type name.

Definition at line 47 of file AssemblerLibGen.hpp.

typedef torc::bitstream::Assembler::SiteTypeToConfigSettings torc::bitstream::AssemblerLibGen::SiteTypeToConfigSettings

inherited

Definition at line 77 of file AssemblerLibGen.hpp.

typedef std::string torc::bitstream::AssemblerLibGen::string

inherited

Imported type name.

Definition at line 41 of file AssemblerLibGen.hpp.

typedef torc::architecture::xilinx::TileIndex torc::bitstream::AssemblerLibGen::TileIndex

inherited

Imported type name.

Definition at line 55 of file AssemblerLibGen.hpp.

typedef torc::architecture::TileInfo torc::bitstream::AssemblerLibGen::TileInfo

inherited

Imported type name.

Definition at line 53 of file AssemblerLibGen.hpp.

typedef torc::architecture::Tiles torc::bitstream::AssemblerLibGen::Tiles

inherited

Imported type name.

Definition at line 51 of file AssemblerLibGen.hpp.

typedef torc::bitstream::Assembler::TileTypeToSiteType torc::bitstream::AssemblerLibGen::TileTypeToSiteType

inherited

Definition at line 78 of file AssemblerLibGen.hpp.

typedef std::map<std::string,std::set<std::string> > torc::bitstream::AssemblerLibGen::TileTypeToSiteTypeSet

inherited

Typedef of map from tile type to set of site type.

Definition at line 84 of file AssemblerLibGen.hpp.

typedef torc::architecture::Tilewire torc::bitstream::AssemblerLibGen::Tilewire

inherited

Imported type name.

Definition at line 57 of file AssemblerLibGen.hpp.

Constructor & Destructor Documentation

torc::bitstream::Virtex7LibGen::Virtex7LibGen ( string  inDevice, path  inHarnessFolder, path  inXdlGenerationFolder  )

inline

Constructor.

Definition at line 30 of file Virtex7LibGen.hpp.

            : AssemblerLibGen(inDevice, inHarnessFolder, inXdlGenerationFolder) {
            initialize();    
        }   

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virtual torc::bitstream::Virtex7LibGen::~Virtex7LibGen ( )

inlinevirtual

Destructor.

Definition at line 35 of file Virtex7LibGen.hpp.

{ }

Member Function Documentation

void torc::bitstream::Virtex7LibGen::compressBitFile ( path  primaryFile, path  referenceFile  )

protectedvirtual

Compress given bitstream file against reference bitstream file.

Implements torc::bitstream::AssemblerLibGen.

Definition at line 79 of file Virtex7LibGen.cpp.

                                                                        {

    bool debug = false;

    // Read the bitstream files
    torc::bitstream::BitstreamSharedPtr referenceBitstreamPtr = Factory::newBitstreamPtr(referenceFile);
    torc::bitstream::BitstreamSharedPtr primBitstreamPtr = Factory::newBitstreamPtr(primaryFile);

    // Check if both the bitstreams were read successfully.
    if(referenceBitstreamPtr && primBitstreamPtr) {
        std::cout << "Read the two bit files - " << primaryFile.filename() << " and " << referenceFile.filename() << " successfully" << std::endl;
    } else {
        std::cout << "Could not read the bit files " << primaryFile << " " << referenceFile << std::endl;
        return;
    }

    // dynamically cast the bitstream pointer into a Virtex7 bitstream pointer

    boost::shared_ptr<torc::bitstream::Virtex7> primVirtexBitstreamPtr = boost::dynamic_pointer_cast<torc::bitstream::Virtex7>(
        primBitstreamPtr);
    boost::shared_ptr<torc::bitstream::Virtex7> refVirtex7BitstreamPtr = boost::dynamic_pointer_cast<torc::bitstream::Virtex7>(
        referenceBitstreamPtr);

    // initalize frame map
    refVirtex7BitstreamPtr->initializeDeviceInfo(referenceBitstreamPtr->getDesignName());
    refVirtex7BitstreamPtr->initializeFrameMaps();
    refVirtex7BitstreamPtr->readFramePackets();

    primVirtexBitstreamPtr->initializeDeviceInfo(primBitstreamPtr->getDesignName());
    primVirtexBitstreamPtr->initializeFrameMaps();
    primVirtexBitstreamPtr->readFramePackets();

    uint32_t wordOffset = getWordOffsetFromXdlFile(primaryFile, primVirtexBitstreamPtr);

    // look up the frame blocks
    torc::bitstream::VirtexFrameBlocks& refFrameBlocks = refVirtex7BitstreamPtr->getFrameBlocks();
    torc::bitstream::VirtexFrameBlocks& primFrameBlocks = primVirtexBitstreamPtr->getFrameBlocks();
    std::vector<boost::int32_t> combinedAddressVector;


    // iterate over the block types
    for(int blockIndex = 0; blockIndex < Bitstream::eBlockTypeCount; blockIndex++) {
        // look up the frame set for this block
        torc::bitstream::VirtexFrameSet& nullFrameSet = refFrameBlocks.mBlock[blockIndex];
        torc::bitstream::VirtexFrameSet& primFrameSet = primFrameBlocks.mBlock[blockIndex];

        if(nullFrameSet.size() != primFrameSet.size()) {
            std::cout << "Frame set sizes do not match" << std::endl;
            return;
        }

        // We expect the majorIndex to remain same for all the mismatching part of the bitstream.
        uint32_t relativeFrameIndex = 0, currentMajorIndex = 0, previousMajorIndex = 0;
        bool firstMismatch = true;

        // iterate over the frames
        for(uint32_t frameIndex = 0; frameIndex < nullFrameSet.size(); frameIndex++) {
            // look up the frame for this set
            VirtexFrameSharedPtr nullFramePtr = nullFrameSet[frameIndex];
            VirtexFrameSharedPtr primFramePtr = primFrameSet[frameIndex];

            const VirtexFrame::word_t* wordsReference = nullFramePtr->getWords();
            const VirtexFrame::word_t* wordsPrim = primFramePtr->getWords();

            const VirtexFrame::word_t* pReferenceWords = wordsReference;
            const VirtexFrame::word_t* pPrimWords = wordsPrim;
            const VirtexFrame::word_t* eReferenceWords = pReferenceWords
                + nullFramePtr->getLength();
            const VirtexFrame::word_t* ePrimWords = pPrimWords + primFramePtr->getLength();

            if(nullFramePtr->getLength() != primFramePtr->getLength()) {
                std::cout << "WARNING: Frames of different sizes " << nullFramePtr->getLength() << " "
                    << primFramePtr->getLength() << std::endl;
            }

            // iterate over the frame words
            bool found = false;
            int wordIndex = 0;

            // Iterate over the frame words
            while(pReferenceWords < eReferenceWords) {
                // If the word is not zero and not same as that of reference bitstream and not crc word
                if(*pPrimWords != 0 && *pReferenceWords != *pPrimWords && wordIndex != sCrcWordIndex) {

                    boost::int32_t bitIndex = 0;
                    // ToDo: Uncomment after support is introduced
                    primVirtexBitstreamPtr->splitFrameIndex(frameIndex, currentMajorIndex,  relativeFrameIndex);

                    // If this is not the first mismatch, compare the major index with previous mismatching word's major index.
                    if(!firstMismatch) {
                        if(currentMajorIndex != previousMajorIndex) {
                            std::cout << "WARNING: Bitstream mismatch across major indices: " << currentMajorIndex << " and " << previousMajorIndex << std::endl;
                            //exit (-1);
                            return;
                        }
                    } else {
                        firstMismatch = false;
                        previousMajorIndex = currentMajorIndex;
                    }

                    // Get the 1 bits in primary design which are zero in reference design
                    VirtexFrame::word_t tempWord = (*pPrimWords ^ *pReferenceWords) & *pPrimWords;
                    // Find all the 1s in the word
                    while(tempWord != 0) {
                        // check if the LSB is 1
                        if(tempWord & 1) {
                            // store the combined address
                            combinedAddressVector.push_back((relativeFrameIndex << 16) | ((wordIndex - wordOffset)
                                << 8) | bitIndex);

                        }
                        tempWord = tempWord >> 1;
                        bitIndex++;
                    }
                    found = true;
                }
                pReferenceWords++;
                pPrimWords++;
                wordIndex++;
            }
            // if we found any non-zero words, display them. This if for debugging purpose only.
            if(found) {
                std::cout << "Found unmatching frame: block " << blockIndex << ", relative index "
                    << Hex32(relativeFrameIndex) << ", global index: " << Hex32(frameIndex)
                    << ", major index: " << Hex32(currentMajorIndex) << std::endl;
                pReferenceWords = wordsReference;
                if(debug) {
                    std::cout << "    Referen: ";
                    while(pReferenceWords < eReferenceWords) {
                        std::cout << Hex32(*pReferenceWords++) << " ";
                    }
                    std::cout << std::endl;
                    pPrimWords = wordsPrim;
                    std::cout << "    Primary: ";
                    while(pPrimWords < ePrimWords) {
                        std::cout << Hex32(*pPrimWords++) << " ";
                    }
                    std::cout << std::endl;
                }
            }
        }
    }

    // Store all the combined addresses in the sparse bit file.
    boost::filesystem::path sparceBitstreamPath = primaryFile.replace_extension().string()
        + ".cbit";

    std::ofstream sparceBitstreamFile;
    sparceBitstreamFile.open(sparceBitstreamPath.string().c_str(), std::ios::binary | std::ios::out);
    if(sparceBitstreamFile.good()) {
        std::cout << " Opened library file to write " << sparceBitstreamPath.string().c_str()
            << std::endl;
    } else {
        std::cerr << " Could not open library file to write - "
            << sparceBitstreamPath.string().c_str() << std::endl;
        exit(-1);
    }

    boost::int32_t vectorSize = combinedAddressVector.size();
    sparceBitstreamFile.write((char *) &vectorSize, 4);
    std::cout << "Different words -" << std::endl;
    std::cout << "    ";
    for(std::vector<boost::int32_t>::const_iterator iter = combinedAddressVector.begin(); iter
        != combinedAddressVector.end(); iter++) {
        sparceBitstreamFile.write((char *) (&*iter), 4);
        std::cout << Hex32((*iter)) << " ";
    }
    std::cout << std::endl;

    std::cout << "Wrote data to the library file." << std::endl;

    sparceBitstreamFile.close();

}

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void torc::bitstream::AssemblerLibGen::compressBitFiles ( )

inherited

Compress all Xilinx bitfiles in mXdlGenerationFolder.

Definition at line 736 of file AssemblerLibGen.cpp.

                                       {
    // Go over all the .bit files
    // Go over all the files in the directory
    boost::filesystem::directory_iterator eFiles;
    boost::filesystem::directory_iterator pFiles(mXdlGenerationFolder);
    while(pFiles != eFiles) {
        // If it is a Xilinx bit file (.bit extension)
        path filePath = pFiles->path();
        pFiles++;
        if(filePath.extension() == ".bit") {

            // Check if bit file in newer then compressed bit file
            path cBitPath = filePath;
            cBitPath.replace_extension(".cbit");
            if(boost::filesystem::exists(cBitPath)) {
                std::time_t bitFileModTime = boost::filesystem::last_write_time(filePath);
                std::time_t cBitFileModTime = boost::filesystem::last_write_time(cBitPath);
                // If compressed bit file modification time later than bitgen bit, continue
                if(cBitFileModTime > bitFileModTime)
                    continue;
            }
        
            // Check for reference file
            // (Note: Wrapping filename() as a path for compatibility with Boost.Filesystem V2)
            string referenceBitFileName 
                = boost::filesystem::path(filePath.filename()).string();
            path referenceBitFilePath = mXdlGenerationReferenceFolder / referenceBitFileName;
            if(!boost::filesystem::exists(referenceBitFilePath)) {
                // Remove last part of Xdl file name (config value)
                unsigned position = referenceBitFileName.find_last_of('-');
                referenceBitFileName.replace(position, string::npos, ".bit");
                referenceBitFilePath = mXdlGenerationReferenceFolder / referenceBitFileName;
                if(!boost::filesystem::exists(referenceBitFilePath)) {
                    // Get null bitstream path
                    referenceBitFilePath = mLibraryFolder / "null_bitstreams" / mDB.getDeviceName();
                    referenceBitFilePath.replace_extension(".bit");
                    
                }

            }
            compressBitFile(filePath, referenceBitFilePath);
            // std::cout << "Bitfile: " << filePath.filename() << ". Reference: " << referenceBitFilePath.filename() << std::endl;
        }
    }

    generateMemoryMicroBitstream();
}

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AssemblerLibGen::DesignSharedPtr torc::bitstream::AssemblerLibGen::createEmptyDesignWithSameMetadata ( DesignSharedPtr  inDesignPtr )

protectedinherited

Create an empty design with same metadata. Does not copy configurations.

Return empty design with same metadata

Definition at line 383 of file AssemblerLibGen.cpp.

                                                                                                             {
    DesignSharedPtr emptyDesign = torc::physical::Factory::newDesignPtr(inDesignPtr->getName(),
        inDesignPtr->getDevice(), inDesignPtr->getPackage(), inDesignPtr->getSpeedGrade(),
        inDesignPtr->getXdlVersion());

    return emptyDesign;
}

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void torc::bitstream::AssemblerLibGen::createHexConfigXdl ( const string &  inConfigSetting, const string &  inSiteType, int  numHexChars, DesignSharedPtr  inHarnessDesignPtr  )

protectedinherited

Create Xdl for configurations which hex string values.

Create Xdl for configurations with values as hex string.

Definition at line 461 of file AssemblerLibGen.cpp.

                                                {
    // We know for Virtex 5 DSP's mask and pattern have 12 hex characters as config value.
    long long configValNumber = 1;

    std::string siteTypeAndElement = inXdlFileNamePartial + sNameSeparator + inConfigSetting;

    std::stringstream xdlReferenceFileName;
    xdlReferenceFileName << siteTypeAndElement << sXdlExtension;
    createReferenceXdlForConfigSetting(inConfigSetting, inHarnessDesignPtr, inXdlFileNamePartial);

    for(int bitPosition = 0; bitPosition < inNumHexChars*4; bitPosition++) {
        std::stringstream ssConfigVal;
        ssConfigVal << std::setfill('0') << std::setw(inNumHexChars) << std::hex << configValNumber;

        std::stringstream xdlFileName;
        xdlFileName << siteTypeAndElement << sNameSeparator << bitPosition << sXdlExtension;

        setConfigAndGenerateXdl(inConfigSetting, ssConfigVal.str(), xdlFileName.str(), inHarnessDesignPtr);

        configValNumber = configValNumber << 1;

    }

    // Set the config to default again
    InstanceSharedPtr instancePtr = *(inHarnessDesignPtr->instancesBegin());
    instancePtr->setConfig(inConfigSetting, "", getReferenceConfigValue(inConfigSetting));
}

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void torc::bitstream::AssemblerLibGen::createRambBaseXdl ( const string &  inSiteType, DesignSharedPtr  inHarnessDesignPtr  )

protectedinherited

Create Xdl with a Ramb instane and no configuration.

Create Xdl with just Ramb site instantiated.

Definition at line 436 of file AssemblerLibGen.cpp.

                                                                                                    {
    // Create XDL file name of the pattern <Family>-<TileType>-<SiteType>-<Element>-<Config>.xdl
    std::stringstream ssXDLFileName;
    ssXDLFileName << mDB.getFamilyName() << sNameSeparator << mCurTileType << sNameSeparator << inSiteType << sNameSeparator
        << inSiteType << sNameSeparator << "BASE.xdl";
    boost::filesystem::path xdlFilePath = mXdlGenerationFolder / ssXDLFileName.str();
    std::fstream xdlExport(xdlFilePath.string().c_str(), std::ios::out);
    torc::physical::XdlExporter fileExporter(xdlExport);
    DesignSharedPtr emptyDesignPtr = createEmptyDesignWithSameMetadata(inHarnessDesignPtr);
    // add a bram instance
    // Add an empty instance of same site type and location
    InstanceSharedPtr instancePtr = *(inHarnessDesignPtr->instancesBegin());

    InstanceSharedPtr emptyInstance = torc::physical::Factory::newInstancePtr(instancePtr->getName(),
        instancePtr->getType(), instancePtr->getTile(), instancePtr->getSite(),
        instancePtr->getBonding());

    emptyDesignPtr->addInstance(emptyInstance);

    fileExporter(emptyDesignPtr);
    xdlExport.close();

}

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void torc::bitstream::AssemblerLibGen::createReferenceXdlForConfigSetting ( const string &  inConfigSetting, DesignSharedPtr  outHarnessDesignPtr, const string &  inXdlFileNamePartial  )

protectedinherited

Create reference Xdl for given config setting.

Definition at line 669 of file AssemblerLibGen.cpp.

                                            {

    InstanceSharedPtr instancePtr = *(inHarnessDesignPtr->instancesBegin());
    // If no instance found, just return
    if(!instancePtr) {
        std::cerr << "No instance found in the harness " << inHarnessDesignPtr->getName()
            << std::endl;
        return;
    }

    // Set config value to #OFF for the given element
    std::string referenceConfigValue = getReferenceConfigValue(inConfigSetting);
    instancePtr->setConfig(inConfigSetting, "", referenceConfigValue);

    // Generate an reference XDL file for this element's custom harness
    std::stringstream ssReferenceXdlFileName;
    ssReferenceXdlFileName << inXdlFileNamePartial << sNameSeparator
        << inConfigSetting << sXdlExtension;
    boost::filesystem::path referenceXDLFilePath = mXdlGenerationReferenceFolder / ssReferenceXdlFileName.str();

    std::ofstream fileStream(referenceXDLFilePath.string().c_str());
    if(!fileStream.good()) {
        std::cerr << "Could not open file " << referenceXDLFilePath.string() << std::endl;
        return;
    }

    // Export design as XDL
    torc::physical::XdlExporter exporter(fileStream);
    exporter(inHarnessDesignPtr);
    fileStream.close();
}

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void torc::bitstream::AssemblerLibGen::createXdlForCompoundSettings ( const PrimitiveElement &  inElement, const string &  inSiteType, PrimitiveStructureSharedPtr  inPrimitiveStructurePtr, DesignSharedPtr  inHarnessDesignPtr  )

protectedinherited

Create Xdls for compound settings.

Definition at line 491 of file AssemblerLibGen.cpp.

                                                                                                                                                                                                        {
    std::vector<std::string> compoundElements = mCompoundSettingMap[inElement1.getName()];
    // For now assume there is only on element in the vector, i.e. there is a compound
    // setting with only two elements.
    if(compoundElements.size() != 1) {
        std::cerr << "WARNING: Compound setting with more than two elements not handled currently"
            << std::endl;
    } else {

        // Generate XDLs with all permutations of configs of the two elements
        // The two element names will be concatenated to form a compound element name Element1Element2.
        // Similarly two config settings will be concatenated to form a compound config name.
        std::string element1Name = inElement1.getName();
        std::string element2Name = compoundElements[0];
        std::string compoundElementName = element1Name + element2Name;

        // Get the other element
        int elementIndex = getElementIndexFromName(element2Name, inPrimitiveStructurePtr);

        if(elementIndex == -1) {
            std::cerr << "WARNING: Compound setting " << element2Name << " not found" << std::endl;
            return;
        }

        const PrimitiveElement &element2 = inPrimitiveStructurePtr->getPrimitiveDefPtr()->getElements()[elementIndex];

        // Get the first instance
        InstanceSharedPtr instancePtr = *(inHarnessDesignPtr->instancesBegin());

        // Store the 2nd elements harness config
        std::string harnessConfig2Val, harnessConfig2Name;
        instancePtr->getConfig(element2Name, harnessConfig2Name, harnessConfig2Val);

        // Set element1 OFF and generate harness
        std::string referenceXdlFileName = inSiteType + sNameSeparator + compoundElementName + sXdlExtension;
        instancePtr->setConfig(element1Name, "", getReferenceConfigValue(element1Name));
        instancePtr->setConfig(element2Name, "", getReferenceConfigValue(element2Name));
        
        boost::filesystem::path referenceXDLFilePath = mXdlGenerationReferenceFolder / referenceXdlFileName;

        std::ofstream fileStream(referenceXDLFilePath.string().c_str());
        if(!fileStream.good()) {
            std::cerr << "Could not open file " << referenceXDLFilePath.string() << std::endl;
            return;
        }

        // Export design as XDL (create referene Xdl)
        torc::physical::XdlExporter exporter(fileStream);
        exporter(inHarnessDesignPtr);
        fileStream.close();

        // Iterate over configs of 1st element
        const PrimitiveElement::StringSet &configs1 = inElement1.getCfgs();
        PrimitiveElement::StringSet::const_iterator pConfigs1 = configs1.begin();
        PrimitiveElement::StringSet::const_iterator eConfigs1 = configs1.end();

        while(pConfigs1 != eConfigs1) {

            // Iterate over configs of 2nd element.
            const PrimitiveElement::StringSet &configs2 = element2.getCfgs();
            PrimitiveElement::StringSet::const_iterator pConfigs2 = configs2.begin();
            PrimitiveElement::StringSet::const_iterator eConfigs2 = configs2.end();

            while(pConfigs2 != eConfigs2) {

                // Form the XDL file name
                std::string compoundConfigName = *pConfigs1 + *pConfigs2;
                std::string xdlFileName = inSiteType + sNameSeparator + compoundElementName
                    + sNameSeparator + compoundConfigName + sXdlExtension;

                // Set element1 config and generate primary XDL
                instancePtr->setConfig(element1Name, "", *pConfigs1);
                setConfigAndGenerateXdl(element2Name, *pConfigs2, xdlFileName, inHarnessDesignPtr);
                pConfigs2++;
            }

            pConfigs1++;
        }

        // Set original value of element2
        instancePtr->setConfig(element2Name, harnessConfig2Name, harnessConfig2Val);
    }
}

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void torc::bitstream::AssemblerLibGen::createXdlForGeneralConfigSetting ( const string &  inConfigSetting, const string &  inConfigVal, const string &  inXdlFileNamePartial, DesignSharedPtr  inHarnessDesignPtr  )

protectedinherited

Set config value and create Xdl.

Definition at line 392 of file AssemblerLibGen.cpp.

                                                                            {

    std::string xdlFileName = inXdlFileNamePartial + sNameSeparator + inConfigVal + sXdlExtension;

    setConfigAndGenerateXdl(inConfigSetting, inConfigVal, xdlFileName, inHarnessDesignPtr);
}

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void torc::bitstream::AssemblerLibGen::createXdlForLut ( const torc::architecture::PrimitiveElement &  inElement, const string &  inXdlFileNamePartial, DesignSharedPtr  inHarnessDesignPtr  )

protectedinherited

Create Xdl for Lut.

Definition at line 614 of file AssemblerLibGen.cpp.

                                        {
    std::string configSetting = inElement.getName();

//  std::cout << "Found a LUT " << configSetting << std::endl;

    DesignSharedPtr emptyDesign = createEmptyDesignWithSameMetadata(inHarnessDesignPtr);
    InstanceSharedPtr instancePtr = *(inHarnessDesignPtr->instancesBegin());
    InstanceSharedPtr emptyInstance = torc::physical::Factory::newInstancePtr(instancePtr->getName(),
        instancePtr->getType(), instancePtr->getTile(), instancePtr->getSite(),
        instancePtr->getBonding());
    emptyDesign->addInstance(emptyInstance);

    // Generate reference XDL for LUT
    createReferenceXdlForConfigSetting(configSetting, emptyDesign, inXdlFileNameSitetype);
    string xdlFileNameSetting = inXdlFileNameSitetype + sNameSeparator + configSetting;

    const PrimitiveElementPinArray &pins = inElement.getPins();
    PrimitiveElementPinArray::const_iterator pPinsOut = pins.begin();
    PrimitiveElementPinArray::const_iterator ePinsOut = pins.end();
    //For every output-input pin combination
    while(pPinsOut != ePinsOut) {

        // Handly only input Ax assigned to output O5/O6
        if(pPinsOut->isOutput() && boost::iequals(pPinsOut->getName().substr(0, 1), "O")) {

            PrimitiveElementPinArray::const_iterator pPinsIn = pins.begin();
            PrimitiveElementPinArray::const_iterator ePinsIn = pins.end();

            while(pPinsIn != ePinsIn && boost::iequals(pPinsIn->getName().substr(0, 1), "A")) {
                if(pPinsIn->isInput()) {

                    std::string configVal = "#LUT:" + pPinsOut->getName() + "=" + pPinsIn->getName();
                    std::string xdlFileName = xdlFileNameSetting + sNameSeparator + configVal + sXdlExtension;
                    setConfigAndGenerateXdl(configSetting, configVal, xdlFileName, emptyDesign);
                }
                pPinsIn++;
            }

            // Generate XDLs for output 1 also
            std::string configVal = "#LUT:" + pPinsOut->getName() + "=" + "1";
            std::stringstream xdlFileName1;
            xdlFileName1 << xdlFileNameSetting << sNameSeparator << configVal << sXdlExtension;
            setConfigAndGenerateXdl(configSetting, configVal, xdlFileName1.str(), emptyDesign);

            configVal = "#LUT:" + pPinsOut->getName() + "=" + "0";
            std::stringstream xdlFileName0;
            xdlFileName0 << xdlFileNameSetting << sNameSeparator << configVal << sXdlExtension;
            setConfigAndGenerateXdl(configSetting, configVal, xdlFileName0.str(), emptyDesign);
        }
        pPinsOut++;
    }
}

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void torc::bitstream::AssemblerLibGen::createXdlForOrphanElements ( const torc::architecture::PrimitiveElement &  inElement, const string &  inXdlFileNamePartial, DesignSharedPtr  inHarnessDesignPtr  )

protectedinherited

Create Xdls for orphan elements with empty reference Xdl.

Definition at line 576 of file AssemblerLibGen.cpp.

                                                    {
    
    std::string elementName = inElement.getName();
    std::string siteTypeAndElem;
    std::cout << "Found Orphan Element " << elementName << std::endl;
    // Get and empty design with same metadata
    DesignSharedPtr emptyDesign = createEmptyDesignWithSameMetadata(inHarnessDesignPtr);

    // Add an empty instance of same site type and location
    InstanceSharedPtr instancePtr = *(inHarnessDesignPtr->instancesBegin());

    InstanceSharedPtr emptyInstance = torc::physical::Factory::newInstancePtr(instancePtr->getName(),
        instancePtr->getType(), instancePtr->getTile(), instancePtr->getSite(),
        instancePtr->getBonding());

    emptyDesign->addInstance(emptyInstance);

    createReferenceXdlForConfigSetting(elementName, emptyDesign, inXdlFileNamePartial);

    // Go over all the configs
    const PrimitiveElement::StringSet &configs = inElement.getCfgs();
    PrimitiveElement::StringSet::const_iterator pConfigs = configs.begin();
    PrimitiveElement::StringSet::const_iterator eConfigs = configs.end();

    std::string xdlFileNameSetting = inXdlFileNamePartial + sNameSeparator + elementName;
    // Iterate over configs of the primitive
    while(pConfigs != eConfigs) {
        std::string xdlFileName = xdlFileNameSetting + sNameSeparator + *pConfigs + sXdlExtension;
        //std::cout << "\t\tConfig " << *pConfigs << ". File " << xdlFileName << std::endl;
        setConfigAndGenerateXdl(elementName, *pConfigs, xdlFileName, emptyDesign);
        pConfigs++;
    }
    
}

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void torc::bitstream::AssemblerLibGen::createXdlsForConfigSetting ( const torc::architecture::PrimitiveElement &  inElement, PrimitiveStructureSharedPtr const  inPrimitiveStructurePtr, const string &  inSiteType, DesignSharedPtr  inHarnessDesignPtr  )

protectedinherited

Create Xdls for each config value of the config setting

Definition at line 401 of file AssemblerLibGen.cpp.

                                        {

    std::string configSetting = inElement.getName();

    if(isCompoundSettingHead(inElement.getName())) {
        createXdlForCompoundSettings(inElement, inXdlFileNamePartial, inPrimitiveStructurePtr, inHarnessDesignPtr);
//  } // The use of orphan elements is still debatable
//  else if(inPrimitiveStructurePtr->isOrphan(inElement) && inElement.getName() != "SYNC_ATTR" && 
//              inElement.getName().substr(1) != "5FFSR") {
//      createXdlForOrphanElements(inElement, inXdlFileNamePartial, inHarnessDesignPtr);
    } else {

        std::string xdlFileNameConfig = inXdlFileNamePartial + sNameSeparator + configSetting;

        const torc::architecture::PrimitiveElement::StringSet &configs = inElement.getCfgs();
        torc::architecture::PrimitiveElement::StringSet::const_iterator pConfigs = configs.begin();
        torc::architecture::PrimitiveElement::StringSet::const_iterator eConfigs = configs.end();

        // Iterate over configs of the primitive
        while(pConfigs != eConfigs) {

            if(inPrimitiveStructurePtr->isLUT(inElement, *pConfigs)) {
                createXdlForLut(inElement, inXdlFileNamePartial, inHarnessDesignPtr);
            } else {
                createXdlForGeneralConfigSetting(inElement.getName(), *pConfigs, xdlFileNameConfig, inHarnessDesignPtr);
            }

            pConfigs++;
        }
    }
}

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void torc::bitstream::AssemblerLibGen::exportSink ( Tilewire &  inSource, Tilewire &  inSink  )

protectedinherited

Export a single pip.

Definition at line 231 of file AssemblerLibGen.cpp.

                                                                     {

    ExtendedWireInfo source(mDB, inSource);
    ExtendedWireInfo sink(mDB, inSink);

    std::stringstream ss;
    ss << mDB.getFamilyName() << sNameSeparator << source.mTileTypeName << sNameSeparator << "routing" << sNameSeparator << source.mWireName << sNameSeparator << sink.mWireName;
    std::string designName(ss.str());

    // ToDo: Should load a design for routing from harness folder
    torc::physical::DesignSharedPtr designPtr = torc::physical::Factory::newDesignPtr(designName,
        mDB.getDeviceName(), mDeviceToPackageMap[mDB.getDeviceName()], "-2", "v3.2");

    string dummyInstName = "dummyInst";
    string dummyInstSiteType = "SLICEL";
    string dummyInstSiteLocation = "SLICE_X1Y1";
    torc::physical::InstanceSharedPtr instancePtr = torc::physical::Factory::newInstancePtr(
        dummyInstName, dummyInstSiteType, "DUMMY", dummyInstSiteLocation);

    designPtr->addInstance(instancePtr);

    NetSharedPtr net = torc::physical::Factory::newNetPtr(dummyInstName);
    torc::physical::Pip pip = torc::physical::Factory::newPip(source.mTileName, source.mWireName, sink.mWireName,
        torc::physical::ePipUnidirectionalBuffered);
    net->addPip(pip);

    torc::physical::InstancePinSharedPtr sourcePin = torc::physical::Factory::newInstancePinPtr(instancePtr,
        "BQ");
    torc::physical::InstancePinSharedPtr sinkPin = torc::physical::Factory::newInstancePinPtr(instancePtr,
        "B4");
    net->addSource(sourcePin);
    net->addSink(sinkPin);

    designPtr->addNet(net);

    // export the created design
    boost::filesystem::path xdlFilePath = mXdlGenerationFolder / designName.append(sXdlExtension);
    std::fstream xdlExport(xdlFilePath.string().c_str(), std::ios_base::out);
    torc::physical::XdlExporter fileExporter(xdlExport);
    fileExporter(designPtr);
    xdlExport.close();
}

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void torc::bitstream::AssemblerLibGen::exportTileSinks ( TileIndex  inTileIndex )

protectedinherited

Export all pips within the specified tile.

Definition at line 199 of file AssemblerLibGen.cpp.

                                                           {

    const TileInfo& tileInfo = mTiles.getTileInfo(inTileIndex);

    torc::architecture::xilinx::TileTypeIndex tileTypeIndex = tileInfo.getTypeIndex();

    std::cout << "   Tile name: " << tileInfo.getName() << ", Tile type: " 
        << mTiles.getTileTypeName(tileTypeIndex) << std::endl;

    torc::architecture::xilinx::WireCount wireCount = mTiles.getWireCount(tileTypeIndex);

    // iterate through all the wires in the tile
    for(torc::architecture::xilinx::WireIndex wireIndex /* implicitly initialized to 0 */; wireIndex < wireCount; wireIndex++) {
        // join the tile index and the wire index into a "tilewire"
        Tilewire source(inTileIndex, wireIndex);
        // expand all of the sinks of interest in this tile
        torc::architecture::TilewireVector sinks;
        mDB.expandTilewireSinks(source, sinks, false, true, true, true);
        if(sinks.empty())
            continue;
        // iterate over all of the pips that we have found
        torc::architecture::TilewireVector::iterator p = sinks.begin();
        torc::architecture::TilewireVector::iterator e = sinks.end();
        while(p < e) {
            // look up the sink tilewire
            Tilewire sink = *p++;
            exportSink(source, sink);
        }
    }
}

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void torc::bitstream::AssemblerLibGen::generateBitstreams ( )

inherited

Generate bitstream for all Xdls in mXdlGenerationFolder and mXdlGenerationReferenceFolder.

Generates bitstream for all Xdls be calling a perl script which iterates over Xdls and calls Xilinxs tools to create bitstream

Definition at line 720 of file AssemblerLibGen.cpp.

                                         {
    // Call perl script to convert Xdl to Bitstream.
    path buildFolder = torc::common::DirectoryTree::getExecutablePath() / "torc/bitstream/assembler/build";
    string systemCommand = "perl " + buildFolder.string() + "/xdl2bit.pl " + mXdlGenerationFolder.string();
    int systemReturn = system(systemCommand.c_str());
    if(systemReturn != 0) {
        std::cerr << "Error calling perl script xdl2bit.pl " << std::endl;
    }
    systemCommand = "perl " + buildFolder.string() + "/xdl2bit.pl " + mXdlGenerationReferenceFolder.string();
    systemReturn = system(systemCommand.c_str());
    if(systemReturn != 0) {
        std::cerr << "Error calling perl script xdl2bit.pl " << std::endl;
    }
}

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void torc::bitstream::AssemblerLibGen::generateLogicAndWireXdl ( )

inherited

Generate Xdls for both logic sites and routing pips.

void torc::bitstream::AssemblerLibGen::generateLogicXdls ( )

inherited

Generrate Xdls for logic sites.

Generate micro-Xdl for logic sites.

Definition at line 62 of file AssemblerLibGen.cpp.

                                        {
    std::cout << "Generating micro Xdls for Logic element..." << std::endl;
    // Poplulate tile type to site types map
    TileTypeToSiteTypeSet tileTypeToSiteType = getTileTypeToSiteTypeMap();
    // Populate primitive name to structure map
    PrimitiveStructuresSharedPtrMap primitiveStructures = getPrimitiveNameToStructreMap();

    // Iterate through tile types and then site types
    TileTypeToSiteTypeSet::const_iterator pTileTypes = tileTypeToSiteType.begin();
    TileTypeToSiteTypeSet::const_iterator eTileTypes = tileTypeToSiteType.end();

    // For every tile type
    while(pTileTypes != eTileTypes) {
        //std::cout << "  Tile type: " << pTileTypes->first << std::endl;
        mCurTileType = pTileTypes->first;
        std::set<std::string>::iterator pSites = pTileTypes->second.begin();
        std::set<std::string>::iterator eSites = pTileTypes->second.end();
        pTileTypes++;
        while(pSites != eSites) {

            // look up the PrimitiveDef name and the PrimitiveStructureSharedPtr
            std::string primitiveDefName = *pSites;
            PrimitiveStructureSharedPtr primitiveStructurePtr =
                primitiveStructures[primitiveDefName];
            pSites++;
            //std::cout << "    Site type: " << primitiveDefName << std::endl;
            // If the site type is to be supported
            if(isSiteTypeSupported(primitiveDefName)) {

                // Get the designPtr for test harness for this site type
                torc::physical::DesignSharedPtr harnessDesignPtr = getHarnessDesignForSiteType(
                    primitiveDefName);

                if(!harnessDesignPtr) {
                    std::cout << "WARNING: No harness design for site type " << primitiveDefName << std::endl;
                    continue;
                }

                std::cout << "Tile: " << mCurTileType << "  Site: " << primitiveDefName << std::endl;

                // Create the XDL file name (partial)
                // XDL file is in the form <Family>-<TileType>-<SiteType>-<Config>-<Value>.xdl
                std::stringstream ssXdlFileNamePartial;
                ssXdlFileNamePartial << mDB.getFamilyName() << sNameSeparator << mCurTileType << sNameSeparator << primitiveDefName;

                if(isRambSite(primitiveDefName)) {
                    createRambBaseXdl(primitiveDefName, harnessDesignPtr);
                }

                // For Dsp site, MASK and PATTER config have hex config value.
                // The allowed values of these hex cofig are not present in Xdlrc and have to be created
                if(isDspSite(primitiveDefName)) {
                    createHexConfigXdl("MASK", ssXdlFileNamePartial.str(), 12, harnessDesignPtr);
                    createHexConfigXdl("PATTERN", ssXdlFileNamePartial.str(), 12, harnessDesignPtr);
                }

                // We know the design has only one instance. So, get the first one in the iterator.
                torc::physical::InstanceSharedPtr harnessInstancePtr = *(harnessDesignPtr->instancesBegin());

                const torc::architecture::PrimitiveDef* primitiveDefPtr =
                    primitiveStructurePtr->getPrimitiveDefPtr();

                const PrimitiveElementArray& elements = primitiveDefPtr->getElements();
                PrimitiveElementArray::const_iterator pElements = elements.begin();
                PrimitiveElementArray::const_iterator eElements = elements.end();

                // Iterate over config settings/elements of the site
                while(pElements != eElements) {
                    const torc::architecture::PrimitiveElement &element = *pElements++;
                    //std::cout << "   " << element.getName() << std::endl << "      " ;
                    // Cache the current setting of the element in harness design
                    std::string harnessConfigName;
                    std::string harnessConfigVal;
                    // We know harness XDL design has only one instance
                    harnessInstancePtr = *(harnessDesignPtr->instancesBegin());
                    harnessInstancePtr->getConfig(element.getName(), harnessConfigName, harnessConfigVal);

                    // Ignore the route through elements
                    if(!primitiveStructurePtr->isRoutethrough(element)) {

                        // Generate XDLs only if the element has a config to be set.
                        if(element.getCfgs().size() > 0) {

                            // ToDo: Not all config setting require reference Xdl with harness as base. E.g. LUT configs.
                            // These configs can retain their setting and Xdls for them are not built up on harness.
                            createReferenceXdlForConfigSetting(element.getName(), harnessDesignPtr,
                                ssXdlFileNamePartial.str());

                            // Generate XDL for each config of the element.
                            createXdlsForConfigSetting(element, primitiveStructurePtr, ssXdlFileNamePartial.str(),
                                harnessDesignPtr);
                        }
                    }

                    // Store back the previous setting of the element in harness Design
                    harnessInstancePtr->setConfig(element.getName(), harnessConfigName, harnessConfigVal);

                }
            }
        }
    }

}

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void torc::bitstream::Virtex7LibGen::generateMemoryMicroBitstream ( )

protectedvirtual

Generate micro-bitstreams for memory elements like LUT in RAM mode.

Implements torc::bitstream::AssemblerLibGen.

Definition at line 307 of file Virtex7LibGen.cpp.

                                                 {
    // Get compressed bit files for LUTs in RAM/ROM mode.
    path libraryMemFolder = mLibraryFolder / "memory";
    string perlScript = libraryMemFolder.string() + "/extract-bits-for-luts.pl";
    string llFile = getParentFamilyName() + "-CLBLM_L-SLICEM-X-ROM.ll";
    path llFilePath = libraryMemFolder / llFile;
    string systemCommand = "perl " +  perlScript + " " + llFilePath.string();
    int systemReturn = system(systemCommand.c_str());

    llFile = getParentFamilyName() + "-CLBLM_R-SLICEM-X-ROM.ll";
    llFilePath = libraryMemFolder / llFile;
    systemCommand = "perl " +  perlScript + " " + llFilePath.string();
    systemReturn = system(systemCommand.c_str());
    string cpyCmd = "mv " + libraryMemFolder.string() + "/*.cbit " + mXdlGenerationFolder.string();
//  ToDo: Uncomment line below
    systemReturn = system(cpyCmd.c_str());
    (void) systemReturn;
}

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void torc::bitstream::AssemblerLibGen::generateWireXdls ( )

inherited

Generate Xdls for routing pips.

Generate XDL files for tiles supported for PIPs.

Definition at line 167 of file AssemblerLibGen.cpp.

                                       {
    std::cout << "Generating micro XDLs for routing PIPs..." << std::endl;
    TileCount tileCount = mTiles.getTileCount();

    // Go over tiles supported for PIPs
    std::vector<std::string> tilesSupported = getTilesSupportedForPips();
    std::vector<std::string>::const_iterator pTiles = tilesSupported.begin();
    std::vector<std::string>::const_iterator eTiles = tilesSupported.end();
    while(pTiles != eTiles) {
        
        std::string currTileName = *pTiles++;
        bool firstTile = true; //Torc doesn't handle first tile well. So ignore it.
        for(TileIndex i; i < tileCount; i++) {
            const TileInfo& tileInfo = mTiles.getTileInfo(i);
            TileTypeIndex tileTypeIndex = tileInfo.getTypeIndex();
            std::string tileTypeName = mTiles.getTileTypeName(tileTypeIndex);
            if(tileTypeName.compare(currTileName) == 0) {
                if(firstTile) {
                    firstTile = false;
                    continue;
                } else {
                    exportTileSinks(i);
                    break;
                }
            }
        }
    }

}

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static CompoundSettingMap torc::bitstream::Virtex7LibGen::getCompoundSettingsMap ( )

inlinestatic

Returns map of coumpound settings.

Definition at line 37 of file Virtex7LibGen.hpp.

                                                           {
            CompoundSettingMap compoundSettingMap;
            std::vector<std::string> acascregCompound;
            acascregCompound.push_back("AREG");
            compoundSettingMap["ACASCREG"] = acascregCompound;

            std::vector<std::string> bcascregCompound;
            bcascregCompound.push_back("BREG");
            compoundSettingMap["BCASCREG"] = bcascregCompound;

            return compoundSettingMap;
        }

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std::map<string, string> torc::bitstream::AssemblerLibGen::getDeviceToPackageMap ( )

inlineprotectedinherited

Get a map from device to default package.

Definition at line 186 of file AssemblerLibGen.hpp.

                                                       {
            std::map<string, string> deviceToPackageMap;
            deviceToPackageMap["xc5vfx130t"] = "FF1738";
            deviceToPackageMap["xc5vlx110t"] = "FF1136";
            deviceToPackageMap["xc7a100t"] = "FGG484";
            deviceToPackageMap["xc7z045"] = "FBG676";
            return deviceToPackageMap;
        }

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int torc::bitstream::AssemblerLibGen::getElementIndexFromName ( const string  inElementName, PrimitiveStructureSharedPtr  inPrimitiveStructurePtr  )

protectedinherited

Get index in Element array.

Definition at line 937 of file AssemblerLibGen.cpp.

                                                                                                                            {
    int elementIndex = -1, index = 0;
    const PrimitiveElementArray& elementsArray = inPrimitiveStructurePtr->getPrimitiveDefPtr()->getElements();
    PrimitiveElementArray::const_iterator pElements = elementsArray.begin();
    PrimitiveElementArray::const_iterator eElements = elementsArray.end();

    // For every primitive element (BEL) in the site
    while(pElements != eElements) {
        if(pElements->getName().compare(inElementName) == 0) {
            elementIndex = index;
            break;
        }
        pElements++; index++;
    }
    return elementIndex;
}

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AssemblerLibGen::DesignSharedPtr torc::bitstream::AssemblerLibGen::getHarnessDesignForSiteType ( const string &  inSiteType )

protectedinherited

Returns harness design pointer for the given site type.

Every site type has a harness design which serves as base generating Xdl for all configurations of the site type

Definition at line 347 of file AssemblerLibGen.cpp.

                                                                                                    {

    // Harness file name is of format <tile_type>-<site_type>.xdl
    string harnessFileName = mCurTileType + sNameSeparator + inSiteType + sXdlExtension;
    path harnessFilePath = mHarnessFolder / harnessFileName;

    DesignSharedPtr harnessDesignPtr;
    std::ifstream fileStream(harnessFilePath.string().c_str());
    if(!fileStream.good()) {
        std::cerr << "Could not open file " << harnessFilePath.string() << std::endl;
        return harnessDesignPtr;
    }
    torc::physical::XdlImporter importer;
    importer(fileStream, harnessFilePath.string());

    fileStream.close();

    // Return the design pointer
    harnessDesignPtr = importer.getDesignPtr();
    return harnessDesignPtr;
}

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virtual string torc::bitstream::Virtex7LibGen::getParentFamilyName ( )

inlineprotectedvirtual

Get parent family name.

Virtual Functions

Reimplemented from torc::bitstream::AssemblerLibGen.

Definition at line 84 of file Virtex7LibGen.hpp.

                                             {
            return "Virtex7";
        }

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AssemblerLibGen::PrimitiveStructuresSharedPtrMap torc::bitstream::Virtex7LibGen::getPrimitiveNameToStructreMap ( )

protectedvirtual

Populate primitive name to primitive structure map.

Creates map from primitive name to primitive structure object pointer

Implements torc::bitstream::AssemblerLibGen.

Definition at line 278 of file Virtex7LibGen.cpp.

                                                                                            {
    PrimitiveStructuresSharedPtrMap primitiveStructures;
    // look up the primitive def types
    typedef const torc::architecture::Array<const torc::architecture::PrimitiveDef>
        PrimitiveDefArray;
    PrimitiveDefArray & primitiveDefs = mSites.getSiteTypes();
    PrimitiveDefArray::const_iterator pPrimitiveDefs = primitiveDefs.begin();
    PrimitiveDefArray::const_iterator ePrimitiveDefs = primitiveDefs.end();
    // Store the corresponding primitive structures in a map.
    while(pPrimitiveDefs < ePrimitiveDefs) {
        // create a PrimitiveStructure object for this PrimitiveDef
        torc::packer::PrimitiveStructureSharedPtr primitiveStructurePtr(
            new torc::packer::Virtex7PrimitiveStructure(&*pPrimitiveDefs++));
        const torc::architecture::PrimitiveDef *primitiveDefPtr =
            primitiveStructurePtr->getPrimitiveDefPtr();
        const std::string & primitiveDefName = primitiveDefPtr->getName();
        // insert the PrimitiveStructure into the map
        if(!isSlicelType(primitiveDefName)) {
            primitiveStructures[primitiveDefName] = primitiveStructurePtr;
        } else {
            string sliceEven = primitiveDefName + "E";
            string sliceOdd = primitiveDefName + "O";
            primitiveStructures[sliceEven] = primitiveStructurePtr;
            primitiveStructures[sliceOdd] = primitiveStructurePtr;
        }
    }
    return primitiveStructures;
}

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virtual std::string torc::bitstream::Virtex7LibGen::getRambPrimaryPrimitive ( )

inlineprotectedvirtual

Returns primary primitive for Ramb site type.

Implements torc::bitstream::AssemblerLibGen.

Definition at line 57 of file Virtex7LibGen.hpp.

                                                    {
            return "RAMB36E1";
        }

std::map<string, string> torc::bitstream::Virtex7LibGen::getReferenceConfigMap ( )

inlineprotected

Get a map from config setting to reference value.

Definition at line 63 of file Virtex7LibGen.hpp.

                                                       {
            std::map<string, string> referenceConfigMap;
            referenceConfigMap["A5FFINIT"] = "INIT1";
            referenceConfigMap["B5FFINIT"] = "INIT1";
            referenceConfigMap["C5FFINIT"] = "INIT1";
            referenceConfigMap["D5FFINIT"] = "INIT1";
            referenceConfigMap["AFFINIT"] = "INIT1";
            referenceConfigMap["BFFINIT"] = "INIT1";
            referenceConfigMap["CFFINIT"] = "INIT1";
            referenceConfigMap["DFFINIT"] = "INIT1";
            referenceConfigMap["RAM_MODE"] = "TDP";
            referenceConfigMap["LFSR_EN_SET"] = "SET";
            referenceConfigMap["TEST_SET_P"] = "SET";
            referenceConfigMap["MASK"] = "000000000000";
            referenceConfigMap["PATTERN"] = "000000000000";

            return referenceConfigMap;
        }

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AssemblerLibGen::string torc::bitstream::AssemblerLibGen::getReferenceConfigValue ( const string &  inConfigSetting )

protectedinherited

Return config value which results in off bit in bitstream.

Returns reference config value for give config setting.

Definition at line 370 of file AssemblerLibGen.cpp.

                                                                                            {
    // if element present in the map of Element->ReferenceConfig, return it.
    std::map<std::string, std::string>::const_iterator pElementConfigMap;
    std::map<std::string, std::string>::const_iterator eElementConfigMap =
        mReferenceConfigMap.end();
    pElementConfigMap = mReferenceConfigMap.find(inConfigSetting);
    if(pElementConfigMap != eElementConfigMap) {
        return pElementConfigMap->second;
    }
    return string(sConfigValueOff);
}

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std::vector< std::string > torc::bitstream::Virtex7LibGen::getTilesSupportedForPips ( )

protectedvirtual

Returns list of supported tiles. Assumes last tile is "LAST_TILE".

Returns list of supported tiles.

Implements torc::bitstream::AssemblerLibGen.

Definition at line 69 of file Virtex7LibGen.cpp.

                                                             {
    uint32_t supportedTileIndex = 0;
    std::vector<std::string> tilesSupported;
    while(sTilesSupportedForPips[supportedTileIndex].compare("LAST_TILE") != 0) {
        tilesSupported.push_back(sTilesSupportedForPips[supportedTileIndex++]);
    }
    return tilesSupported;
}

AssemblerLibGen::TileTypeToSiteTypeSet torc::bitstream::AssemblerLibGen::getTileTypeToSiteTypeMap ( void  )

inherited

Populate map of tile type to set of include site types.

A tile can contain more than one site. This functions returns a map from tile type to set of contained site types

Definition at line 277 of file AssemblerLibGen.cpp.

                                                                               {

    TileTypeToSiteTypeSet tileTypeToSiteTypeMap;
    const torc::architecture::Array<const Site>& allSites = mSites.getSites();

    for(uint i = 0; i < allSites.getSize(); i++) {

        const torc::architecture::Site& site = allSites[i];
        std::string siteType = site.getPrimitiveDefPtr()->getName();

        // Some sites can be instantiated via multiple primitives
        // We are interested in one particular primitive only.
        if(isRambSite(siteType))
            siteType = getRambPrimaryPrimitive();

        TileIndex tileIndex = site.getTileIndex();
        const TileInfo& tileInfo = mTiles.getTileInfo(tileIndex);
        const std::string &tileType = mTiles.getTileTypeName(tileInfo.getTypeIndex());

        // There is no entry in map corresponding to this tile type
        if(tileTypeToSiteTypeMap.find(tileType) == tileTypeToSiteTypeMap.end()) {
            std::set<std::string> siteTypeSet;
            // There are two slices contained in a tile. Micro bitstream for both the slices should be 
            // stored in library.
            if(!isSlicelType(siteType)) {
                siteTypeSet.insert(siteType);
            } else {
                string sliceEven = siteType + "E";
                string sliceOdd = siteType + "O";
                siteTypeSet.insert(sliceEven);
                siteTypeSet.insert(sliceOdd);
            }
            tileTypeToSiteTypeMap.insert(std::pair<std::string, std::set<std::string> >(tileType,
                siteTypeSet));
        } else {
            // There are 2 slices in a tile. The two sites should be treated differently.
            if(!isSlicelType(siteType)) {
                tileTypeToSiteTypeMap[tileType].insert(siteType);
            } else {
                string sliceEven = siteType + "E";
                string sliceOdd = siteType + "O";
                tileTypeToSiteTypeMap[tileType].insert(sliceEven);
                tileTypeToSiteTypeMap[tileType].insert(sliceOdd);
            }
        }
    }
    return tileTypeToSiteTypeMap;
}

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uint32_t torc::bitstream::Virtex7LibGen::getWordOffsetFromTileLocation ( TileRow  tileRow, TileCol  tileCol, BitstreamSharedPtr  inBitstreamPtr  )

protectedvirtual

Get word offset from tile row and col.

Implements torc::bitstream::AssemblerLibGen.

Definition at line 254 of file Virtex7LibGen.cpp.

                                                                                                                        {
    uint32_t bitIndexBegin = 0, bitIndexEnd = 0;
    boost::shared_ptr<Virtex7> virtex7Ptr = boost::dynamic_pointer_cast<Virtex7>(inBitstreamPtr);
    // ToDo: Uncomment after support is introduced
    uint32_t primaryXdlCol = virtex7Ptr->getPrimaryXdlColumn(tileRow, tileCol);
    virtex7Ptr->getXdlFrames(tileRow, primaryXdlCol, bitIndexBegin, 
                    bitIndexEnd, torc::bitstream::Bitstream::eBlockTypeCount);

    // Each frame covers the full height of clock region which contains many rows of tiles.
    // The library contains configuration bits only for the first row. So the word index has to
    // be offset to reach the correct row. The bit index remains same across rows.
    uint32_t outWordOffset = 0;
    if(bitIndexBegin != bitIndexEnd) {
        outWordOffset = Virtex7::eFrameLength - (bitIndexEnd >> 5); // eFrameLength is number of words in a frame
//      outWordOffset = bitIndexBegin >> 5;
    }

    std::cout << "*******Word offset " << outWordOffset << std::endl;

    return outWordOffset;

}

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uint32_t torc::bitstream::AssemblerLibGen::getWordOffsetFromXdlFile ( path  inBitstreamPath, BitstreamSharedPtr  inBitstreamPtr  )

protectedinherited

Get word offset in frame for the site/pip in corresponding Xdl.

Get word offset from Xdl.

Definition at line 883 of file AssemblerLibGen.cpp.

                                                                                                          {

    path xdlFilePath = inBitstreamPath.replace_extension(".xdl");
    std::ifstream xdlStream(xdlFilePath.string().c_str());
    if(!xdlStream.good()) {
        std::cout << "File " << xdlFilePath.string() << " not found" << std::endl;
        return 0;
    }
    torc::physical::XdlImporter xdlImporter;
    xdlImporter(xdlFilePath);

    // Get design pointer and related data base
    torc::physical::DesignSharedPtr designPtr = xdlImporter.getDesignPtr();

    torc::architecture::DDB ddb(designPtr->getDevice());
    const Tiles &tiles = ddb.getTiles();

    torc::architecture::xilinx::TileRow tileRow;
    torc::architecture::xilinx::TileCol tileCol;

    bool pipDesign = false;
    // We know this XDL has only one NET and one PIP
    if(designPtr->netsBegin() != designPtr->netsEnd()) {
        torc::physical::NetSharedPtr netPtr = *(designPtr->netsBegin());
        if(netPtr->pipsBegin() != netPtr->pipsEnd()) {
            std::cout << "\tProcessing NET" << std::endl;
            pipDesign = true;
            torc::physical::Pip pip = *(netPtr->pipsBegin());
            torc::architecture::xilinx::TileIndex tileIndex = tiles.findTileIndex(pip.getTileName());
            const torc::architecture::TileInfo& tileInfo = tiles.getTileInfo(tileIndex);
            tileRow = tileInfo.getRow();
            tileCol = tileInfo.getCol();
        }
    }

    // If there is no pip, it is an XDL for logic element.
    if(pipDesign == false) {
        const Sites &sites = ddb.getSites();
        torc::physical::InstanceSharedPtr instancePtr = *(designPtr->instancesBegin());
        SiteIndex siteIndex = sites.findSiteIndex(instancePtr->getSite());
        const Site& site = sites.getSite(siteIndex);

        // look up the site tile index
        TileIndex tileIndex = site.getTileIndex();
        const TileInfo& tileInfo = tiles.getTileInfo(tileIndex);
        tileRow = tileInfo.getRow();
        tileCol = tileInfo.getCol();
    }

    return getWordOffsetFromTileLocation(tileRow, tileCol, inBitstreamPtr);

}

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void torc::bitstream::Virtex7LibGen::initialize ( void  )

protected

Do architecture specific part of initialization.

Architecture specific part of initializing the object

Definition at line 52 of file Virtex7LibGen.cpp.

                               {

    mCompoundSettingMap = getCompoundSettingsMap();
    mReferenceConfigMap = getReferenceConfigMap();
}

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bool torc::bitstream::AssemblerLibGen::isCompoundSettingHead ( const string &  inSetting )

inlineprotectedinherited

Is given setting head of compound setting group.

Definition at line 144 of file AssemblerLibGen.hpp.

                                                            {
            CompoundSettingMap::const_iterator pElement = mCompoundSettingMap.find(inSetting);
            // If element found in the compound settings map
            if(pElement != mCompoundSettingMap.end()) {
                return true;
            }
            return false;
        }

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bool torc::bitstream::AssemblerLibGen::isDspSite ( const string &  inSiteType )

inlineprotectedinherited

Returns true is input is a DSP site.

Definition at line 140 of file AssemblerLibGen.hpp.

                                                 {
            return boost::regex_search(inSiteType, boost::regex("DSP"));
        }

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bool torc::bitstream::AssemblerLibGen::isRambSite ( const string &  inSiteType )

inlineprotectedinherited

Returns true if input is a RAMB site.

Definition at line 136 of file AssemblerLibGen.hpp.

                                                  {
            return boost::regex_search(inSiteType, boost::regex("RAMB"));
        }

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bool torc::bitstream::Virtex7LibGen::isSiteTypeSupported ( const string &  siteType )

protectedvirtual

Returns true if site type is supported.

Returns true for the sites which are supported by library generation process

Implements torc::bitstream::AssemblerLibGen.

Definition at line 59 of file Virtex7LibGen.cpp.

                                                              {
    return (siteType.compare("SLICEM") == 0     || 
            siteType.compare("SLICELO") == 0    || siteType.compare("SLICELE") == 0 ||
            siteType.compare("*RAMB36E1") == 0 || siteType.compare("*DSP48E1") == 0 || 
//          siteType.compare("BUFGCTRL") == 0   || siteType.compare("BUFDS") == 0 || 
            siteType.compare("*BUFR") == 0      || siteType.compare("*BUFG") == 0)
            ;
}

bool torc::bitstream::AssemblerLibGen::isSlicelType ( const string &  inSiteType )

inlineprotectedinherited

Return true if site type is SLICEL.

Definition at line 126 of file AssemblerLibGen.hpp.

                                                    {
            return boost::regex_search(inSiteType.begin(), inSiteType.end(), boost::regex("SLICEL"));
        }

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void torc::bitstream::AssemblerLibGen::printTileTypeToSiteTypeMapInfo ( TileTypeToSiteTypeSet  tileTypeToSiteType )

inherited

Print the tile type to site type information.

Prints list of tile types and the site types in each of the tile types

Definition at line 327 of file AssemblerLibGen.cpp.

                                                                                             {
    TileTypeToSiteTypeSet::const_iterator p = tileTypeToSiteType.begin();
    TileTypeToSiteTypeSet::const_iterator e = tileTypeToSiteType.end();
    std::cout << "Tile type to Site type info:" << std::endl;
    while(p != e) {
        std::cout << "  Tile: " << p->first << std::endl;
        std::set<std::string>::iterator pSites = p->second.begin();
        std::set<std::string>::iterator eSites = p->second.end();
        while(pSites != eSites) {
            std::cout << "\t" << *pSites;
            pSites++;
        }
        std::cout << std::endl;
        p++;
    }
}

void torc::bitstream::AssemblerLibGen::saveLibraryMapToFile ( TileTypeToSiteType &  inLibrary )

protectedinherited

Save library map to file.

Saves the library map structure in database format

Definition at line 955 of file AssemblerLibGen.cpp.

                                                                        {

    std::string dbFileName = getParentFamilyName() + sLibExtension;
    path dbFilePath = mLibraryFolder / dbFileName;
    std::ofstream dbFile(dbFilePath.string().c_str(), std::ofstream::binary);
    if(!dbFile.is_open()) {
        std::cout << "Could not open file " << dbFilePath.string() << " to write" << std::endl;
        return;
    }

    std::cout << "Storing combined micro-bitstream in " << dbFilePath.string() << std::endl;
    dbFile.write("<<<<BITLIBDB>>>>", 16);
//  std::cout << "Tile map size " << sizeof(tileMap.size()) << std::endl;
    uint32_t dataSize;
    dataSize = inLibrary.size();
    dbFile.write((char *) (&dataSize), sizeof(dataSize));
    std::cout << "Total tiles " << dataSize << std::endl;

    // Now go over the map data structure and write it to a file
    // File format is given at the top of this file
    TileTypeToSiteType::const_iterator pTiletypes = inLibrary.begin();
    TileTypeToSiteType::const_iterator eTiletypes = inLibrary.end();
    while(pTiletypes != eTiletypes) {
        // Write the tile name char count, name string and element count
        dataSize = pTiletypes->first.size();
        dbFile.write((const char *) &dataSize, sizeof(dataSize));
        dbFile.write((const char *) pTiletypes->first.c_str(), pTiletypes->first.size());
        dataSize = pTiletypes->second.size();
        dbFile.write((const char*) &dataSize, sizeof(dataSize));
        std::cout << "Tile type " << pTiletypes->first << " has " << pTiletypes->second.size()
            << " sites." << std::endl;

        // Iterate over elements
        SiteTypeToConfigSettings::const_iterator pSiteTypes = pTiletypes->second.begin();
        SiteTypeToConfigSettings::const_iterator eSiteTypes = pTiletypes->second.end();
        while(pSiteTypes != eSiteTypes) {

            // Write site type name char count, name string and config setting count
            dataSize = pSiteTypes->first.size();
            dbFile.write((const char *) &dataSize, sizeof(dataSize));
            dbFile.write((const char *) pSiteTypes->first.c_str(), pSiteTypes->first.size());
            dataSize = pSiteTypes->second.size();
            dbFile.write((const char *) &dataSize, sizeof(dataSize));
//          std::cout << "   Element type " << pSiteTypes->first << " has "
//              << pSiteTypes->second.size() << " configs." << std::endl;

            // Itereate over configs
            ConfigSettingsToValues::const_iterator pConfigSettings = pSiteTypes->second.begin();
            ConfigSettingsToValues::const_iterator eConfigSettings = pSiteTypes->second.end();
            while(pConfigSettings != eConfigSettings) {
                // Write config namem char count, name string and count of bit addresses
                dataSize = pConfigSettings->first.size();
                dbFile.write((const char *) &dataSize, sizeof(dataSize));
                dbFile.write(pConfigSettings->first.c_str(), pConfigSettings->first.size());
                dataSize = pConfigSettings->second.size();
                dbFile.write((const char *) &dataSize, sizeof(dataSize));

                ConfigValuesToBits::const_iterator pConfigValues = pConfigSettings->second.begin();
                ConfigValuesToBits::const_iterator eConfigValues = pConfigSettings->second.end();

                while(pConfigValues != eConfigValues) {

                    dataSize = pConfigValues->first.size();
                    dbFile.write((const char *) &dataSize, sizeof(dataSize));
                    dbFile.write(pConfigValues->first.c_str(), pConfigValues->first.size());
                    dataSize = pConfigValues->second.size();
                    dbFile.write((const char *) &dataSize, sizeof(dataSize));
                    // Write the bit addresses
                    for(std::vector<uint32_t>::const_iterator iter = pConfigValues->second.begin(); iter
                        != pConfigValues->second.end(); iter++) {
                        dbFile.write((char *) &*iter, sizeof(uint32_t));
                    }
//                  std::cout << "\t" << pConfigSettings->first << " " << pConfigSettings->second.size();
                    pConfigValues++;
                }
                pConfigSettings++;
            }
//          std::cout << std::endl;
            pSiteTypes++;
        }
        pTiletypes++;
    }

    // Close file
    dbFile.close();

}

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void torc::bitstream::AssemblerLibGen::setConfigAndGenerateXdl ( const string &  inConfigSetting, const string &  inConfigValue, const string &  inXdlFileName, DesignSharedPtr  inOutDesignPtr  )

protectedinherited

Set given config and generate Xdl.

Definition at line 703 of file AssemblerLibGen.cpp.

                                                                 {

    InstanceSharedPtr instancePtr = *(inOutDesignPtr->instancesBegin());

    instancePtr->setConfig(inConfigSetting, "", inConfigValue);
    // create the appropriate file paths
    path xdlFilePath = mXdlGenerationFolder / inXdlFileName;

    // Export the design as XDL
    std::fstream xdlExport(xdlFilePath.string().c_str(), std::ios_base::out);
    torc::physical::XdlExporter fileExporter(xdlExport);
    fileExporter(inOutDesignPtr);
}

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void torc::bitstream::AssemblerLibGen::stitchMicroBitstreams ( )

inherited

Stitch micro-bitstreams in mXdlGenerationFolder.

Stitch micro-bitstreams in folder mXdlGenerationFolder Go over all files with extension .cbit, split file name on '-' to get family, tile type, site type, config setting, and config value. The vector of address and names are stored in map data structure and then stored in a file. File format is - <<<<BITLIBDB>>>> Number of tile types Tile type name char count Tile type Number of sites Site type name char count Site type Config seting name char count Config setting Config value name char count Config value Number of 32bit words in compressed bitstream words

Definition at line 802 of file AssemblerLibGen.cpp.

                                            {
    std::cout << "Stitching micro bitstream files..." << std::endl; 
    // Maps to store the information on tile type, elements and configs
    std::vector<ConfigValuesToBits> configMapVector;
    std::vector<ConfigSettingsToValues> settingsToValuesMap;
    std::vector<SiteTypeToConfigSettings> siteToSettingsMap;
    TileTypeToSiteType library;

    // Go over all the files in the directory
    boost::filesystem::directory_iterator eFiles;
    boost::filesystem::directory_iterator pFiles(mXdlGenerationFolder);
    while(pFiles != eFiles) {

        // If it is a compressed bit file (.cbit extension)
        if(pFiles->path().extension() == ".cbit") {

            std::ifstream libBitFile(pFiles->path().string().c_str(), std::ios::binary);
            if(!libBitFile.good()) {
                std::cerr << "ERROR: Could not open micro-bitstream file " << pFiles->path().string() << std::endl;
                return;
            }

            // Get number of bits set and put the bit addresses in a vector
            int32_t numSetBits, bitAddr;
            libBitFile.read((char *) &numSetBits, 4);
            std::cout << "\t" << pFiles->path().filename() <<  " opened. Bit count " << numSetBits << std::endl;
            std::vector<uint32_t> bitAddresses;
            for(int i = 0; i < numSetBits && !libBitFile.eof(); i++) {
                libBitFile.read((char *) &bitAddr, 4);
                bitAddresses.push_back(bitAddr);
            }

            // Get the file name without extension and split the name to get tile type, site type element/source wire and config/sink wire.
            boost::filesystem::path filePath(pFiles->path());
            // (Note: Wrapping filename() as a path for compatibility with Boost.Filesystem V2)
            std::string fileName(boost::filesystem::path(filePath.replace_extension().filename()).string());

            std::vector<std::string> splitVector;
            boost::algorithm::split(splitVector, fileName, boost::algorithm::is_any_of(sNameSeparator));

            // Get the tile type, element(source wire) and config (sink wire)from the split string
            string tileType(splitVector[1]);
            string siteType(splitVector[2]);
            string configSetting(splitVector[3]);
            string configValue(splitVector[4]);

            // if tile not found in map, a new tile type has come up. Add it to the map.
            // Create another map for Element-config and push it in vector so that it is not destroyed.
            if(library.find(tileType) == library.end()) {
                SiteTypeToConfigSettings siteToSettings;
                siteToSettingsMap.push_back(siteToSettings);
                library[tileType] = siteToSettingsMap.back();
            }

            // Check if site type is present in map
            if(library[tileType].find(siteType) == library[tileType].end()) {
                ConfigSettingsToValues settingToValues;
                settingsToValuesMap.push_back(settingToValues);
                library[tileType][siteType] = settingsToValuesMap.back();
            }

            // Check if config setting is present in library
            if(library[tileType][siteType].find(configSetting) == library[tileType][siteType].end()) {
                ConfigValuesToBits valuesToBits;
                configMapVector.push_back(valuesToBits);
                library[tileType][siteType][configSetting] = configMapVector.back();
            }

            // Mapping the config to bit addresses
            library[tileType][siteType][configSetting][configValue] = bitAddresses;

        }

        pFiles++;
    }

    saveLibraryMapToFile(library);

}

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Field Documentation

CompoundSettingMap torc::bitstream::AssemblerLibGen::mCompoundSettingMap

protectedinherited

Map from one compound setting to vector of other related settings.

Definition at line 224 of file AssemblerLibGen.hpp.

string torc::bitstream::AssemblerLibGen::mCurTileType

protectedinherited

Tile type for which Xdl are being generated currently.

Definition at line 228 of file AssemblerLibGen.hpp.

DDB& torc::bitstream::AssemblerLibGen::mDB

protectedinherited

Database object.

Definition at line 217 of file AssemblerLibGen.hpp.

std::map<string, string> torc::bitstream::AssemblerLibGen::mDeviceToPackageMap

protectedinherited

Map from device to pakcage.

Definition at line 225 of file AssemblerLibGen.hpp.

path torc::bitstream::AssemblerLibGen::mHarnessFolder

protectedinherited

Harness folder.

Definition at line 220 of file AssemblerLibGen.hpp.

path torc::bitstream::AssemblerLibGen::mLibraryFolder

protectedinherited

Path to library folder.

Definition at line 223 of file AssemblerLibGen.hpp.

std::map<string, string> torc::bitstream::AssemblerLibGen::mReferenceConfigMap

protectedinherited

Map from config setting to reference config value.

Definition at line 226 of file AssemblerLibGen.hpp.

const Sites& torc::bitstream::AssemblerLibGen::mSites

protectedinherited

Sites from the database object.

Definition at line 218 of file AssemblerLibGen.hpp.

const Tiles& torc::bitstream::AssemblerLibGen::mTiles

protectedinherited

Tiles from the database object.

Definition at line 219 of file AssemblerLibGen.hpp.

path torc::bitstream::AssemblerLibGen::mXdlGenerationFolder

protectedinherited

Folder in which Xdls will be generated.

Definition at line 221 of file AssemblerLibGen.hpp.

path torc::bitstream::AssemblerLibGen::mXdlGenerationReferenceFolder

protectedinherited

Folder in which reference Xdls will be genered.

Definition at line 222 of file AssemblerLibGen.hpp.

const char * torc::bitstream::AssemblerLibGen::sConfigValueOff = "#OFF"

staticprotectedinherited

Config value to switch off element (#OFF)

Definition at line 230 of file AssemblerLibGen.hpp.

const int torc::bitstream::Virtex7LibGen::sCrcWordIndex = 50

staticprotected

This have to be changed for different Family.

Definition at line 98 of file Virtex7LibGen.hpp.

const char * torc::bitstream::AssemblerLibGen::sLibExtension = ".ldb"

staticprotectedinherited

.ldb

Definition at line 232 of file AssemblerLibGen.hpp.

const char * torc::bitstream::AssemblerLibGen::sNameSeparator = "-"

staticprotectedinherited

Symbol to separate out parts of file name.

static const initialization

Definition at line 229 of file AssemblerLibGen.hpp.

const string torc::bitstream::Virtex7LibGen::sTilesSupportedForPips

staticprotected

Initial value:

= {
                                "INT_R",
                                "INT_L",
                                "CLBLM_L",
                                "CLBLM_R",
                                "CLK_BUFG_BOT_R",
                                "CLK_BUFG_REBUF",
                                "CLK_BUFG_TOP_R",
                                "CLK_HROW_BOT_R",
                                "CLK_HROW_TOP_R",
                                "CLK_MTBF2",
                                "CLK_PMV",
                                "CLK_PMV2",
                                "HCLK_CMT",
                                "HCLK_IOI",
                                "HCLK_IOI3",
                                "HCLK_BRAM",
                                "HCLK_CLB",
                                "HCLK_GTX",
                                "HCLK_IOB",
                                "HCLK_VBRK",
                                "LAST_TILE"
                            }

Array of supported routing tiles.

Definition at line 99 of file Virtex7LibGen.hpp.

const char * torc::bitstream::AssemblerLibGen::sXdlExtension = ".xdl"

staticprotectedinherited

.xdl

Definition at line 231 of file AssemblerLibGen.hpp.

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The documentation for this class was generated from the following files:

• Virtex7LibGen.hpp
• Virtex7LibGen.cpp