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AssemblerLibGen.hpp
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15 
16 /// \brief Base class to encapsulate micro-bitstream library generation code
17 
18 #ifndef ASSEMBLERLIBGEN_HPP_
19 #define ASSEMBLERLIBGEN_HPP_
20 
21 #include <iostream>
22 #include <vector>
23 #include <map>
24 #include "../Assembler.hpp"
25 #include "torc/Architecture.hpp"
26 #include "torc/physical/Design.hpp"
28 #include "torc/physical/Net.hpp"
31 #include <boost/filesystem/path.hpp>
32 #include <boost/regex.hpp>
33 
34 namespace torc {
35 namespace bitstream {
36  // Class to encapsulate micro-bitstream generation functions
38 public:
39  // Type definitions imported from torc namespace
40  /// \brief Imported type name.
42  /// \brief Imported type name.
44  /// \brief Imported type name.
46  /// \brief Imported type name.
48  /// \brief Imported type name.
50  /// \brief Imported type name.
52  /// \brief Imported type name.
54  /// \brief Imported type name.
56  /// \brief Imported type name.
58  /// \brief Imported type name.
60  /// \brief Imported type name.
62  /// \brief Imported type name.
64  /// \brief Imported type name.
66  /// \brief Imported type name.
68  /// \brief Imported type name.
70  /// \brief Imported type name.
72  /// \brief Imported type name.
74  //Typedefs from Assembler class
79  /// \brief Map from one setting to vector of related setings
81 
82  // Type definitions for Maps
83  /// \brief Typedef of map from tile type to set of site type
84  typedef std::map<std::string,std::set<std::string> > TileTypeToSiteTypeSet;
85  /// \brief Typedef of map from primitive name to primitive structure shared pointer
86  typedef std::map<std::string, PrimitiveStructureSharedPtr> PrimitiveStructuresSharedPtrMap;
87  public:
88  /// \brief Constructor
89  AssemblerLibGen(string inDevice, path inHarnessFolder, path inXdlGenerationFolder)
90  :mDB(*(new DDB(inDevice))), mSites(mDB.getSites()), mTiles(mDB.getTiles()),
91  mHarnessFolder(inHarnessFolder), mXdlGenerationFolder(inXdlGenerationFolder) {
92 
93  initialize();
94  }
95  /// \brief Destructor
96  virtual ~AssemblerLibGen() {
97  delete &mDB;
98  }
99 
100  // Public functions
101  /// \brief Generrate Xdls for logic sites
102  void generateLogicXdls();
103  /// \brief Generate Xdls for routing pips
104  void generateWireXdls();
105  /// \brief Generate Xdls for both logic sites and routing pips
107  /// \brief Generate bitstream for all Xdls in mXdlGenerationFolder and mXdlGenerationReferenceFolder
108  void generateBitstreams();
109  /// \brief Compress all Xilinx bitfiles in mXdlGenerationFolder
110  void compressBitFiles();
111  /// \brief Stitch micro-bitstreams in mXdlGenerationFolder
112  void stitchMicroBitstreams();
113  /// \brief Populate map of tile type to set of include site types
115  /// \brief Print the tile type to site type information
116  void printTileTypeToSiteTypeMapInfo(TileTypeToSiteTypeSet tileTypeToSiteType);
117 
118  protected:
119  /// \brief Initialize object of this class
120  void initialize();
121  /// \brief Export all pips within the specified tile
122  void exportTileSinks(TileIndex inTileIndex);
123  /// \brief Export a single pip.
124  void exportSink(Tilewire& inSource, Tilewire& inSink);
125  /// \brief Return true if site type is SLICEL
126  bool isSlicelType(const string &inSiteType) {
127  return boost::regex_search(inSiteType.begin(), inSiteType.end(), boost::regex("SLICEL"));
128  }
129  /// \brief Returns harness design pointer for the given site type
130  DesignSharedPtr getHarnessDesignForSiteType(const string &inSiteType);
131  /// \brief Return config value which results in off bit in bitstream
132  string getReferenceConfigValue(const string &inConfigSetting);
133  /// \brief Create an empty design with same metadata. Does not copy configurations
135  /// \brief Returns true if input is a RAMB site
136  bool isRambSite(const string &inSiteType) {
137  return boost::regex_search(inSiteType, boost::regex("RAMB"));
138  }
139  /// \brief Returns true is input is a DSP site
140  bool isDspSite(const string &inSiteType) {
141  return boost::regex_search(inSiteType, boost::regex("DSP"));
142  }
143  /// \brief Is given setting head of compound setting group
144  bool isCompoundSettingHead(const string &inSetting) {
145  CompoundSettingMap::const_iterator pElement = mCompoundSettingMap.find(inSetting);
146  // If element found in the compound settings map
147  if(pElement != mCompoundSettingMap.end()) {
148  return true;
149  }
150  return false;
151  }
152  /// \breif Create Xdls for each config value of the config setting
154  PrimitiveStructureSharedPtr const inPrimitiveStructurePtr, const string &inSiteType,
155  DesignSharedPtr inHarnessDesignPtr);
156  /// \brief Set config value and create Xdl
157  void createXdlForGeneralConfigSetting(const string &inConfigSetting, const string &inConfigVal,
158  const string &inXdlFileNamePartial, DesignSharedPtr inHarnessDesignPtr);
159  /// \brief Create Xdl with a Ramb instane and no configuration
160  void createRambBaseXdl(const string &inSiteType, DesignSharedPtr inHarnessDesignPtr);
161  /// \brief Create Xdl for configurations which hex string values
162  void createHexConfigXdl(const string &inConfigSetting, const string &inSiteType, int numHexChars,
163  DesignSharedPtr inHarnessDesignPtr);
164  /// \brief Create Xdls for compound settings
165  void createXdlForCompoundSettings(const PrimitiveElement &inElement, const string &inSiteType,
166  PrimitiveStructureSharedPtr inPrimitiveStructurePtr, DesignSharedPtr inHarnessDesignPtr);
167  /// \brief Create Xdls for orphan elements with empty reference Xdl
169  const string &inXdlFileNamePartial, DesignSharedPtr inHarnessDesignPtr);
170  /// \brief Create Xdl for Lut
171  void createXdlForLut(const torc::architecture::PrimitiveElement &inElement, const string &inXdlFileNamePartial,
172  DesignSharedPtr inHarnessDesignPtr);
173  /// \brief Create reference Xdl for given config setting
174  void createReferenceXdlForConfigSetting(const string &inConfigSetting, DesignSharedPtr outHarnessDesignPtr,
175  const string &inXdlFileNamePartial);
176  /// \brief Set given config and generate Xdl
177  void setConfigAndGenerateXdl(const string &inConfigSetting, const string & inConfigValue,
178  const string &inXdlFileName, DesignSharedPtr inOutDesignPtr);
179  /// \brief Get word offset in frame for the site/pip in corresponding Xdl
180  uint32_t getWordOffsetFromXdlFile(path inBitstreamPath, BitstreamSharedPtr inBitstreamPtr);
181  /// \brief Get index in Element array
182  int getElementIndexFromName(const string inElementName, PrimitiveStructureSharedPtr inPrimitiveStructurePtr);
183  /// \brief Save library map to file
184  void saveLibraryMapToFile(TileTypeToSiteType &inLibrary);
185  /// \brief Get a map from device to default package
186  std::map<string, string> getDeviceToPackageMap() {
187  std::map<string, string> deviceToPackageMap;
188  deviceToPackageMap["xc5vfx130t"] = "FF1738";
189  deviceToPackageMap["xc5vlx110t"] = "FF1136";
190  deviceToPackageMap["xc7a100t"] = "FGG484";
191  deviceToPackageMap["xc7z045"] = "FBG676";
192  return deviceToPackageMap;
193  }
194 
195  /// Virtual Functions
196  /// \brief Returns parent family name
197  virtual string getParentFamilyName() {
198  return mDB.getFamilyName();
199  }
200  /// \brief Returns true if site type is supported
201  virtual bool isSiteTypeSupported(const string &inSiteType) = 0;
202  /// \brief Returns vector of supported tiles.
203  virtual std::vector<std::string> getTilesSupportedForPips() = 0;
204  /// \brie Returns primary primitivie for RAMB site type
205  virtual std::string getRambPrimaryPrimitive() = 0;
206  /// \brief Compress the diff of primary bitstream and reference bitstream
207  virtual void compressBitFile(path primaryFile, path referenceFile) = 0;
208  /// \brief Get word offset from tile location
209  virtual uint32_t getWordOffsetFromTileLocation(TileRow tileRow, TileCol tileCol,
210  BitstreamSharedPtr inBitstreamPtr) = 0;
211  /// \brief Populate primitive name to primitive structure map
213  /// \brief Generate micro-bitstreams for memory elements like LUT in RAM mode
214  virtual void generateMemoryMicroBitstream() = 0;
215 
216  protected:
217  DDB &mDB; ///< Database object
218  const Sites &mSites; ///< Sites from the database object
219  const Tiles &mTiles; ///< Tiles from the database object
220  path mHarnessFolder; ///< Harness folder
221  path mXdlGenerationFolder; ///< Folder in which Xdls will be generated
222  path mXdlGenerationReferenceFolder; ///< Folder in which reference Xdls will be genered
223  path mLibraryFolder; ///< Path to library folder
224  CompoundSettingMap mCompoundSettingMap; ///< Map from one compound setting to vector of other related settings
225  std::map<string, string> mDeviceToPackageMap; ///< Map from device to pakcage
226  std::map<string, string> mReferenceConfigMap; ///< Map from config setting to reference config value
227 
228  string mCurTileType; ///< Tile type for which Xdl are being generated currently
229  static const char *sNameSeparator; ///< Symbol to separate out parts of file name
230  static const char *sConfigValueOff; ///< Config value to switch off element (#OFF)
231  static const char *sXdlExtension; ///< .xdl
232  static const char *sLibExtension; ///< .ldb
233 
234  };
235 }
236 }
237 
238 #endif /* ASSEMBLERLIBGEN_HPP_ */
void generateWireXdls()
Generate Xdls for routing pips.
std::string string
Imported type name.
Encapsulation of a tile index in an unsigned 32-bit integer.
torc::physical::InstanceSharedPtr InstanceSharedPtr
Imported type name.
Encapsulation of a tile row in an unsigned 16-bit integer.
path mXdlGenerationFolder
Folder in which Xdls will be generated.
std::map< const string, std::vector< string > > CompoundSettingMap
Element name to vector of related element names that collectively affect bits.
Definition: Assembler.hpp:71
torc::architecture::TileInfo TileInfo
Imported type name.
torc::bitstream::Assembler::ConfigValuesToBits ConfigValuesToBits
torc::architecture::DDB DDB
Imported type name.
static const char * sLibExtension
.ldb
void createXdlForOrphanElements(const torc::architecture::PrimitiveElement &inElement, const string &inXdlFileNamePartial, DesignSharedPtr inHarnessDesignPtr)
Create Xdls for orphan elements with empty reference Xdl.
Encapsulation of a tile column in an unsigned 16-bit integer.
Main torc::architecture namespace header.
std::map< string, string > getDeviceToPackageMap()
Get a map from device to default package.
Device database, including complete wiring and logic support.
Definition: DDB.hpp:42
void printTileTypeToSiteTypeMapInfo(TileTypeToSiteTypeSet tileTypeToSiteType)
Print the tile type to site type information.
torc::architecture::PrimitiveElementArray PrimitiveElementArray
Imported type name.
std::map< const string, ConfigValuesToBits > ConfigSettingsToValues
Map from config setting to config values. ConfigSettingsToValues.
Definition: Assembler.hpp:75
bool isRambSite(const string &inSiteType)
Returns true if input is a RAMB site.
const string & getFamilyName(void) const
Returns the family name.
Definition: DDB.hpp:134
const Sites & mSites
Sites from the database object.
Header for the Instance class.
void createXdlForGeneralConfigSetting(const string &inConfigSetting, const string &inConfigVal, const string &inXdlFileNamePartial, DesignSharedPtr inHarnessDesignPtr)
Set config value and create Xdl.
void exportTileSinks(TileIndex inTileIndex)
Export all pips within the specified tile.
path mXdlGenerationReferenceFolder
Folder in which reference Xdls will be genered.
virtual ~AssemblerLibGen()
Destructor.
bool isSlicelType(const string &inSiteType)
Return true if site type is SLICEL.
std::map< const string, SiteTypeToConfigSettings > TileTypeToSiteType
Map from tile type to site types. Includes routing as a site type.
Definition: Assembler.hpp:79
torc::architecture::Sites Sites
Imported type name.
void generateLogicAndWireXdl()
Generate Xdls for both logic sites and routing pips.
Header for the PrimitiveStructure class.
torc::architecture::PrimitiveElement PrimitiveElement
Imported type name.
torc::architecture::Site Site
Imported type name.
static const char * sNameSeparator
Symbol to separate out parts of file name.
void setConfigAndGenerateXdl(const string &inConfigSetting, const string &inConfigValue, const string &inXdlFileName, DesignSharedPtr inOutDesignPtr)
Set given config and generate Xdl.
virtual void generateMemoryMicroBitstream()=0
Generate micro-bitstreams for memory elements like LUT in RAM mode.
int getElementIndexFromName(const string inElementName, PrimitiveStructureSharedPtr inPrimitiveStructurePtr)
Get index in Element array.
std::string string
uint32_t getWordOffsetFromXdlFile(path inBitstreamPath, BitstreamSharedPtr inBitstreamPtr)
Get word offset in frame for the site/pip in corresponding Xdl.
std::map< std::string, std::set< std::string > > TileTypeToSiteTypeSet
Typedef of map from tile type to set of site type.
void saveLibraryMapToFile(TileTypeToSiteType &inLibrary)
Save library map to file.
virtual void compressBitFile(path primaryFile, path referenceFile)=0
Compress the diff of primary bitstream and reference bitstream.
string getReferenceConfigValue(const string &inConfigSetting)
Return config value which results in off bit in bitstream.
void createRambBaseXdl(const string &inSiteType, DesignSharedPtr inHarnessDesignPtr)
Create Xdl with a Ramb instane and no configuration.
void exportSink(Tilewire &inSource, Tilewire &inSink)
Export a single pip.
virtual uint32_t getWordOffsetFromTileLocation(TileRow tileRow, TileCol tileCol, BitstreamSharedPtr inBitstreamPtr)=0
Get word offset from tile location.
Encapsulation of a device logic site.
Definition: Site.hpp:30
std::map< string, string > mReferenceConfigMap
Map from config setting to reference config value.
CompoundSettingMap mCompoundSettingMap
Map from one compound setting to vector of other related settings.
AssemblerLibGen(string inDevice, path inHarnessFolder, path inXdlGenerationFolder)
Constructor.
string mCurTileType
Tile type for which Xdl are being generated currently.
Site type and population data for the family and the device.
Definition: Sites.hpp:45
static const char * sConfigValueOff
Config value to switch off element (#OFF)
Header for the Design class.
Encapsulation of a device tile and wire pair.
Definition: Tilewire.hpp:39
const Tiles & mTiles
Tiles from the database object.
Tile map, tile type, and wire information for the family and device.
Definition: Tiles.hpp:36
virtual bool isSiteTypeSupported(const string &inSiteType)=0
Returns true if site type is supported.
torc::architecture::Tiles Tiles
Imported type name.
torc::architecture::ExtendedWireInfo ExtendedWireInfo
Imported type name.
Header for the Bitstream class.
Encapsulation of a tile within a device tile map.
Definition: TileInfo.hpp:33
boost::shared_ptr< Net > NetSharedPtr
Shared pointer encapsulation of a Net.
Verbose encapsulation of a wire's information.
void createXdlsForConfigSetting(const torc::architecture::PrimitiveElement &inElement, PrimitiveStructureSharedPtr const inPrimitiveStructurePtr, const string &inSiteType, DesignSharedPtr inHarnessDesignPtr)
Create Xdls for each config value of the config setting
boost::filesystem::path path
virtual std::string getRambPrimaryPrimitive()=0
Returns primary primitivie for RAMB site type
boost::shared_ptr< Instance > InstanceSharedPtr
Shared pointer encapsulation of an Instance.
void createXdlForCompoundSettings(const PrimitiveElement &inElement, const string &inSiteType, PrimitiveStructureSharedPtr inPrimitiveStructurePtr, DesignSharedPtr inHarnessDesignPtr)
Create Xdls for compound settings.
TileTypeToSiteTypeSet getTileTypeToSiteTypeMap(void)
Populate map of tile type to set of include site types.
std::map< std::string, PrimitiveStructureSharedPtr > PrimitiveStructuresSharedPtrMap
Typedef of map from primitive name to primitive structure shared pointer.
bool isCompoundSettingHead(const string &inSetting)
Is given setting head of compound setting group.
torc::bitstream::Assembler::ConfigSettingsToValues ConfigSettingsToValues
boost::shared_ptr< Design > DesignSharedPtr
Shared pointer encapsulation of a Design.
DesignSharedPtr getHarnessDesignForSiteType(const string &inSiteType)
Returns harness design pointer for the given site type.
torc::bitstream::Assembler::SiteTypeToConfigSettings SiteTypeToConfigSettings
bool isDspSite(const string &inSiteType)
Returns true is input is a DSP site.
void createReferenceXdlForConfigSetting(const string &inConfigSetting, DesignSharedPtr outHarnessDesignPtr, const string &inXdlFileNamePartial)
Create reference Xdl for given config setting.
std::map< const string, ConfigSettingsToValues > SiteTypeToConfigSettings
Map from site type to config settings. SiteTypeToConfigSettings.
Definition: Assembler.hpp:77
torc::physical::NetSharedPtr NetSharedPtr
Imported type name.
static const char * sXdlExtension
.xdl
Encapsulation of a primitive site element. Primitive elements are subcomponents of logic primitive s...
void stitchMicroBitstreams()
Stitch micro-bitstreams in mXdlGenerationFolder.
void createHexConfigXdl(const string &inConfigSetting, const string &inSiteType, int numHexChars, DesignSharedPtr inHarnessDesignPtr)
Create Xdl for configurations which hex string values.
void compressBitFiles()
Compress all Xilinx bitfiles in mXdlGenerationFolder.
void generateBitstreams()
Generate bitstream for all Xdls in mXdlGenerationFolder and mXdlGenerationReferenceFolder.
path mLibraryFolder
Path to library folder.
boost::shared_ptr< PrimitiveStructure > PrimitiveStructureSharedPtr
Shared pointer encapsulation of a PrimitiveStructure.
torc::bitstream::Assembler::TileTypeToSiteType TileTypeToSiteType
Header for the Net class.
void generateLogicXdls()
Generrate Xdls for logic sites.
void initialize()
Initialize object of this class.
torc::bitstream::Assembler::CompoundSettingMap CompoundSettingMap
Map from one setting to vector of related setings.
std::map< string, string > mDeviceToPackageMap
Map from device to pakcage.
virtual string getParentFamilyName()
Returns parent family name.
boost::shared_ptr< Bitstream > BitstreamSharedPtr
torc::bitstream::BitstreamSharedPtr BitstreamSharedPtr
Imported type name.
void createXdlForLut(const torc::architecture::PrimitiveElement &inElement, const string &inXdlFileNamePartial, DesignSharedPtr inHarnessDesignPtr)
Create Xdl for Lut.
virtual std::vector< std::string > getTilesSupportedForPips()=0
Returns vector of supported tiles.
DesignSharedPtr createEmptyDesignWithSameMetadata(DesignSharedPtr inDesignPtr)
Create an empty design with same metadata. Does not copy configurations.
torc::architecture::xilinx::TileIndex TileIndex
Imported type name.
torc::architecture::Tilewire Tilewire
Imported type name.
std::map< const string, std::vector< uint32_t > > ConfigValuesToBits
Map from config value to vector of config bits. ConfigValuesToBits.
Definition: Assembler.hpp:73
boost::filesystem::path path
Imported type name.
torc::physical::DesignSharedPtr DesignSharedPtr
Imported type name.
torc::packer::PrimitiveStructureSharedPtr PrimitiveStructureSharedPtr
Imported type name.
virtual PrimitiveStructuresSharedPtrMap getPrimitiveNameToStructreMap()=0
Populate primitive name to primitive structure map.