45 float aResult, aResult2;
73 for ( i = 0; i < pCut->
nLeaves; i++ )
77 if ( pNodeChild->
nRefs++ > 0 )
105 for ( i = 0; i < pCut->
nLeaves; i++ )
109 if ( --pNodeChild->
nRefs > 0 )
133 for ( i = 0; i < vMapping->
nSize; i++ )
135 pNode = vMapping->
pArray[i];
144 for ( i = 0; i < pMan->
nOutputs; i++ )
float Fpga_CutDerefSwitch(Fpga_Man_t *pMan, Fpga_Node_t *pNode, Fpga_Cut_t *pCut, int fFanouts)
ABC_NAMESPACE_IMPL_START float Fpga_CutGetSwitchDerefed(Fpga_Man_t *pMan, Fpga_Node_t *pNode, Fpga_Cut_t *pCut)
DECLARATIONS ///.
Fpga_Node_t * ppLeaves[FPGA_MAX_LEAVES+1]
#define ABC_NAMESPACE_IMPL_END
float Fpga_MappingGetSwitching(Fpga_Man_t *pMan, Fpga_NodeVec_t *vMapping)
#define ABC_NAMESPACE_IMPL_START
int Fpga_NodeIsAnd(Fpga_Node_t *p)
int Fpga_NodeIsVar(Fpga_Node_t *p)
STRUCTURE DEFINITIONS ///.
float Fpga_CutRefSwitch(Fpga_Man_t *pMan, Fpga_Node_t *pNode, Fpga_Cut_t *pCut, int fFanouts)
#define Fpga_IsComplement(p)
GLOBAL VARIABLES ///.