fpga.h File Reference

Go to the source code of this file.

Macros
#define	FPGA_MAX_LUTSIZE   32
	INCLUDES ///. More...
#define	Fpga_IsComplement(p)   (((int)((ABC_PTRUINT_T) (p) & 01)))
	GLOBAL VARIABLES ///. More...
#define	Fpga_Regular(p)   ((Fpga_Node_t *)((ABC_PTRUINT_T)(p) & ~01))
#define	Fpga_Not(p)   ((Fpga_Node_t *)((ABC_PTRUINT_T)(p) ^ 01))
#define	Fpga_NotCond(p, c)   ((Fpga_Node_t *)((ABC_PTRUINT_T)(p) ^ (c)))
#define	Fpga_Ref(p)
#define	Fpga_Deref(p)
#define	Fpga_RecursiveDeref(p, c)

Typedefs
typedef struct Fpga_ManStruct_t_	Fpga_Man_t
	STRUCTURE DEFINITIONS ///. More...
typedef struct Fpga_NodeStruct_t_	Fpga_Node_t
typedef struct Fpga_NodeVecStruct_t_	Fpga_NodeVec_t
typedef struct Fpga_CutStruct_t_	Fpga_Cut_t
typedef struct Fpga_LutLibStruct_t_	Fpga_LutLib_t

Functions
Fpga_Man_t *	Fpga_ManCreate (int nInputs, int nOutputs, int fVerbose)
	FUNCTION DEFINITIONS ///. More...
Fpga_Node_t *	Fpga_NodeCreate (Fpga_Man_t *p, Fpga_Node_t *p1, Fpga_Node_t *p2)
void	Fpga_ManFree (Fpga_Man_t *pMan)
void	Fpga_ManPrintTimeStats (Fpga_Man_t *p)
int	Fpga_ManReadInputNum (Fpga_Man_t *p)
	FUNCTION DEFINITIONS ///. More...
int	Fpga_ManReadOutputNum (Fpga_Man_t *p)
Fpga_Node_t **	Fpga_ManReadInputs (Fpga_Man_t *p)
Fpga_Node_t **	Fpga_ManReadOutputs (Fpga_Man_t *p)
Fpga_Node_t *	Fpga_ManReadConst1 (Fpga_Man_t *p)
float *	Fpga_ManReadInputArrivals (Fpga_Man_t *p)
int	Fpga_ManReadVerbose (Fpga_Man_t *p)
int	Fpga_ManReadVarMax (Fpga_Man_t *p)
float *	Fpga_ManReadLutAreas (Fpga_Man_t *p)
Fpga_NodeVec_t *	Fpga_ManReadMapping (Fpga_Man_t *p)
void	Fpga_ManSetOutputNames (Fpga_Man_t *p, char **ppNames)
void	Fpga_ManSetInputArrivals (Fpga_Man_t *p, float *pArrivals)
void	Fpga_ManSetAreaRecovery (Fpga_Man_t *p, int fAreaRecovery)
void	Fpga_ManSetDelayLimit (Fpga_Man_t *p, float DelayLimit)
void	Fpga_ManSetAreaLimit (Fpga_Man_t *p, float AreaLimit)
void	Fpga_ManSetObeyFanoutLimits (Fpga_Man_t *p, int fObeyFanoutLimits)
void	Fpga_ManSetNumIterations (Fpga_Man_t *p, int nNumIterations)
int	Fpga_ManReadFanoutViolations (Fpga_Man_t *p)
void	Fpga_ManSetFanoutViolations (Fpga_Man_t *p, int nVio)
void	Fpga_ManSetChoiceNodeNum (Fpga_Man_t *p, int nChoiceNodes)
void	Fpga_ManSetChoiceNum (Fpga_Man_t *p, int nChoices)
void	Fpga_ManSetVerbose (Fpga_Man_t *p, int fVerbose)
void	Fpga_ManSetSwitching (Fpga_Man_t *p, int fSwitching)
void	Fpga_ManSetLatchPaths (Fpga_Man_t *p, int fLatchPaths)
void	Fpga_ManSetLatchNum (Fpga_Man_t *p, int nLatches)
void	Fpga_ManSetDelayTarget (Fpga_Man_t *p, float DelayTarget)
void	Fpga_ManSetName (Fpga_Man_t *p, char *pFileName)
int	Fpga_LibReadLutMax (Fpga_LutLib_t *pLib)
char *	Fpga_NodeReadData0 (Fpga_Node_t *p)
Fpga_Node_t *	Fpga_NodeReadData1 (Fpga_Node_t *p)
int	Fpga_NodeReadRefs (Fpga_Node_t *p)
int	Fpga_NodeReadNum (Fpga_Node_t *p)
int	Fpga_NodeReadLevel (Fpga_Node_t *p)
Fpga_Cut_t *	Fpga_NodeReadCuts (Fpga_Node_t *p)
Fpga_Cut_t *	Fpga_NodeReadCutBest (Fpga_Node_t *p)
Fpga_Node_t *	Fpga_NodeReadOne (Fpga_Node_t *p)
Fpga_Node_t *	Fpga_NodeReadTwo (Fpga_Node_t *p)
void	Fpga_NodeSetLevel (Fpga_Node_t *p, Fpga_Node_t *pNode)
void	Fpga_NodeSetData0 (Fpga_Node_t *p, char *pData)
void	Fpga_NodeSetData1 (Fpga_Node_t *p, Fpga_Node_t *pNode)
void	Fpga_NodeSetArrival (Fpga_Node_t *p, float Time)
void	Fpga_NodeSetNextE (Fpga_Node_t *p, Fpga_Node_t *pNextE)
void	Fpga_NodeSetRepr (Fpga_Node_t *p, Fpga_Node_t *pRepr)
void	Fpga_NodeSetSwitching (Fpga_Node_t *p, float Switching)
int	Fpga_NodeIsConst (Fpga_Node_t *p)
int	Fpga_NodeIsVar (Fpga_Node_t *p)
int	Fpga_NodeIsAnd (Fpga_Node_t *p)
int	Fpga_NodeComparePhase (Fpga_Node_t *p1, Fpga_Node_t *p2)
int	Fpga_CutReadLeavesNum (Fpga_Cut_t *p)
Fpga_Node_t **	Fpga_CutReadLeaves (Fpga_Cut_t *p)
Fpga_Node_t *	Fpga_NodeAnd (Fpga_Man_t *p, Fpga_Node_t *p1, Fpga_Node_t *p2)
Fpga_Node_t *	Fpga_NodeOr (Fpga_Man_t *p, Fpga_Node_t *p1, Fpga_Node_t *p2)
Fpga_Node_t *	Fpga_NodeExor (Fpga_Man_t *p, Fpga_Node_t *p1, Fpga_Node_t *p2)
Fpga_Node_t *	Fpga_NodeMux (Fpga_Man_t *p, Fpga_Node_t *pNode, Fpga_Node_t *pNodeT, Fpga_Node_t *pNodeE)
void	Fpga_NodeSetChoice (Fpga_Man_t *pMan, Fpga_Node_t *pNodeOld, Fpga_Node_t *pNodeNew)
void	Fpga_ManStats (Fpga_Man_t *p)
int	Fpga_Mapping (Fpga_Man_t *p)
	FUNCTION DEFINITIONS ///. More...
void	Fpga_MappingCreatePiCuts (Fpga_Man_t *p)
void	Fpga_CutsCleanSign (Fpga_Man_t *pMan)
void	Fpga_CutsCleanRoot (Fpga_Man_t *pMan)
void	Fpga_CutCreateFromNode (Fpga_Man_t *p, int iRoot, int *pLeaves, int nLeaves)
void	Fpga_MappingSetUsedCuts (Fpga_Man_t *p)
Fpga_LutLib_t *	Fpga_LutLibDup (Fpga_LutLib_t *p)
int	Fpga_LutLibReadVarMax (Fpga_LutLib_t *p)
	DECLARATIONS ///. More...
float *	Fpga_LutLibReadLutAreas (Fpga_LutLib_t *p)
float *	Fpga_LutLibReadLutDelays (Fpga_LutLib_t *p)
float	Fpga_LutLibReadLutArea (Fpga_LutLib_t *p, int Size)
float	Fpga_LutLibReadLutDelay (Fpga_LutLib_t *p, int Size)
void *	Fpga_TruthsCutBdd (void *dd, Fpga_Cut_t *pCut)
int	Fpga_CutVolume (Fpga_Cut_t *pCut)
int	Fpga_ManCheckConsistency (Fpga_Man_t *p)
void	Fpga_ManCleanData0 (Fpga_Man_t *pMan)
Fpga_NodeVec_t *	Fpga_CollectNodeTfo (Fpga_Man_t *pMan, Fpga_Node_t *pNode)
void	Fpga_SetSimpleLutLib (int nLutSize)

Macro Definition Documentation

#define Fpga_Deref

(

p

)

Definition at line 63 of file fpga.h.

#define Fpga_IsComplement

(

p

)

(((int)((ABC_PTRUINT_T) (p) & 01)))

GLOBAL VARIABLES ///.

MACRO DEFINITIONS ///

Definition at line 57 of file fpga.h.

#define FPGA_MAX_LUTSIZE   32

INCLUDES ///.

CFile****************************************************************

FileName [fpga.h]

PackageName [MVSIS 2.0: Multi-valued logic synthesis system.]

Synopsis [Technology mapping for variable-size-LUT FPGAs.]

Author [MVSIS Group]

Affiliation [UC Berkeley]

Date [Ver. 2.0. Started - August 18, 2004.]

Revision [

Id:

fpga.h,v 1.7 2004/09/30 21:18:09 satrajit Exp

]PARAMETERS ///

Definition at line 37 of file fpga.h.

#define Fpga_Not

(

p

)

((Fpga_Node_t *)((ABC_PTRUINT_T)(p) ^ 01))

Definition at line 59 of file fpga.h.

#define Fpga_NotCond	(		p,
			c
	)		((Fpga_Node_t *)((ABC_PTRUINT_T)(p) ^ (c)))

Definition at line 60 of file fpga.h.

#define Fpga_RecursiveDeref	(		p,
			c
	)

Definition at line 64 of file fpga.h.

#define Fpga_Ref

(

p

)

Definition at line 62 of file fpga.h.

#define Fpga_Regular

(

p

)

((Fpga_Node_t *)((ABC_PTRUINT_T)(p) & ~01))

Definition at line 58 of file fpga.h.

Typedef Documentation

typedef struct Fpga_CutStruct_t_ Fpga_Cut_t

Definition at line 46 of file fpga.h.

typedef struct Fpga_LutLibStruct_t_ Fpga_LutLib_t

Definition at line 47 of file fpga.h.

typedef struct Fpga_ManStruct_t_ Fpga_Man_t

STRUCTURE DEFINITIONS ///.

Definition at line 43 of file fpga.h.

typedef struct Fpga_NodeStruct_t_ Fpga_Node_t

Definition at line 44 of file fpga.h.

typedef struct Fpga_NodeVecStruct_t_ Fpga_NodeVec_t

Definition at line 45 of file fpga.h.

Function Documentation

Fpga_NodeVec_t* Fpga_CollectNodeTfo	(	Fpga_Man_t *	pMan,
		Fpga_Node_t *	pNode
	)

Function*************************************************************

Synopsis [Collects the TFO of the node.]

Description []

SideEffects []

SeeAlso []

Definition at line 675 of file fpgaUtils.c.

{
    Fpga_NodeVec_t * vVisited, * vTfo;
    int i;
    // perform the traversal
    vVisited = Fpga_NodeVecAlloc( 100 );
    vTfo     = Fpga_NodeVecAlloc( 100 );
    for ( i = 0; i < pMan->nOutputs; i++ )
        Fpga_CollectNodeTfo_rec( Fpga_Regular(pMan->pOutputs[i]), pNode, vVisited, vTfo );
    for ( i = 0; i < vVisited->nSize; i++ )
        vVisited->pArray[i]->fMark0 = vVisited->pArray[i]->fMark1 = 0;
    Fpga_NodeVecFree( vVisited );
    return vTfo;
}

void Fpga_CutCreateFromNode	(	Fpga_Man_t *	p,
		int	iRoot,
		int *	pLeaves,
		int	nLeaves
	)

Fpga_Node_t** Fpga_CutReadLeaves

(

Fpga_Cut_t *

p

)

Definition at line 142 of file fpgaCreate.c.

{  return p->ppLeaves; }

int Fpga_CutReadLeavesNum

(

Fpga_Cut_t *

p

)

Function*************************************************************

Synopsis [Reads parameters from the cut.]

Description []

SideEffects []

SeeAlso []

Definition at line 141 of file fpgaCreate.c.

{  return p->nLeaves;  }

void Fpga_CutsCleanRoot

(

Fpga_Man_t *

pMan

)

Function*************************************************************

Synopsis [Clean the signatures.]

Description []

SideEffects []

SeeAlso []

Definition at line 819 of file fpgaCut.c.

{
    Fpga_Node_t * pNode;
    Fpga_Cut_t * pCut;
    int i;
    for ( i = 0; i < pMan->nBins; i++ )
        for ( pNode = pMan->pBins[i]; pNode; pNode = pNode->pNext )
            for ( pCut = pNode->pCuts; pCut; pCut = pCut->pNext )
                pCut->pRoot = NULL;
}

void Fpga_CutsCleanSign

(

Fpga_Man_t *

pMan

)

Function*************************************************************

Synopsis [Clean the signatures.]

Description []

SideEffects []

SeeAlso []

Definition at line 797 of file fpgaCut.c.

{
    Fpga_Node_t * pNode;
    Fpga_Cut_t * pCut;
    int i;
    for ( i = 0; i < pMan->nBins; i++ )
        for ( pNode = pMan->pBins[i]; pNode; pNode = pNode->pNext )
            for ( pCut = pNode->pCuts; pCut; pCut = pCut->pNext )
                pCut->uSign = 0;
}

int Fpga_CutVolume

(

Fpga_Cut_t *

pCut

)

Function*************************************************************

Synopsis [Derives the truth table for one cut.]

Description []

SideEffects []

SeeAlso []

Definition at line 140 of file fpgaTruth.c.

{
    Fpga_NodeVec_t * vVisited;
    int Volume, i;
    assert( pCut->nLeaves > 1 );
    // set the leaf variables
    for ( i = 0; i < pCut->nLeaves; i++ )
        pCut->ppLeaves[i]->pCuts->fMark = 1;
    // recursively compute the function
    vVisited = Fpga_NodeVecAlloc( 10 );
    Fpga_CutVolume_rec( pCut, vVisited ); 
    // clean the marks
    for ( i = 0; i < pCut->nLeaves; i++ )
        pCut->ppLeaves[i]->pCuts->fMark = 0;
    for ( i = 0; i < vVisited->nSize; i++ )
    {
        pCut = (Fpga_Cut_t *)vVisited->pArray[i];
        pCut->fMark = 0;
    }
    Volume = vVisited->nSize;
    printf( "%d ", Volume );
    Fpga_NodeVecFree( vVisited );
    return Volume;
}

int Fpga_LibReadLutMax

(

Fpga_LutLib_t *

pLib

)

Function*************************************************************

Synopsis [Reads the parameters of the LUT library.]

Description []

SideEffects []

SeeAlso []

Definition at line 86 of file fpgaCreate.c.

{ return pLib->LutMax; }

Fpga_LutLib_t* Fpga_LutLibDup

(

Fpga_LutLib_t *

p

)

Function*************************************************************

Synopsis [Duplicates the LUT library.]

Description []

SideEffects []

SeeAlso []

Definition at line 165 of file fpgaLib.c.

{
    Fpga_LutLib_t * pNew;
    pNew = ABC_ALLOC( Fpga_LutLib_t, 1 );
    *pNew = *p;
    pNew->pName = Extra_UtilStrsav( pNew->pName );
    return pNew;
}

float Fpga_LutLibReadLutArea	(	Fpga_LutLib_t *	p,
		int	Size
	)

Definition at line 45 of file fpgaLib.c.

{ assert( Size <= p->LutMax ); return p->pLutAreas[Size];  }

float* Fpga_LutLibReadLutAreas

(

Fpga_LutLib_t *

p

)

Definition at line 44 of file fpgaLib.c.

{ return p->pLutAreas;  }

float Fpga_LutLibReadLutDelay	(	Fpga_LutLib_t *	p,
		int	Size
	)

float* Fpga_LutLibReadLutDelays

(

Fpga_LutLib_t *

p

)

int Fpga_LutLibReadVarMax

(

Fpga_LutLib_t *

p

)

DECLARATIONS ///.

CFile****************************************************************

FileName [fpgaLib.c]

PackageName [MVSIS 1.3: Multi-valued logic synthesis system.]

Synopsis [Technology mapping for variable-size-LUT FPGAs.]

Author [MVSIS Group]

Affiliation [UC Berkeley]

Date [Ver. 2.0. Started - August 18, 2004.]

Revision [

Id:

fpgaLib.c,v 1.4 2005/01/23 06:59:41 alanmi Exp

]FUNCTION DEFINITIONS /// Function*************************************************************

Synopsis [APIs to access LUT library.]

Description []

SideEffects []

SeeAlso []

Definition at line 43 of file fpgaLib.c.

{ return p->LutMax;     }

int Fpga_ManCheckConsistency

(

Fpga_Man_t *

p

)

Function*************************************************************

Synopsis [Verify one useful property.]

Description [This procedure verifies one useful property. After the FRAIG construction with choice nodes is over, each primary node should have fanins that are primary nodes. The primary nodes is the one that does not have pNode->pRepr set to point to another node.]

SideEffects []

SeeAlso []

Definition at line 500 of file fpgaUtils.c.

{
    Fpga_Node_t * pNode;
    Fpga_NodeVec_t * pVec;
    int i;
    pVec = Fpga_MappingDfs( p, 0 );
    for ( i = 0; i < pVec->nSize; i++ )
    {
        pNode = pVec->pArray[i];
        if ( Fpga_NodeIsVar(pNode) )
        {
            if ( pNode->pRepr )
                printf( "Primary input %d is a secondary node.\n", pNode->Num );
        }
        else if ( Fpga_NodeIsConst(pNode) )
        {
            if ( pNode->pRepr )
                printf( "Constant 1 %d is a secondary node.\n", pNode->Num );
        }
        else
        {
            if ( pNode->pRepr )
                printf( "Internal node %d is a secondary node.\n", pNode->Num );
            if ( Fpga_Regular(pNode->p1)->pRepr )
                printf( "Internal node %d has first fanin that is a secondary node.\n", pNode->Num );
            if ( Fpga_Regular(pNode->p2)->pRepr )
                printf( "Internal node %d has second fanin that is a secondary node.\n", pNode->Num );
        }
    }
    Fpga_NodeVecFree( pVec );
    return 1;
}

void Fpga_ManCleanData0

(

Fpga_Man_t *

pMan

)

Function*************************************************************

Synopsis [Computes the limited DFS ordering for one node.]

Description []

SideEffects []

SeeAlso []

Definition at line 657 of file fpgaUtils.c.

{
    int i;
    for ( i = 0; i < pMan->vNodesAll->nSize; i++ )
        pMan->vNodesAll->pArray[i]->pData0 = 0;
}

Fpga_Man_t* Fpga_ManCreate	(	int	nInputs,
		int	nOutputs,
		int	fVerbose
	)

FUNCTION DEFINITIONS ///.

Function*************************************************************

Synopsis [Create the mapping manager.]

Description [The number of inputs and outputs is assumed to be known is advance. It is much simpler to have them fixed upfront. When it comes to representing the object graph in the form of AIG, the resulting manager is similar to the regular AIG manager, except that it does not use reference counting (and therefore does not have garbage collections). It does have table resizing. The data structure is more flexible to represent additional information needed for mapping.]

SideEffects []

SeeAlso []

Definition at line 163 of file fpgaCreate.c.

{
    Fpga_Man_t * p;
    int i;

    // start the manager
    p = ABC_ALLOC( Fpga_Man_t, 1 );
    memset( p, 0, sizeof(Fpga_Man_t) );
    p->pLutLib   = (Fpga_LutLib_t *)Abc_FrameReadLibLut();
    p->nVarsMax  = p->pLutLib->LutMax;
    p->fVerbose  = fVerbose;
    p->fAreaRecovery = 1;
    p->fEpsilon  = (float)0.001;

    Fpga_TableCreate( p );
//if ( p->fVerbose )
//    printf( "Node = %d (%d) bytes. Cut = %d bytes.\n", sizeof(Fpga_Node_t), FPGA_NUM_BYTES(sizeof(Fpga_Node_t)), sizeof(Fpga_Cut_t) ); 
    p->mmNodes  = Extra_MmFixedStart( FPGA_NUM_BYTES(sizeof(Fpga_Node_t)) );
    p->mmCuts   = Extra_MmFixedStart( sizeof(Fpga_Cut_t) );

    assert( p->nVarsMax > 0 );
//    Fpga_MappingSetupTruthTables( p->uTruths );

    // make sure the constant node will get index -1
    p->nNodes = -1;
    // create the constant node
    p->pConst1 = Fpga_NodeCreate( p, NULL, NULL );
    p->vNodesAll = Fpga_NodeVecAlloc( 1000 );
    p->vMapping = Fpga_NodeVecAlloc( 1000 );

    // create the PI nodes
    p->nInputs = nInputs;
    p->pInputs = ABC_ALLOC( Fpga_Node_t *, nInputs );
    for ( i = 0; i < nInputs; i++ )
        p->pInputs[i] = Fpga_NodeCreate( p, NULL, NULL );

    // create the place for the output nodes
    p->nOutputs = nOutputs;
    p->pOutputs = ABC_ALLOC( Fpga_Node_t *, nOutputs );
    memset( p->pOutputs, 0, sizeof(Fpga_Node_t *) * nOutputs );
    return p;
}

void Fpga_ManFree

(

Fpga_Man_t *

p

)

Function*************************************************************

Synopsis [Deallocates the mapping manager.]

Description []

SideEffects []

SeeAlso []

Definition at line 217 of file fpgaCreate.c.

{
//    Fpga_ManStats( p );
//    int i;
//    for ( i = 0; i < p->vNodesAll->nSize; i++ )
//        Fpga_NodeVecFree( p->vNodesAll->pArray[i]->vFanouts );
//    Fpga_NodeVecFree( p->pConst1->vFanouts );
    if ( p->vMapping )
        Fpga_NodeVecFree( p->vMapping );
    if ( p->vAnds )    
        Fpga_NodeVecFree( p->vAnds );
    if ( p->vNodesAll )    
        Fpga_NodeVecFree( p->vNodesAll );
    Extra_MmFixedStop( p->mmNodes );
    Extra_MmFixedStop( p->mmCuts );
    ABC_FREE( p->ppOutputNames );
    ABC_FREE( p->pInputArrivals );
    ABC_FREE( p->pInputs );
    ABC_FREE( p->pOutputs );
    ABC_FREE( p->pBins );
    ABC_FREE( p );
}

void Fpga_ManPrintTimeStats

(

Fpga_Man_t *

p

)

Function*************************************************************

Synopsis [Prints runtime statistics of the mapping manager.]

Description []

SideEffects []

SeeAlso []

Definition at line 252 of file fpgaCreate.c.

{
//    extern char * pNetName;
//    extern int TotalLuts;
//    FILE * pTable;

    
/*
    pTable = fopen( "stats.txt", "a+" );
    fprintf( pTable, "%s ", pNetName );
    fprintf( pTable, "%.0f ", p->fRequiredGlo );
//    fprintf( pTable, "%.0f ", p->fAreaGlo );//+ (float)nOutputInvs );
    fprintf( pTable, "%.0f ", (float)TotalLuts );
    fprintf( pTable, "%4.2f\n", (float)(p->timeTotal-p->timeToMap)/(float)(CLOCKS_PER_SEC) );
    fclose( pTable );
*/

//    printf( "N-canonical = %d. Matchings = %d.  ", p->nCanons, p->nMatches );
//    printf( "Choice nodes = %d. Choices = %d.\n", p->nChoiceNodes, p->nChoices );
    ABC_PRT( "ToMap", p->timeToMap );
    ABC_PRT( "Cuts ", p->timeCuts );
    ABC_PRT( "Match", p->timeMatch );
    ABC_PRT( "Area ", p->timeRecover );
    ABC_PRT( "ToNet", p->timeToNet );
    ABC_PRT( "TOTAL", p->timeTotal );
    if ( p->time1 ) { ABC_PRT( "time1", p->time1 ); }
    if ( p->time2 ) { ABC_PRT( "time2", p->time2 ); }
}

Fpga_Node_t* Fpga_ManReadConst1

(

Fpga_Man_t *

p

)

Definition at line 55 of file fpgaCreate.c.

{ return p->pConst1;    }

int Fpga_ManReadFanoutViolations

(

Fpga_Man_t *

p

)

float* Fpga_ManReadInputArrivals

(

Fpga_Man_t *

p

)

Definition at line 56 of file fpgaCreate.c.

{ return p->pInputArrivals;}

int Fpga_ManReadInputNum

(

Fpga_Man_t *

p

)

FUNCTION DEFINITIONS ///.

Function*************************************************************

Synopsis [Reads parameters of the mapping manager.]

Description []

SideEffects []

SeeAlso []

Definition at line 51 of file fpgaCreate.c.

{ return p->nInputs;    }

Fpga_Node_t** Fpga_ManReadInputs

(

Fpga_Man_t *

p

)

Definition at line 53 of file fpgaCreate.c.

{ return p->pInputs;    }

float* Fpga_ManReadLutAreas

(

Fpga_Man_t *

p

)

Definition at line 59 of file fpgaCreate.c.

{ return p->pLutLib->pLutAreas;  }

Fpga_NodeVec_t* Fpga_ManReadMapping

(

Fpga_Man_t *

p

)

Definition at line 60 of file fpgaCreate.c.

{ return p->vMapping;   }

int Fpga_ManReadOutputNum

(

Fpga_Man_t *

p

)

Definition at line 52 of file fpgaCreate.c.

{ return p->nOutputs;   }

Fpga_Node_t** Fpga_ManReadOutputs

(

Fpga_Man_t *

p

)

Definition at line 54 of file fpgaCreate.c.

{ return p->pOutputs;   }

int Fpga_ManReadVarMax

(

Fpga_Man_t *

p

)

Definition at line 58 of file fpgaCreate.c.

{ return p->pLutLib->LutMax;     }

int Fpga_ManReadVerbose

(

Fpga_Man_t *

p

)

Definition at line 57 of file fpgaCreate.c.

{ return p->fVerbose;   }

void Fpga_ManSetAreaLimit	(	Fpga_Man_t *	p,
		float	AreaLimit
	)

Definition at line 65 of file fpgaCreate.c.

{ p->AreaLimit    = AreaLimit;     }

void Fpga_ManSetAreaRecovery	(	Fpga_Man_t *	p,
		int	fAreaRecovery
	)

Definition at line 63 of file fpgaCreate.c.

{ p->fAreaRecovery = fAreaRecovery;}

void Fpga_ManSetChoiceNodeNum	(	Fpga_Man_t *	p,
		int	nChoiceNodes
	)

Definition at line 66 of file fpgaCreate.c.

{ p->nChoiceNodes = nChoiceNodes;  }  

void Fpga_ManSetChoiceNum	(	Fpga_Man_t *	p,
		int	nChoices
	)

Definition at line 67 of file fpgaCreate.c.

{ p->nChoices = nChoices;          }   

void Fpga_ManSetDelayLimit	(	Fpga_Man_t *	p,
		float	DelayLimit
	)

Definition at line 64 of file fpgaCreate.c.

{ p->DelayLimit   = DelayLimit;    }

void Fpga_ManSetDelayTarget	(	Fpga_Man_t *	p,
		float	DelayTarget
	)

Definition at line 72 of file fpgaCreate.c.

{ p->DelayTarget = DelayTarget;    }   

void Fpga_ManSetFanoutViolations	(	Fpga_Man_t *	p,
		int	nVio
	)

void Fpga_ManSetInputArrivals	(	Fpga_Man_t *	p,
		float *	pArrivals
	)

Definition at line 62 of file fpgaCreate.c.

{ p->pInputArrivals = pArrivals; }

void Fpga_ManSetLatchNum	(	Fpga_Man_t *	p,
		int	nLatches
	)

Definition at line 71 of file fpgaCreate.c.

{ p->nLatches = nLatches;          }   

void Fpga_ManSetLatchPaths	(	Fpga_Man_t *	p,
		int	fLatchPaths
	)

Definition at line 70 of file fpgaCreate.c.

{ p->fLatchPaths = fLatchPaths;    }   

void Fpga_ManSetName	(	Fpga_Man_t *	p,
		char *	pFileName
	)

Definition at line 73 of file fpgaCreate.c.

{ p->pFileName = pFileName;        }   

void Fpga_ManSetNumIterations	(	Fpga_Man_t *	p,
		int	nNumIterations
	)

void Fpga_ManSetObeyFanoutLimits	(	Fpga_Man_t *	p,
		int	fObeyFanoutLimits
	)

void Fpga_ManSetOutputNames	(	Fpga_Man_t *	p,
		char **	ppNames
	)

Definition at line 61 of file fpgaCreate.c.

{ p->ppOutputNames = ppNames; }

void Fpga_ManSetSwitching	(	Fpga_Man_t *	p,
		int	fSwitching
	)

Definition at line 69 of file fpgaCreate.c.

{ p->fSwitching = fSwitching;      }   

void Fpga_ManSetVerbose	(	Fpga_Man_t *	p,
		int	fVerbose
	)

Definition at line 68 of file fpgaCreate.c.

{ p->fVerbose = fVerbose;          }   

void Fpga_ManStats

(

Fpga_Man_t *

p

)

Function*************************************************************

Synopsis [Prints some interesting stats.]

Description []

SideEffects []

SeeAlso []

Definition at line 564 of file fpgaCreate.c.

{
    FILE * pTable;
    pTable = fopen( "stats.txt", "a+" );
    fprintf( pTable, "%s ", p->pFileName );
    fprintf( pTable, "%4d ", p->nInputs - p->nLatches );
    fprintf( pTable, "%4d ", p->nOutputs - p->nLatches );
    fprintf( pTable, "%4d ", p->nLatches );
    fprintf( pTable, "%7d ", p->vAnds->nSize );
    fprintf( pTable, "%7d ", Fpga_CutCountAll(p) );
    fprintf( pTable, "%2d\n", (int)p->fRequiredGlo );
    fclose( pTable );
}

int Fpga_Mapping

(

Fpga_Man_t *

p

)

FUNCTION DEFINITIONS ///.

Function*************************************************************

Synopsis [Performs technology mapping for the given object graph.]

Description [The object graph is stored in the mapping manager. First, all the AND-nodes, which fanout into the POs, are collected in the DFS fashion. Next, three steps are performed: the k-feasible cuts are computed for each node, the truth tables are computed for each cut, and the delay-optimal matches are assigned for each node.]

SideEffects []

SeeAlso []

Definition at line 53 of file fpgaCore.c.

{
    clock_t clk, clkTotal = clock();
 
    // collect the nodes reachable from POs in the DFS order (including the choices)
    p->vAnds = Fpga_MappingDfs( p, 1 );
    Fpga_ManReportChoices( p ); // recomputes levels
    Fpga_MappingSetChoiceLevels( p );

    // compute the cuts of nodes in the DFS order
    clk = clock();
    Fpga_MappingCuts( p );
    p->timeCuts = clock() - clk;

    // match the truth tables to the supergates
    clk = clock();
    if ( !Fpga_MappingMatches( p, 1 ) )
        return 0;
    p->timeMatch = clock() - clk;

    // perform area recovery
    clk = clock();
    if ( !Fpga_MappingPostProcess( p ) )
        return 0;
    p->timeRecover = clock() - clk;
//ABC_PRT( "Total mapping time", clock() - clkTotal );

    s_MappingTime = clock() - clkTotal;
    s_MappingMem = Fpga_CutCountAll(p) * (sizeof(Fpga_Cut_t) - sizeof(int) * (FPGA_MAX_LEAVES - p->nVarsMax));

    // print the AI-graph used for mapping
    //Fpga_ManShow( p, "test" );
//    if ( p->fVerbose )
//        Fpga_MappingPrintOutputArrivals( p );
    if ( p->fVerbose )
    {
        ABC_PRT( "Total time", clock() - clkTotal );
    }
    return 1;
}

void Fpga_MappingCreatePiCuts

(

Fpga_Man_t *

p

)

Function*************************************************************

Synopsis [Performs technology mapping for variable-size-LUTs.]

Description []

SideEffects []

SeeAlso []

Definition at line 181 of file fpgaCut.c.

{
    Fpga_Cut_t * pCut;
    int i;

    // set the elementary cuts for the PI variables
    for ( i = 0; i < p->nInputs; i++ )
    {
        pCut = Fpga_CutAlloc( p );
        pCut->nLeaves = 1;
        pCut->ppLeaves[0] = p->pInputs[i];
        pCut->uSign = (1 << (i%31));
        p->pInputs[i]->pCuts   = pCut;
        p->pInputs[i]->pCutBest = pCut;
        // set the input arrival times
//        p->pInputs[i]->pCut[1]->tArrival = p->pInputArrivals[i];
    }
}

void Fpga_MappingSetUsedCuts

(

Fpga_Man_t *

pMan

)

Function*************************************************************

Synopsis [Sets the used cuts to be the currently selected ones.]

Description []

SideEffects []

SeeAlso []

Definition at line 459 of file fpgaCutUtils.c.

{
    int i;
    for ( i = 0; i < pMan->vNodesAll->nSize; i++ )
        if ( pMan->vNodesAll->pArray[i]->pCutOld )
        {
            pMan->vNodesAll->pArray[i]->pCutBest = pMan->vNodesAll->pArray[i]->pCutOld;
            pMan->vNodesAll->pArray[i]->pCutOld  = NULL;
        }
}

Fpga_Node_t* Fpga_NodeAnd	(	Fpga_Man_t *	p,
		Fpga_Node_t *	p1,
		Fpga_Node_t *	p2
	)

Function*************************************************************

Synopsis [Elementary AND operation on the AIG.]

Description []

SideEffects []

SeeAlso []

Definition at line 470 of file fpgaCreate.c.

{
    Fpga_Node_t * pNode;
    pNode = Fpga_TableLookup( p, p1, p2 );     
    return pNode;
}

int Fpga_NodeComparePhase	(	Fpga_Node_t *	p1,
		Fpga_Node_t *	p2
	)

Definition at line 128 of file fpgaCreate.c.

{ assert( !Fpga_IsComplement(p1) ); assert( !Fpga_IsComplement(p2) ); return p1->fInv ^ p2->fInv; }

Fpga_Node_t* Fpga_NodeCreate	(	Fpga_Man_t *	p,
		Fpga_Node_t *	p1,
		Fpga_Node_t *	p2
	)

Function*************************************************************

Synopsis [Creates a new node.]

Description [This procedure should be called to create the constant node and the PI nodes first.]

SideEffects []

SeeAlso []

Definition at line 293 of file fpgaCreate.c.

{
    Fpga_Node_t * pNode;
    // create the node
    pNode = (Fpga_Node_t *)Extra_MmFixedEntryFetch( p->mmNodes );
    memset( pNode, 0, sizeof(Fpga_Node_t) );
    // set very large required time
    pNode->tRequired = FPGA_FLOAT_LARGE;
    pNode->aEstFanouts = -1;
    pNode->p1  = p1; 
    pNode->p2  = p2;
    // set the number of this node
    pNode->Num = p->nNodes++;
    // place to store the fanouts
//    pNode->vFanouts = Fpga_NodeVecAlloc( 5 );
    // store this node in the internal array
    if ( pNode->Num >= 0 )
        Fpga_NodeVecPush( p->vNodesAll, pNode );
    else
        pNode->fInv = 1;
    // set the level of this node
    if ( p1 ) 
    {
#ifdef FPGA_ALLOCATE_FANOUT
        // create the fanout info
        Fpga_NodeAddFaninFanout( Fpga_Regular(p1), pNode );
        Fpga_NodeAddFaninFanout( Fpga_Regular(p2), pNode );
#endif
        // compute the level
        pNode->Level = 1 + FPGA_MAX(Fpga_Regular(p1)->Level, Fpga_Regular(p2)->Level);
        pNode->fInv  = Fpga_NodeIsSimComplement(p1) & Fpga_NodeIsSimComplement(p2);
    }
    // reference the inputs 
    if ( p1 ) Fpga_NodeRef(p1);
    if ( p2 ) Fpga_NodeRef(p2);
    return pNode;
}

Fpga_Node_t* Fpga_NodeExor	(	Fpga_Man_t *	p,
		Fpga_Node_t *	p1,
		Fpga_Node_t *	p2
	)

Function*************************************************************

Synopsis [Elementary EXOR operation on the AIG.]

Description []

SideEffects []

SeeAlso []

Definition at line 506 of file fpgaCreate.c.

{
    return Fpga_NodeMux( p, p1, Fpga_Not(p2), p2 );
}

int Fpga_NodeIsAnd

(

Fpga_Node_t *

p

)

Definition at line 127 of file fpgaCreate.c.

{  return (Fpga_Regular(p))->p1 != NULL;  }

int Fpga_NodeIsConst

(

Fpga_Node_t *

p

)

Function*************************************************************

Synopsis [Checks the type of the node.]

Description []

SideEffects []

SeeAlso []

Definition at line 125 of file fpgaCreate.c.

{  return (Fpga_Regular(p))->Num == -1;    }

int Fpga_NodeIsVar

(

Fpga_Node_t *

p

)

Definition at line 126 of file fpgaCreate.c.

{  return (Fpga_Regular(p))->p1 == NULL && (Fpga_Regular(p))->Num >= 0; }

Fpga_Node_t* Fpga_NodeMux	(	Fpga_Man_t *	p,
		Fpga_Node_t *	pC,
		Fpga_Node_t *	pT,
		Fpga_Node_t *	pE
	)

Function*************************************************************

Synopsis [Elementary MUX operation on the AIG.]

Description []

SideEffects []

SeeAlso []

Definition at line 522 of file fpgaCreate.c.

{
    Fpga_Node_t * pAnd1, * pAnd2, * pRes;
    pAnd1 = Fpga_TableLookup( p, pC,           pT ); 
    pAnd2 = Fpga_TableLookup( p, Fpga_Not(pC), pE ); 
    pRes  = Fpga_NodeOr( p, pAnd1, pAnd2 );           
    return pRes;
}

Fpga_Node_t* Fpga_NodeOr	(	Fpga_Man_t *	p,
		Fpga_Node_t *	p1,
		Fpga_Node_t *	p2
	)

Function*************************************************************

Synopsis [Elementary OR operation on the AIG.]

Description []

SideEffects []

SeeAlso []

Definition at line 488 of file fpgaCreate.c.

{
    Fpga_Node_t * pNode;
    pNode = Fpga_Not( Fpga_TableLookup( p, Fpga_Not(p1), Fpga_Not(p2) ) );  
    return pNode;
}

Fpga_Cut_t* Fpga_NodeReadCutBest

(

Fpga_Node_t *

p

)

Definition at line 105 of file fpgaCreate.c.

{ return p->pCutBest;  }

Fpga_Cut_t* Fpga_NodeReadCuts

(

Fpga_Node_t *

p

)

Definition at line 104 of file fpgaCreate.c.

{ return p->pCuts;     }

char* Fpga_NodeReadData0

(

Fpga_Node_t *

p

)

Function*************************************************************

Synopsis [Reads parameters of the mapping node.]

Description []

SideEffects []

SeeAlso []

Definition at line 99 of file fpgaCreate.c.

{ return p->pData0;    }

Fpga_Node_t* Fpga_NodeReadData1

(

Fpga_Node_t *

p

)

Definition at line 100 of file fpgaCreate.c.

{ return p->pLevel;    }

int Fpga_NodeReadLevel

(

Fpga_Node_t *

p

)

Definition at line 103 of file fpgaCreate.c.

{ return Fpga_Regular(p)->Level;  }

int Fpga_NodeReadNum

(

Fpga_Node_t *

p

)

Definition at line 102 of file fpgaCreate.c.

{ return p->Num;       }

Fpga_Node_t* Fpga_NodeReadOne

(

Fpga_Node_t *

p

)

Definition at line 106 of file fpgaCreate.c.

{ return p->p1;        }

int Fpga_NodeReadRefs

(

Fpga_Node_t *

p

)

Definition at line 101 of file fpgaCreate.c.

{ return p->nRefs;     }

Fpga_Node_t* Fpga_NodeReadTwo

(

Fpga_Node_t *

p

)

Definition at line 107 of file fpgaCreate.c.

{ return p->p2;        }

void Fpga_NodeSetArrival	(	Fpga_Node_t *	p,
		float	Time
	)

void Fpga_NodeSetChoice	(	Fpga_Man_t *	pMan,
		Fpga_Node_t *	pNodeOld,
		Fpga_Node_t *	pNodeNew
	)

Function*************************************************************

Synopsis [Sets the node to be equivalent to the given one.]

Description [This procedure is a work-around for the equivalence check. Does not verify the equivalence. Use at the user's risk.]

SideEffects []

SeeAlso []

Definition at line 544 of file fpgaCreate.c.

{
    pNodeNew->pNextE = pNodeOld->pNextE;
    pNodeOld->pNextE = pNodeNew;
    pNodeNew->pRepr  = pNodeOld;
}

void Fpga_NodeSetData0	(	Fpga_Node_t *	p,
		char *	pData
	)

Definition at line 108 of file fpgaCreate.c.

{ p->pData0 = pData;  }

void Fpga_NodeSetData1	(	Fpga_Node_t *	p,
		Fpga_Node_t *	pNode
	)

Definition at line 109 of file fpgaCreate.c.

{ p->pLevel = pNode;  }

void Fpga_NodeSetLevel	(	Fpga_Node_t *	p,
		Fpga_Node_t *	pNode
	)

void Fpga_NodeSetNextE	(	Fpga_Node_t *	p,
		Fpga_Node_t *	pNextE
	)

Definition at line 110 of file fpgaCreate.c.

{ p->pNextE = pNextE; }

void Fpga_NodeSetRepr	(	Fpga_Node_t *	p,
		Fpga_Node_t *	pRepr
	)

Definition at line 111 of file fpgaCreate.c.

{ p->pRepr = pRepr;   }

void Fpga_NodeSetSwitching	(	Fpga_Node_t *	p,
		float	Switching
	)

Definition at line 112 of file fpgaCreate.c.

{ p->Switching = Switching;   }

void Fpga_SetSimpleLutLib

(

int

nLutSize

)

Function*************************************************************

Synopsis [Sets simple LUT library.]

Description []

SideEffects []

SeeAlso []

Definition at line 252 of file fpga.c.

{
    Fpga_LutLib_t s_LutLib10= { "lutlib",10, 0, {0,1,1,1,1,1,1,1,1,1,1}, {{0},{1},{1},{1},{1},{1},{1},{1},{1},{1},{1}} };
    Fpga_LutLib_t s_LutLib9 = { "lutlib", 9, 0, {0,1,1,1,1,1,1,1,1,1}, {{0},{1},{1},{1},{1},{1},{1},{1},{1},{1}} };
    Fpga_LutLib_t s_LutLib8 = { "lutlib", 8, 0, {0,1,1,1,1,1,1,1,1}, {{0},{1},{1},{1},{1},{1},{1},{1},{1}} };
    Fpga_LutLib_t s_LutLib7 = { "lutlib", 7, 0, {0,1,1,1,1,1,1,1}, {{0},{1},{1},{1},{1},{1},{1},{1}} };
    Fpga_LutLib_t s_LutLib6 = { "lutlib", 6, 0, {0,1,1,1,1,1,1}, {{0},{1},{1},{1},{1},{1},{1}} };
    Fpga_LutLib_t s_LutLib5 = { "lutlib", 5, 0, {0,1,1,1,1,1}, {{0},{1},{1},{1},{1},{1}} };
    Fpga_LutLib_t s_LutLib4 = { "lutlib", 4, 0, {0,1,1,1,1}, {{0},{1},{1},{1},{1}} };
    Fpga_LutLib_t s_LutLib3 = { "lutlib", 3, 0, {0,1,1,1}, {{0},{1},{1},{1}} };
    Fpga_LutLib_t * pLutLib;
    assert( nLutSize >= 3 && nLutSize <= 10 );
    switch ( nLutSize )
    {
        case 3:  pLutLib = &s_LutLib3; break;
        case 4:  pLutLib = &s_LutLib4; break;
        case 5:  pLutLib = &s_LutLib5; break;
        case 6:  pLutLib = &s_LutLib6; break;
        case 7:  pLutLib = &s_LutLib7; break;
        case 8:  pLutLib = &s_LutLib8; break;
        case 9:  pLutLib = &s_LutLib9; break;
        case 10: pLutLib = &s_LutLib10; break;
        default: pLutLib = NULL; break;
    }
    if ( pLutLib == NULL )
        return;
    Fpga_LutLibFree( (Fpga_LutLib_t *)Abc_FrameReadLibLut() );
    Abc_FrameSetLibLut( Fpga_LutLibDup(pLutLib) );
}

void* Fpga_TruthsCutBdd	(	void *	dd,
		Fpga_Cut_t *	pCut
	)

Function*************************************************************

Synopsis [Derives the truth table for one cut.]

Description []

SideEffects []

SeeAlso []

Definition at line 79 of file fpgaTruth.c.

{
    Fpga_NodeVec_t * vVisited;
    DdNode * bFunc;
    int i;
    assert( pCut->nLeaves > 1 );
    // set the leaf variables
    for ( i = 0; i < pCut->nLeaves; i++ )
        pCut->ppLeaves[i]->pCuts->uSign = (unsigned)(ABC_PTRUINT_T)Cudd_bddIthVar( (DdManager *)dd, i );
    // recursively compute the function
    vVisited = Fpga_NodeVecAlloc( 10 );
    bFunc = Fpga_TruthsCutBdd_rec( (DdManager *)dd, pCut, vVisited );   Cudd_Ref( bFunc );
    // clean the intermediate BDDs
    for ( i = 0; i < pCut->nLeaves; i++ )
        pCut->ppLeaves[i]->pCuts->uSign = 0;
    for ( i = 0; i < vVisited->nSize; i++ )
    {
        pCut = (Fpga_Cut_t *)vVisited->pArray[i];
        Cudd_RecursiveDeref( (DdManager *)dd, (DdNode*)(ABC_PTRUINT_T)pCut->uSign );
        pCut->uSign = 0;
    }
//    printf( "%d ", vVisited->nSize );
    Fpga_NodeVecFree( vVisited );
    Cudd_Deref( bFunc );
    return bFunc;
}