TechmapWorker Struct Reference

Data Structures
struct	TechmapWireData

Public Types
typedef std::map< std::string, std::vector< TechmapWireData > >	TechmapWires

Public Member Functions
	TechmapWorker ()
std::string	constmap_tpl_name (SigMap &sigmap, RTLIL::Module *tpl, RTLIL::Cell *cell, bool verbose)
TechmapWires	techmap_find_special_wires (RTLIL::Module *module)
void	techmap_module_worker (RTLIL::Design *design, RTLIL::Module *module, RTLIL::Cell *cell, RTLIL::Module *tpl)
bool	techmap_module (RTLIL::Design *design, RTLIL::Module *module, RTLIL::Design *map, std::set< RTLIL::Cell * > &handled_cells, const std::map< RTLIL::IdString, std::set< RTLIL::IdString, RTLIL::sort_by_id_str >> &celltypeMap, bool in_recursion)

Data Fields
std::map< RTLIL::IdString, void(*)(RTLIL::Module *, RTLIL::Cell *)>	simplemap_mappers
std::map< std::pair < RTLIL::IdString, std::map < RTLIL::IdString, RTLIL::Const > >, RTLIL::Module * >	techmap_cache
std::map< RTLIL::Module *, bool >	techmap_do_cache
std::set< RTLIL::Module *, RTLIL::IdString::compare_ptr_by_name < RTLIL::Module > >	module_queue
bool	extern_mode
bool	assert_mode
bool	flatten_mode
bool	recursive_mode
bool	autoproc_mode

Detailed Description

Definition at line 65 of file techmap.cc.

Member Typedef Documentation

typedef std::map<std::string, std::vector<TechmapWireData> > TechmapWorker::TechmapWires

Definition at line 77 of file techmap.cc.

Constructor & Destructor Documentation

TechmapWorker::TechmapWorker ( )

inline

Definition at line 85 of file techmap.cc.

    {
        extern_mode = false;
        assert_mode = false;
        flatten_mode = false;
        recursive_mode = false;
        autoproc_mode = false;
    }

Member Function Documentation

std::string TechmapWorker::constmap_tpl_name ( SigMap &  sigmap, RTLIL::Module *  tpl, RTLIL::Cell *  cell, bool  verbose  )

inline

Definition at line 94 of file techmap.cc.

    {
        std::string constmap_info;
        std::map<RTLIL::SigBit, std::pair<RTLIL::IdString, int>> connbits_map;

        for (auto conn : cell->connections())
            for (int i = 0; i < GetSize(conn.second); i++) {
                RTLIL::SigBit bit = sigmap(conn.second[i]);
                if (bit.wire == nullptr) {
                    if (verbose)
                        log("  Constant input on bit %d of port %s: %s\n", i, log_id(conn.first), log_signal(bit));
                    constmap_info += stringf("|%s %d %d", log_id(conn.first), i, bit.data);
                } else if (connbits_map.count(bit)) {
                    if (verbose)
                        log("  Bit %d of port %s and bit %d of port %s are connected.\n", i, log_id(conn.first),
                                connbits_map.at(bit).second, log_id(connbits_map.at(bit).first));
                    constmap_info += stringf("|%s %d %s %d", log_id(conn.first), i,
                            log_id(connbits_map.at(bit).first), connbits_map.at(bit).second);
                } else {
                    connbits_map[bit] = std::pair<RTLIL::IdString, int>(conn.first, i);
                    constmap_info += stringf("|%s %d", log_id(conn.first), i);
                }
            }

        return stringf("$paramod$constmap:%s%s", sha1(constmap_info).c_str(), tpl->name.c_str());
    }

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TechmapWires TechmapWorker::techmap_find_special_wires ( RTLIL::Module *  module )

inline

Definition at line 121 of file techmap.cc.

    {
        TechmapWires result;

        if (module == NULL)
            return result;

        for (auto &it : module->wires_) {
            const char *p = it.first.c_str();
            if (*p == '$')
                continue;

            const char *q = strrchr(p+1, '.');
            p = q ? q : p+1;

            if (!strncmp(p, "_TECHMAP_", 9)) {
                TechmapWireData record;
                record.wire = it.second;
                record.value = it.second;
                result[p].push_back(record);
                it.second->attributes["\\keep"] = RTLIL::Const(1);
                it.second->attributes["\\_techmap_special_"] = RTLIL::Const(1);
            }
        }

        if (!result.empty()) {
            SigMap sigmap(module);
            for (auto &it1 : result)
            for (auto &it2 : it1.second)
                sigmap.apply(it2.value);
        }

        return result;
    }

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bool TechmapWorker::techmap_module ( RTLIL::Design *  design, RTLIL::Module *  module, RTLIL::Design *  map, std::set< RTLIL::Cell * > &  handled_cells, const std::map< RTLIL::IdString, std::set< RTLIL::IdString, RTLIL::sort_by_id_str >> &  celltypeMap, bool  in_recursion  )

inline

Definition at line 271 of file techmap.cc.

    {
        std::string mapmsg_prefix = in_recursion ? "Recursively mapping" : "Mapping";

        if (!design->selected(module))
            return false;

        bool log_continue = false;
        bool did_something = false;

        SigMap sigmap(module);

        TopoSort<RTLIL::Cell*, RTLIL::IdString::compare_ptr_by_name<RTLIL::Cell>> cells;
        std::map<RTLIL::Cell*, std::set<RTLIL::SigBit>> cell_to_inbit;
        std::map<RTLIL::SigBit, std::set<RTLIL::Cell*>> outbit_to_cell;

        for (auto cell : module->cells())
        {
            if (!design->selected(module, cell) || handled_cells.count(cell) > 0)
                continue;

            std::string cell_type = cell->type.str();
            if (in_recursion && cell_type.substr(0, 2) == "\\$")
                cell_type = cell_type.substr(1);

            if (celltypeMap.count(cell_type) == 0) {
                if (assert_mode && cell_type.back() != '_')
                    log_error("(ASSERT MODE) No matching template cell for type %s found.\n", log_id(cell_type));
                continue;
            }

            for (auto &conn : cell->connections())
            {
                RTLIL::SigSpec sig = sigmap(conn.second);
                sig.remove_const();

                if (GetSize(sig) == 0)
                    continue;

                for (auto &tpl_name : celltypeMap.at(cell_type)) {
                    RTLIL::Module *tpl = map->modules_[tpl_name];
                    RTLIL::Wire *port = tpl->wire(conn.first);
                    if (port && port->port_input)
                        cell_to_inbit[cell].insert(sig.begin(), sig.end());
                    if (port && port->port_output)
                        for (auto &bit : sig)
                            outbit_to_cell[bit].insert(cell);
                }
            }

            cells.node(cell);
        }

        for (auto &it_right : cell_to_inbit)
        for (auto &it_sigbit : it_right.second)
        for (auto &it_left : outbit_to_cell[it_sigbit])
            cells.edge(it_left, it_right.first);

        cells.sort();

        for (auto cell : cells.sorted)
        {
            log_assert(handled_cells.count(cell) == 0);
            log_assert(cell == module->cell(cell->name));
            bool mapped_cell = false;

            std::string cell_type = cell->type.str();
            if (in_recursion && cell_type.substr(0, 2) == "\\$")
                cell_type = cell_type.substr(1);

            for (auto &tpl_name : celltypeMap.at(cell_type))
            {
                RTLIL::IdString derived_name = tpl_name;
                RTLIL::Module *tpl = map->modules_[tpl_name];
                std::map<RTLIL::IdString, RTLIL::Const> parameters = cell->parameters;

                if (tpl->get_bool_attribute("\\blackbox"))
                    continue;

                if (!flatten_mode)
                {
                    std::string extmapper_name;

                    if (tpl->get_bool_attribute("\\techmap_simplemap"))
                        extmapper_name = "simplemap";

                    if (tpl->get_bool_attribute("\\techmap_maccmap"))
                        extmapper_name = "maccmap";

                    if (tpl->attributes.count("\\techmap_wrap"))
                        extmapper_name = "wrap";

                    if (!extmapper_name.empty())
                    {
                        cell->type = cell_type;

                        if ((extern_mode && !in_recursion) || extmapper_name == "wrap")
                        {
                            std::string m_name = stringf("$extern:%s:%s", extmapper_name.c_str(), log_id(cell->type));

                            for (auto &c : cell->parameters)
                                m_name += stringf(":%s=%s", log_id(c.first), log_signal(c.second));

                            if (extmapper_name == "wrap")
                                m_name += ":" + sha1(tpl->attributes.at("\\techmap_wrap").decode_string());

                            RTLIL::Design *extmapper_design = extern_mode && !in_recursion ? design : tpl->design;
                            RTLIL::Module *extmapper_module = extmapper_design->module(m_name);

                            if (extmapper_module == nullptr)
                            {
                                extmapper_module = extmapper_design->addModule(m_name);
                                RTLIL::Cell *extmapper_cell = extmapper_module->addCell(cell->type, cell);

                                int port_counter = 1;
                                for (auto &c : extmapper_cell->connections_) {
                                    RTLIL::Wire *w = extmapper_module->addWire(c.first, GetSize(c.second));
                                    if (w->name == "\\Y" || w->name == "\\Q")
                                        w->port_output = true;
                                    else
                                        w->port_input = true;
                                    w->port_id = port_counter++;
                                    c.second = w;
                                }

                                extmapper_module->fixup_ports();
                                extmapper_module->check();

                                if (extmapper_name == "simplemap") {
                                    log("Creating %s with simplemap.\n", log_id(extmapper_module));
                                    if (simplemap_mappers.count(extmapper_cell->type) == 0)
                                        log_error("No simplemap mapper for cell type %s found!\n", log_id(extmapper_cell->type));
                                    simplemap_mappers.at(extmapper_cell->type)(extmapper_module, extmapper_cell);
                                    extmapper_module->remove(extmapper_cell);
                                }

                                if (extmapper_name == "maccmap") {
                                    log("Creating %s with maccmap.\n", log_id(extmapper_module));
                                    if (extmapper_cell->type != "$macc")
                                        log_error("The maccmap mapper can only map $macc (not %s) cells!\n", log_id(extmapper_cell->type));
                                    maccmap(extmapper_module, extmapper_cell);
                                    extmapper_module->remove(extmapper_cell);
                                }

                                if (extmapper_name == "wrap") {
                                    std::string cmd_string = tpl->attributes.at("\\techmap_wrap").decode_string();
                                    log("Running \"%s\" on wrapper %s.\n", cmd_string.c_str(), log_id(extmapper_module));
                                    Pass::call_on_module(extmapper_design, extmapper_module, cmd_string);
                                    log_continue = true;
                                }
                            }

                            cell->type = extmapper_module->name;
                            cell->parameters.clear();

                            if (!extern_mode || in_recursion) {
                                tpl = extmapper_module;
                                goto use_wrapper_tpl;
                            }

                            log("%s %s.%s (%s) to %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), log_id(extmapper_module));
                        }
                        else
                        {
                            log("%s %s.%s (%s) with %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), extmapper_name.c_str());

                            if (extmapper_name == "simplemap") {
                                if (simplemap_mappers.count(cell->type) == 0)
                                    log_error("No simplemap mapper for cell type %s found!\n", RTLIL::id2cstr(cell->type));
                                simplemap_mappers.at(cell->type)(module, cell);
                            }

                            if (extmapper_name == "maccmap") {
                                if (cell->type != "$macc")
                                    log_error("The maccmap mapper can only map $macc (not %s) cells!\n", log_id(cell->type));
                                maccmap(module, cell);
                            }

                            module->remove(cell);
                            cell = NULL;
                        }

                        did_something = true;
                        mapped_cell = true;
                        break;
                    }

                    for (auto conn : cell->connections()) {
                        if (conn.first.substr(0, 1) == "$")
                            continue;
                        if (tpl->wires_.count(conn.first) > 0 && tpl->wires_.at(conn.first)->port_id > 0)
                            continue;
                        if (!conn.second.is_fully_const() || parameters.count(conn.first) > 0 || tpl->avail_parameters.count(conn.first) == 0)
                            goto next_tpl;
                        parameters[conn.first] = conn.second.as_const();
                    }

                    if (0) {
            next_tpl:
                        continue;
                    }

                    if (tpl->avail_parameters.count("\\_TECHMAP_CELLTYPE_") != 0)
                        parameters["\\_TECHMAP_CELLTYPE_"] = RTLIL::unescape_id(cell->type);

                    for (auto conn : cell->connections()) {
                        if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTMSK_%s_", RTLIL::id2cstr(conn.first))) != 0) {
                            std::vector<RTLIL::SigBit> v = sigmap(conn.second).to_sigbit_vector();
                            for (auto &bit : v)
                                bit = RTLIL::SigBit(bit.wire == NULL ? RTLIL::State::S1 : RTLIL::State::S0);
                            parameters[stringf("\\_TECHMAP_CONSTMSK_%s_", RTLIL::id2cstr(conn.first))] = RTLIL::SigSpec(v).as_const();
                        }
                        if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTVAL_%s_", RTLIL::id2cstr(conn.first))) != 0) {
                            std::vector<RTLIL::SigBit> v = sigmap(conn.second).to_sigbit_vector();
                            for (auto &bit : v)
                                if (bit.wire != NULL)
                                    bit = RTLIL::SigBit(RTLIL::State::Sx);
                            parameters[stringf("\\_TECHMAP_CONSTVAL_%s_", RTLIL::id2cstr(conn.first))] = RTLIL::SigSpec(v).as_const();
                        }
                    }

                    int unique_bit_id_counter = 0;
                    std::map<RTLIL::SigBit, int> unique_bit_id;
                    unique_bit_id[RTLIL::State::S0] = unique_bit_id_counter++;
                    unique_bit_id[RTLIL::State::S1] = unique_bit_id_counter++;
                    unique_bit_id[RTLIL::State::Sx] = unique_bit_id_counter++;
                    unique_bit_id[RTLIL::State::Sz] = unique_bit_id_counter++;

                    for (auto conn : cell->connections())
                        if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn.first))) != 0) {
                            for (auto &bit : sigmap(conn.second).to_sigbit_vector())
                                if (unique_bit_id.count(bit) == 0)
                                    unique_bit_id[bit] = unique_bit_id_counter++;
                        }

                    int bits = 0;
                    for (int i = 0; i < 32; i++)
                        if (((unique_bit_id_counter-1) & (1 << i)) != 0)
                            bits = i;
                    if (tpl->avail_parameters.count("\\_TECHMAP_BITS_CONNMAP_"))
                        parameters["\\_TECHMAP_BITS_CONNMAP_"] = bits;

                    for (auto conn : cell->connections())
                        if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn.first))) != 0) {
                            RTLIL::Const value;
                            for (auto &bit : sigmap(conn.second).to_sigbit_vector()) {
                                RTLIL::Const chunk(unique_bit_id.at(bit), bits);
                                value.bits.insert(value.bits.end(), chunk.bits.begin(), chunk.bits.end());
                            }
                            parameters[stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn.first))] = value;
                        }
                }

                if (0) {
            use_wrapper_tpl:;
                    // do not register techmap_wrap modules with techmap_cache
                } else {
                    std::pair<RTLIL::IdString, std::map<RTLIL::IdString, RTLIL::Const>> key(tpl_name, parameters);
                    if (techmap_cache.count(key) > 0) {
                        tpl = techmap_cache[key];
                    } else {
                        if (cell->parameters.size() != 0) {
                            derived_name = tpl->derive(map, parameters);
                            tpl = map->module(derived_name);
                            log_continue = true;
                        }
                        techmap_cache[key] = tpl;
                    }
                }

                if (flatten_mode) {
                    techmap_do_cache[tpl] = true;
                } else {
                    RTLIL::Module *constmapped_tpl = map->module(constmap_tpl_name(sigmap, tpl, cell, false));
                    if (constmapped_tpl != nullptr)
                        tpl = constmapped_tpl;
                }

                if (techmap_do_cache.count(tpl) == 0)
                {
                    bool keep_running = true;
                    techmap_do_cache[tpl] = true;

                    std::set<std::string> techmap_wire_names;

                    while (keep_running)
                    {
                        TechmapWires twd = techmap_find_special_wires(tpl);
                        keep_running = false;

                        for (auto &it : twd)
                            techmap_wire_names.insert(it.first);

                        for (auto &it : twd["_TECHMAP_FAIL_"]) {
                            RTLIL::SigSpec value = it.value;
                            if (value.is_fully_const() && value.as_bool()) {
                                log("Not using module `%s' from techmap as it contains a %s marker wire with non-zero value %s.\n",
                                        derived_name.c_str(), RTLIL::id2cstr(it.wire->name), log_signal(value));
                                techmap_do_cache[tpl] = false;
                            }
                        }

                        if (!techmap_do_cache[tpl])
                            break;

                        for (auto &it : twd)
                        {
                            if (it.first.substr(0, 12) != "_TECHMAP_DO_" || it.second.empty())
                                continue;

                            auto &data = it.second.front();

                            if (!data.value.is_fully_const())
                                log_error("Techmap yielded config wire %s with non-const value %s.\n", RTLIL::id2cstr(data.wire->name), log_signal(data.value));

                            techmap_wire_names.erase(it.first);

                            const char *p = data.wire->name.c_str();
                            const char *q = strrchr(p+1, '.');
                            q = q ? q : p+1;

                            std::string cmd_string = data.value.as_const().decode_string();

                        restart_eval_cmd_string:
                            if (cmd_string.rfind("CONSTMAP; ", 0) == 0)
                            {
                                cmd_string = cmd_string.substr(strlen("CONSTMAP; "));

                                log("Analyzing pattern of constant bits for this cell:\n");
                                RTLIL::IdString new_tpl_name = constmap_tpl_name(sigmap, tpl, cell, true);
                                log("Creating constmapped module `%s'.\n", log_id(new_tpl_name));
                                log_assert(map->module(new_tpl_name) == nullptr);

                                RTLIL::Module *new_tpl = map->addModule(new_tpl_name);
                                tpl->cloneInto(new_tpl);

                                techmap_do_cache.erase(tpl);
                                techmap_do_cache[new_tpl] = true;
                                tpl = new_tpl;

                                std::map<RTLIL::SigBit, RTLIL::SigBit> port_new2old_map;
                                std::map<RTLIL::SigBit, RTLIL::SigBit> port_connmap;
                                std::map<RTLIL::SigBit, RTLIL::SigBit> cellbits_to_tplbits;

                                for (auto wire : tpl->wires().to_vector())
                                {
                                    if (!wire->port_input || wire->port_output)
                                        continue;

                                    RTLIL::IdString port_name = wire->name;
                                    tpl->rename(wire, NEW_ID);

                                    RTLIL::Wire *new_wire = tpl->addWire(port_name, wire);
                                    wire->port_input = false;
                                    wire->port_id = 0;

                                    for (int i = 0; i < wire->width; i++) {
                                        port_new2old_map[RTLIL::SigBit(new_wire, i)] = RTLIL::SigBit(wire, i);
                                        port_connmap[RTLIL::SigBit(wire, i)] = RTLIL::SigBit(new_wire, i);
                                    }
                                }

                                for (auto conn : cell->connections())
                                    for (int i = 0; i < GetSize(conn.second); i++)
                                    {
                                        RTLIL::SigBit bit = sigmap(conn.second[i]);
                                        RTLIL::SigBit tplbit(tpl->wire(conn.first), i);

                                        if (bit.wire == nullptr)
                                        {
                                            RTLIL::SigBit oldbit = port_new2old_map.at(tplbit);
                                            port_connmap.at(oldbit) = bit;
                                        }
                                        else if (cellbits_to_tplbits.count(bit))
                                        {
                                            RTLIL::SigBit oldbit = port_new2old_map.at(tplbit);
                                            port_connmap.at(oldbit) = cellbits_to_tplbits[bit];
                                        }
                                        else
                                            cellbits_to_tplbits[bit] = tplbit;
                                    }

                                RTLIL::SigSig port_conn;
                                for (auto &it : port_connmap) {
                                    port_conn.first.append_bit(it.first);
                                    port_conn.second.append_bit(it.second);
                                }
                                tpl->connect(port_conn);

                                tpl->check();
                                goto restart_eval_cmd_string;
                            }

                            if (cmd_string.rfind("RECURSION; ", 0) == 0)
                            {
                                cmd_string = cmd_string.substr(strlen("RECURSION; "));
                                while (techmap_module(map, tpl, map, handled_cells, celltypeMap, true)) { }
                                goto restart_eval_cmd_string;
                            }

                            Pass::call_on_module(map, tpl, cmd_string);

                            log_assert(!strncmp(q, "_TECHMAP_DO_", 12));
                            std::string new_name = data.wire->name.substr(0, q-p) + "_TECHMAP_DONE_" + data.wire->name.substr(q-p+12);
                            while (tpl->wires_.count(new_name))
                                new_name += "_";
                            tpl->rename(data.wire->name, new_name);

                            keep_running = true;
                            break;
                        }
                    }

                    TechmapWires twd = techmap_find_special_wires(tpl);
                    for (auto &it : twd) {
                        if (it.first != "_TECHMAP_FAIL_" && it.first.substr(0, 12) != "_TECHMAP_DO_" && it.first.substr(0, 14) != "_TECHMAP_DONE_")
                            log_error("Techmap yielded unknown config wire %s.\n", it.first.c_str());
                        if (techmap_do_cache[tpl])
                            for (auto &it2 : it.second)
                                if (!it2.value.is_fully_const())
                                    log_error("Techmap yielded config wire %s with non-const value %s.\n", RTLIL::id2cstr(it2.wire->name), log_signal(it2.value));
                        techmap_wire_names.erase(it.first);
                    }

                    for (auto &it : techmap_wire_names)
                        log_error("Techmap special wire %s disappeared. This is considered a fatal error.\n", RTLIL::id2cstr(it));

                    if (recursive_mode) {
                        if (log_continue) {
                            log_header("Continuing TECHMAP pass.\n");
                            log_continue = false;
                        }
                        while (techmap_module(map, tpl, map, handled_cells, celltypeMap, true)) { }
                    }
                }

                if (techmap_do_cache.at(tpl) == false)
                    continue;

                if (log_continue) {
                    log_header("Continuing TECHMAP pass.\n");
                    log_continue = false;
                }

                if (extern_mode && !in_recursion)
                {
                    std::string m_name = stringf("$extern:%s", log_id(tpl));

                    if (!design->module(m_name))
                    {
                        RTLIL::Module *m = design->addModule(m_name);
                        tpl->cloneInto(m);

                        for (auto cell : m->cells()) {
                            if (cell->type.substr(0, 2) == "\\$")
                                cell->type = cell->type.substr(1);
                        }

                        module_queue.insert(m);
                    }

                    log("%s %s.%s to imported %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(m_name));
                    cell->type = m_name;
                    cell->parameters.clear();
                }
                else
                {
                    log("%s %s.%s using %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(tpl));
                    techmap_module_worker(design, module, cell, tpl);
                    cell = NULL;
                }
                did_something = true;
                mapped_cell = true;
                break;
            }

            if (assert_mode && !mapped_cell)
                log_error("(ASSERT MODE) Failed to map cell %s.%s (%s).\n", log_id(module), log_id(cell), log_id(cell->type));

            handled_cells.insert(cell);
        }

        if (log_continue) {
            log_header("Continuing TECHMAP pass.\n");
            log_continue = false;
        }

        return did_something;
    }

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void TechmapWorker::techmap_module_worker ( RTLIL::Design *  design, RTLIL::Module *  module, RTLIL::Cell *  cell, RTLIL::Module *  tpl  )

inline

Definition at line 156 of file techmap.cc.

    {
        if (tpl->memories.size() != 0)
            log_error("Technology map yielded memories -> this is not supported.\n");

        if (tpl->processes.size() != 0) {
            log("Technology map yielded processes:\n");
            for (auto &it : tpl->processes)
                log("  %s",RTLIL::id2cstr(it.first));
            if (autoproc_mode) {
                Pass::call_on_module(tpl->design, tpl, "proc");
                log_assert(GetSize(tpl->processes) == 0);
            } else
                log_error("Technology map yielded processes -> this is not supported (use -autoproc to run 'proc' automatically).\n");
        }

        std::string orig_cell_name;
        if (!flatten_mode)
            for (auto &it : tpl->cells_)
                if (it.first == "\\_TECHMAP_REPLACE_") {
                    orig_cell_name = cell->name.str();
                    module->rename(cell, stringf("$techmap%d", autoidx++) + cell->name.str());
                    break;
                }

        std::map<RTLIL::IdString, RTLIL::IdString> positional_ports;

        for (auto &it : tpl->wires_) {
            if (it.second->port_id > 0)
                positional_ports[stringf("$%d", it.second->port_id)] = it.first;
            std::string w_name = it.second->name.str();
            apply_prefix(cell->name.str(), w_name);
            RTLIL::Wire *w = module->addWire(w_name, it.second);
            w->port_input = false;
            w->port_output = false;
            w->port_id = 0;
            if (it.second->get_bool_attribute("\\_techmap_special_"))
                w->attributes.clear();
            design->select(module, w);
        }

        SigMap port_signal_map;

        for (auto &it : cell->connections()) {
            RTLIL::IdString portname = it.first;
            if (positional_ports.count(portname) > 0)
                portname = positional_ports.at(portname);
            if (tpl->wires_.count(portname) == 0 || tpl->wires_.at(portname)->port_id == 0) {
                if (portname.substr(0, 1) == "$")
                    log_error("Can't map port `%s' of cell `%s' to template `%s'!\n", portname.c_str(), cell->name.c_str(), tpl->name.c_str());
                continue;
            }
            RTLIL::Wire *w = tpl->wires_.at(portname);
            RTLIL::SigSig c;
            if (w->port_output) {
                c.first = it.second;
                c.second = RTLIL::SigSpec(w);
                apply_prefix(cell->name.str(), c.second, module);
            } else {
                c.first = RTLIL::SigSpec(w);
                c.second = it.second;
                apply_prefix(cell->name.str(), c.first, module);
            }
            if (c.second.size() > c.first.size())
                c.second.remove(c.first.size(), c.second.size() - c.first.size());
            if (c.second.size() < c.first.size())
                c.second.append(RTLIL::SigSpec(RTLIL::State::S0, c.first.size() - c.second.size()));
            log_assert(c.first.size() == c.second.size());
            if (flatten_mode) {
                // more conservative approach:
                // connect internal and external wires
                module->connect(c);
            } else {
                // approach that yields nicer outputs:
                // replace internal wires that are connected to external wires
                if (w->port_output)
                    port_signal_map.add(c.second, c.first);
                else
                    port_signal_map.add(c.first, c.second);
            }
        }

        for (auto &it : tpl->cells_)
        {
            std::string c_name = it.second->name.str();

            if (!flatten_mode && c_name == "\\_TECHMAP_REPLACE_")
                c_name = orig_cell_name;
            else
                apply_prefix(cell->name.str(), c_name);

            RTLIL::Cell *c = module->addCell(c_name, it.second);
            design->select(module, c);

            if (!flatten_mode && c->type.substr(0, 2) == "\\$")
                c->type = c->type.substr(1);

            for (auto &it2 : c->connections_) {
                apply_prefix(cell->name.str(), it2.second, module);
                port_signal_map.apply(it2.second);
            }
        }

        for (auto &it : tpl->connections()) {
            RTLIL::SigSig c = it;
            apply_prefix(cell->name.str(), c.first, module);
            apply_prefix(cell->name.str(), c.second, module);
            port_signal_map.apply(c.first);
            port_signal_map.apply(c.second);
            module->connect(c);
        }

        module->remove(cell);
    }

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Field Documentation

bool TechmapWorker::assert_mode

Definition at line 80 of file techmap.cc.

bool TechmapWorker::autoproc_mode

Definition at line 83 of file techmap.cc.

bool TechmapWorker::extern_mode

Definition at line 79 of file techmap.cc.

bool TechmapWorker::flatten_mode

Definition at line 81 of file techmap.cc.

std::set<RTLIL::Module*, RTLIL::IdString::compare_ptr_by_name<RTLIL::Module> > TechmapWorker::module_queue

Definition at line 70 of file techmap.cc.

bool TechmapWorker::recursive_mode

Definition at line 82 of file techmap.cc.

std::map<RTLIL::IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> TechmapWorker::simplemap_mappers

Definition at line 67 of file techmap.cc.

std::map<std::pair<RTLIL::IdString, std::map<RTLIL::IdString, RTLIL::Const> >, RTLIL::Module*> TechmapWorker::techmap_cache

Definition at line 68 of file techmap.cc.

std::map<RTLIL::Module*, bool> TechmapWorker::techmap_do_cache

Definition at line 69 of file techmap.cc.

---

The documentation for this struct was generated from the following file:

• techmap.cc