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fsm_recode.cc
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1 /*
2  * yosys -- Yosys Open SYnthesis Suite
3  *
4  * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5  *
6  * Permission to use, copy, modify, and/or distribute this software for any
7  * purpose with or without fee is hereby granted, provided that the above
8  * copyright notice and this permission notice appear in all copies.
9  *
10  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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13  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17  *
18  */
19 
20 #include "kernel/log.h"
21 #include "kernel/register.h"
22 #include "kernel/sigtools.h"
23 #include "kernel/consteval.h"
24 #include "kernel/celltypes.h"
25 #include "fsmdata.h"
26 #include <math.h>
27 #include <string.h>
28 #include <errno.h>
29 
32 
33 static void fm_set_fsm_print(RTLIL::Cell *cell, RTLIL::Module *module, FsmData &fsm_data, const char *prefix, FILE *f)
34 {
35  std::string name = cell->parameters["\\NAME"].decode_string();
36 
37  fprintf(f, "set_fsm_state_vector {");
38  for (int i = fsm_data.state_bits-1; i >= 0; i--)
39  fprintf(f, " %s_reg[%d]", name[0] == '\\' ? name.substr(1).c_str() : name.c_str(), i);
40  fprintf(f, " } -name {%s_%s} {%s:/WORK/%s}\n", prefix, RTLIL::unescape_id(name).c_str(),
41  prefix, RTLIL::unescape_id(module->name).c_str());
42 
43  fprintf(f, "set_fsm_encoding {");
44  for (int i = 0; i < GetSize(fsm_data.state_table); i++) {
45  fprintf(f, " s%d=2#", i);
46  for (int j = GetSize(fsm_data.state_table[i].bits)-1; j >= 0; j--)
47  fprintf(f, "%c", fsm_data.state_table[i].bits[j] == RTLIL::State::S1 ? '1' : '0');
48  }
49  fprintf(f, " } -name {%s_%s} {%s:/WORK/%s}\n",
50  prefix, RTLIL::unescape_id(name).c_str(),
51  prefix, RTLIL::unescape_id(module->name).c_str());
52 }
53 
54 static void fsm_recode(RTLIL::Cell *cell, RTLIL::Module *module, FILE *fm_set_fsm_file, std::string default_encoding)
55 {
56  std::string encoding = cell->attributes.count("\\fsm_encoding") ? cell->attributes.at("\\fsm_encoding").decode_string() : "auto";
57 
58  log("Recoding FSM `%s' from module `%s' using `%s' encoding:\n", cell->name.c_str(), module->name.c_str(), encoding.c_str());
59 
60  if (encoding != "none" && encoding != "one-hot" && encoding != "binary" && encoding != "auto") {
61  log(" unknown encoding `%s': using auto instead.\n", encoding.c_str());
62  encoding = "auto";
63  }
64 
65  if (encoding == "none") {
66  log(" nothing to do for encoding `none'.\n");
67  return;
68  }
69 
70  FsmData fsm_data;
71  fsm_data.copy_from_cell(cell);
72 
73  if (fm_set_fsm_file != NULL)
74  fm_set_fsm_print(cell, module, fsm_data, "r", fm_set_fsm_file);
75 
76  if (encoding == "auto") {
77  if (!default_encoding.empty())
78  encoding = default_encoding;
79  else
80  encoding = GetSize(fsm_data.state_table) < 32 ? "one-hot" : "binary";
81  log(" mapping auto encoding to `%s` for this FSM.\n", encoding.c_str());
82  }
83 
84  if (encoding == "one-hot") {
85  fsm_data.state_bits = fsm_data.state_table.size();
86  } else
87  if (encoding == "binary") {
88  int new_num_state_bits = ceil(log2(fsm_data.state_table.size()));
89  if (fsm_data.state_bits == new_num_state_bits) {
90  log(" existing encoding is already a packed binary encoding.\n");
91  return;
92  }
93  fsm_data.state_bits = new_num_state_bits;
94  } else
95  log_error("FSM encoding `%s' is not supported!\n", encoding.c_str());
96 
97  int state_idx_counter = fsm_data.reset_state >= 0 ? 1 : 0;
98  for (int i = 0; i < int(fsm_data.state_table.size()); i++)
99  {
100  int state_idx = fsm_data.reset_state == i ? 0 : state_idx_counter++;
101  RTLIL::Const new_code;
102 
103  if (encoding == "one-hot") {
104  new_code = RTLIL::Const(RTLIL::State::Sa, fsm_data.state_bits);
105  new_code.bits[state_idx] = RTLIL::State::S1;
106  } else
107  if (encoding == "binary") {
108  new_code = RTLIL::Const(state_idx, fsm_data.state_bits);
109  } else
110  log_abort();
111 
112  log(" %s -> %s\n", fsm_data.state_table[i].as_string().c_str(), new_code.as_string().c_str());
113  fsm_data.state_table[i] = new_code;
114  }
115 
116  if (fm_set_fsm_file != NULL)
117  fm_set_fsm_print(cell, module, fsm_data, "i", fm_set_fsm_file);
118 
119  fsm_data.copy_to_cell(cell);
120 }
121 
122 struct FsmRecodePass : public Pass {
123  FsmRecodePass() : Pass("fsm_recode", "recoding finite state machines") { }
124  virtual void help()
125  {
126  // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
127  log("\n");
128  log(" fsm_recode [-encoding type] [-fm_set_fsm_file file] [selection]\n");
129  log("\n");
130  log("This pass reassign the state encodings for FSM cells. At the moment only\n");
131  log("one-hot encoding and binary encoding is supported. The option -encoding\n");
132  log("can be used to specify the encoding scheme used for FSMs without the\n");
133  log("`fsm_encoding' attribute (or with the attribute set to `auto'.\n");
134  log("\n");
135  log("The option -fm_set_fsm_file can be used to generate a file containing the\n");
136  log("mapping from old to new FSM encoding in form of Synopsys Formality set_fsm_*\n");
137  log("commands.\n");
138  log("\n");
139  }
140  virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
141  {
142  FILE *fm_set_fsm_file = NULL;
143  std::string default_encoding;
144 
145  log_header("Executing FSM_RECODE pass (re-assigning FSM state encoding).\n");
146  size_t argidx;
147  for (argidx = 1; argidx < args.size(); argidx++) {
148  std::string arg = args[argidx];
149  if (arg == "-fm_set_fsm_file" && argidx+1 < args.size() && fm_set_fsm_file == NULL) {
150  fm_set_fsm_file = fopen(args[++argidx].c_str(), "w");
151  if (fm_set_fsm_file == NULL)
152  log_error("Can't open fm_set_fsm_file `%s' for writing: %s\n", args[argidx].c_str(), strerror(errno));
153  continue;
154  }
155  if (arg == "-encoding" && argidx+1 < args.size() && fm_set_fsm_file == NULL) {
156  default_encoding = args[++argidx];
157  continue;
158  }
159  break;
160  }
161  extra_args(args, argidx, design);
162 
163  for (auto &mod_it : design->modules_)
164  if (design->selected(mod_it.second))
165  for (auto &cell_it : mod_it.second->cells_)
166  if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second))
167  fsm_recode(cell_it.second, mod_it.second, fm_set_fsm_file, default_encoding);
168 
169  if (fm_set_fsm_file != NULL)
170  fclose(fm_set_fsm_file);
171  }
172 } FsmRecodePass;
173 
const char * c_str() const
Definition: rtlil.h:178
bool selected(T1 *module) const
Definition: rtlil.h:551
void log_header(const char *format,...)
Definition: log.cc:188
static std::string unescape_id(std::string str)
Definition: rtlil.h:257
RTLIL::IdString name
Definition: rtlil.h:853
void copy_to_cell(RTLIL::Cell *cell)
Definition: fsmdata.h:34
virtual void help()
Definition: fsm_recode.cc:124
void log_error(const char *format,...)
Definition: log.cc:204
RTLIL::Module * module
Definition: abc.cc:94
std::map< RTLIL::IdString, RTLIL::Const > parameters
Definition: rtlil.h:856
#define log_abort()
Definition: log.h:84
FsmRecodePass FsmRecodePass
int state_bits
Definition: fsmdata.h:29
std::string as_string() const
Definition: rtlil.cc:116
#define PRIVATE_NAMESPACE_BEGIN
Definition: yosys.h:97
int GetSize(RTLIL::Wire *wire)
Definition: yosys.cc:334
RTLIL::IdString name
Definition: rtlil.h:599
static void fsm_recode(RTLIL::Cell *cell, RTLIL::Module *module, FILE *fm_set_fsm_file, std::string default_encoding)
Definition: fsm_recode.cc:54
#define PRIVATE_NAMESPACE_END
Definition: yosys.h:98
Definition: register.h:27
#define USING_YOSYS_NAMESPACE
Definition: yosys.h:102
std::map< RTLIL::IdString, RTLIL::Module * > modules_
Definition: rtlil.h:507
#define NULL
std::vector< RTLIL::Const > state_table
Definition: fsmdata.h:32
void log(const char *format,...)
Definition: log.cc:180
void copy_from_cell(RTLIL::Cell *cell)
Definition: fsmdata.h:79
std::vector< RTLIL::State > bits
Definition: rtlil.h:438
USING_YOSYS_NAMESPACE static PRIVATE_NAMESPACE_BEGIN void fm_set_fsm_print(RTLIL::Cell *cell, RTLIL::Module *module, FsmData &fsm_data, const char *prefix, FILE *f)
Definition: fsm_recode.cc:33
virtual void execute(std::vector< std::string > args, RTLIL::Design *design)
Definition: fsm_recode.cc:140
void extra_args(std::vector< std::string > args, size_t argidx, RTLIL::Design *design, bool select=true)
Definition: register.cc:128
int reset_state
Definition: fsmdata.h:29