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EvalPass Struct Reference
+ Inheritance diagram for EvalPass:
+ Collaboration diagram for EvalPass:

Public Member Functions

 EvalPass ()
 
virtual void help ()
 
virtual void execute (std::vector< std::string > args, RTLIL::Design *design)
 
pre_post_exec_state_t pre_execute ()
 
void post_execute (pre_post_exec_state_t state)
 
void cmd_log_args (const std::vector< std::string > &args)
 
void cmd_error (const std::vector< std::string > &args, size_t argidx, std::string msg)
 
void extra_args (std::vector< std::string > args, size_t argidx, RTLIL::Design *design, bool select=true)
 
virtual void run_register ()
 

Static Public Member Functions

static void call (RTLIL::Design *design, std::string command)
 
static void call (RTLIL::Design *design, std::vector< std::string > args)
 
static void call_on_selection (RTLIL::Design *design, const RTLIL::Selection &selection, std::string command)
 
static void call_on_selection (RTLIL::Design *design, const RTLIL::Selection &selection, std::vector< std::string > args)
 
static void call_on_module (RTLIL::Design *design, RTLIL::Module *module, std::string command)
 
static void call_on_module (RTLIL::Design *design, RTLIL::Module *module, std::vector< std::string > args)
 
static void init_register ()
 
static void done_register ()
 

Data Fields

std::string pass_name
 
std::string short_help
 
int call_counter
 
int64_t runtime_ns
 
Passnext_queued_pass
 

Detailed Description

Definition at line 361 of file eval.cc.

Constructor & Destructor Documentation

EvalPass::EvalPass ( )
inline

Definition at line 362 of file eval.cc.

362 : Pass("eval", "evaluate the circuit given an input") { }
Pass(std::string name, std::string short_help="** document me **")
Definition: register.cc:40

Member Function Documentation

void Pass::call ( RTLIL::Design design,
std::string  command 
)
staticinherited

Definition at line 146 of file register.cc.

147 {
148  std::vector<std::string> args;
149 
150  std::string cmd_buf = command;
151  std::string tok = next_token(cmd_buf, " \t\r\n");
152 
153  if (tok.empty() || tok[0] == '#')
154  return;
155 
156  if (tok[0] == '!') {
157  cmd_buf = command.substr(command.find('!') + 1);
158  while (!cmd_buf.empty() && (cmd_buf.back() == ' ' || cmd_buf.back() == '\t' ||
159  cmd_buf.back() == '\r' || cmd_buf.back() == '\n'))
160  cmd_buf.resize(cmd_buf.size()-1);
161  log_header("Shell command: %s\n", cmd_buf.c_str());
162  int retCode = run_command(cmd_buf);
163  if (retCode != 0)
164  log_cmd_error("Shell command returned error code %d.\n", retCode);
165  return;
166  }
167 
168  while (!tok.empty()) {
169  if (tok == "#")
170  break;
171  if (tok.back() == ';') {
172  int num_semikolon = 0;
173  while (!tok.empty() && tok.back() == ';')
174  tok.resize(tok.size()-1), num_semikolon++;
175  if (!tok.empty())
176  args.push_back(tok);
177  call(design, args);
178  args.clear();
179  if (num_semikolon == 2)
180  call(design, "clean");
181  if (num_semikolon == 3)
182  call(design, "clean -purge");
183  } else
184  args.push_back(tok);
185  tok = next_token(cmd_buf, " \t\r\n");
186  }
187 
188  call(design, args);
189 }
static std::string next_token(bool pass_newline=false)
Definition: preproc.cc:96
void log_header(const char *format,...)
Definition: log.cc:188
int run_command(const std::string &command, std::function< void(const std::string &)> process_line)
Definition: yosys.cc:195
void log_cmd_error(const char *format,...)
Definition: log.cc:211
static void call(RTLIL::Design *design, std::string command)
Definition: register.cc:146

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void Pass::call ( RTLIL::Design design,
std::vector< std::string >  args 
)
staticinherited

Definition at line 191 of file register.cc.

192 {
193  if (args.size() == 0 || args[0][0] == '#')
194  return;
195 
196  if (echo_mode) {
197  log("%s", create_prompt(design, 0));
198  for (size_t i = 0; i < args.size(); i++)
199  log("%s%s", i ? " " : "", args[i].c_str());
200  log("\n");
201  }
202 
203  if (pass_register.count(args[0]) == 0)
204  log_cmd_error("No such command: %s (type 'help' for a command overview)\n", args[0].c_str());
205 
206  size_t orig_sel_stack_pos = design->selection_stack.size();
207  auto state = pass_register[args[0]]->pre_execute();
208  pass_register[args[0]]->execute(args, design);
209  pass_register[args[0]]->post_execute(state);
210  while (design->selection_stack.size() > orig_sel_stack_pos)
211  design->selection_stack.pop_back();
212 
213  design->check();
214 }
bool echo_mode
Definition: register.cc:30
std::vector< RTLIL::Selection > selection_stack
Definition: rtlil.h:509
const char * create_prompt(RTLIL::Design *design, int recursion_counter)
Definition: yosys.cc:400
void check()
Definition: rtlil.cc:357
void log_cmd_error(const char *format,...)
Definition: log.cc:211
void log(const char *format,...)
Definition: log.cc:180
std::map< std::string, Pass * > pass_register
Definition: register.cc:35

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void Pass::call_on_module ( RTLIL::Design design,
RTLIL::Module module,
std::string  command 
)
staticinherited

Definition at line 240 of file register.cc.

241 {
242  std::string backup_selected_active_module = design->selected_active_module;
243  design->selected_active_module = module->name.str();
244  design->selection_stack.push_back(RTLIL::Selection(false));
245  design->selection_stack.back().select(module);
246 
247  Pass::call(design, command);
248 
249  design->selection_stack.pop_back();
250  design->selected_active_module = backup_selected_active_module;
251 }
std::string str() const
Definition: rtlil.h:182
std::vector< RTLIL::Selection > selection_stack
Definition: rtlil.h:509
RTLIL::IdString name
Definition: rtlil.h:599
std::string selected_active_module
Definition: rtlil.h:511
static void call(RTLIL::Design *design, std::string command)
Definition: register.cc:146

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void Pass::call_on_module ( RTLIL::Design design,
RTLIL::Module module,
std::vector< std::string >  args 
)
staticinherited

Definition at line 253 of file register.cc.

254 {
255  std::string backup_selected_active_module = design->selected_active_module;
256  design->selected_active_module = module->name.str();
257  design->selection_stack.push_back(RTLIL::Selection(false));
258  design->selection_stack.back().select(module);
259 
260  Pass::call(design, args);
261 
262  design->selection_stack.pop_back();
263  design->selected_active_module = backup_selected_active_module;
264 }
std::string str() const
Definition: rtlil.h:182
std::vector< RTLIL::Selection > selection_stack
Definition: rtlil.h:509
RTLIL::IdString name
Definition: rtlil.h:599
std::string selected_active_module
Definition: rtlil.h:511
static void call(RTLIL::Design *design, std::string command)
Definition: register.cc:146

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void Pass::call_on_selection ( RTLIL::Design design,
const RTLIL::Selection selection,
std::string  command 
)
staticinherited

Definition at line 216 of file register.cc.

217 {
218  std::string backup_selected_active_module = design->selected_active_module;
219  design->selected_active_module.clear();
220  design->selection_stack.push_back(selection);
221 
222  Pass::call(design, command);
223 
224  design->selection_stack.pop_back();
225  design->selected_active_module = backup_selected_active_module;
226 }
std::vector< RTLIL::Selection > selection_stack
Definition: rtlil.h:509
std::string selected_active_module
Definition: rtlil.h:511
static void call(RTLIL::Design *design, std::string command)
Definition: register.cc:146

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void Pass::call_on_selection ( RTLIL::Design design,
const RTLIL::Selection selection,
std::vector< std::string >  args 
)
staticinherited

Definition at line 228 of file register.cc.

229 {
230  std::string backup_selected_active_module = design->selected_active_module;
231  design->selected_active_module.clear();
232  design->selection_stack.push_back(selection);
233 
234  Pass::call(design, args);
235 
236  design->selection_stack.pop_back();
237  design->selected_active_module = backup_selected_active_module;
238 }
std::vector< RTLIL::Selection > selection_stack
Definition: rtlil.h:509
std::string selected_active_module
Definition: rtlil.h:511
static void call(RTLIL::Design *design, std::string command)
Definition: register.cc:146

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void Pass::cmd_error ( const std::vector< std::string > &  args,
size_t  argidx,
std::string  msg 
)
inherited

Definition at line 110 of file register.cc.

111 {
112  std::string command_text;
113  int error_pos = 0;
114 
115  for (size_t i = 0; i < args.size(); i++) {
116  if (i < argidx)
117  error_pos += args[i].size() + 1;
118  command_text = command_text + (command_text.empty() ? "" : " ") + args[i];
119  }
120 
121  log("\nSyntax error in command `%s':\n", command_text.c_str());
122  help();
123 
124  log_cmd_error("Command syntax error: %s\n> %s\n> %*s^\n",
125  msg.c_str(), command_text.c_str(), error_pos, "");
126 }
virtual void help()
Definition: register.cc:93
void log_cmd_error(const char *format,...)
Definition: log.cc:211
void log(const char *format,...)
Definition: log.cc:180

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void Pass::cmd_log_args ( const std::vector< std::string > &  args)
inherited

Definition at line 100 of file register.cc.

101 {
102  if (args.size() <= 1)
103  return;
104  log("Full command line:");
105  for (size_t i = 0; i < args.size(); i++)
106  log(" %s", args[i].c_str());
107  log("\n");
108 }
void log(const char *format,...)
Definition: log.cc:180

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void Pass::done_register ( )
staticinherited

Definition at line 62 of file register.cc.

63 {
64  frontend_register.clear();
65  pass_register.clear();
66  backend_register.clear();
68 }
std::map< std::string, Frontend * > frontend_register
Definition: register.cc:34
Pass * first_queued_pass
Definition: register.cc:31
#define log_assert(_assert_expr_)
Definition: log.h:85
#define NULL
std::map< std::string, Pass * > pass_register
Definition: register.cc:35
std::map< std::string, Backend * > backend_register
Definition: register.cc:36

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virtual void EvalPass::execute ( std::vector< std::string >  args,
RTLIL::Design design 
)
inlinevirtual

Implements Pass.

Definition at line 386 of file eval.cc.

387  {
388  std::vector<std::pair<std::string, std::string>> sets;
389  std::vector<std::string> shows, tables;
390  bool set_undef = false;
391 
392  log_header("Executing EVAL pass (evaluate the circuit given an input).\n");
393 
394  size_t argidx;
395  for (argidx = 1; argidx < args.size(); argidx++) {
396  if (args[argidx] == "-set" && argidx+2 < args.size()) {
397  std::string lhs = args[++argidx].c_str();
398  std::string rhs = args[++argidx].c_str();
399  sets.push_back(std::pair<std::string, std::string>(lhs, rhs));
400  continue;
401  }
402  if (args[argidx] == "-set-undef") {
403  set_undef = true;
404  continue;
405  }
406  if (args[argidx] == "-show" && argidx+1 < args.size()) {
407  shows.push_back(args[++argidx]);
408  continue;
409  }
410  if (args[argidx] == "-table" && argidx+1 < args.size()) {
411  tables.push_back(args[++argidx]);
412  continue;
413  }
414  if ((args[argidx] == "-brute_force_equiv_checker" || args[argidx] == "-brute_force_equiv_checker_x") && argidx+3 == args.size()) {
415  /* this should only be used for regression testing of ConstEval -- see vloghammer */
416  std::string mod1_name = RTLIL::escape_id(args[++argidx]);
417  std::string mod2_name = RTLIL::escape_id(args[++argidx]);
418  if (design->modules_.count(mod1_name) == 0)
419  log_error("Can't find module `%s'!\n", mod1_name.c_str());
420  if (design->modules_.count(mod2_name) == 0)
421  log_error("Can't find module `%s'!\n", mod2_name.c_str());
422  BruteForceEquivChecker checker(design->modules_.at(mod1_name), design->modules_.at(mod2_name), args[argidx-2] == "-brute_force_equiv_checker_x");
423  if (checker.errors > 0)
424  log_cmd_error("Modules are not equivialent!\n");
425  log("Verified %s = %s (using brute-force check on %d cases).\n",
426  mod1_name.c_str(), mod2_name.c_str(), checker.counter);
427  return;
428  }
429  if (args[argidx] == "-vloghammer_report" && argidx+5 == args.size()) {
430  /* this should only be used for regression testing of ConstEval -- see vloghammer */
431  std::string module_prefix = args[++argidx];
432  std::string module_list = args[++argidx];
433  std::string input_list = args[++argidx];
434  std::string pattern_list = args[++argidx];
435  VlogHammerReporter reporter(design, module_prefix, module_list, input_list, pattern_list);
436  reporter.run();
437  return;
438  }
439  break;
440  }
441  extra_args(args, argidx, design);
442 
444  for (auto &mod_it : design->modules_)
445  if (design->selected(mod_it.second)) {
446  if (module)
447  log_cmd_error("Only one module must be selected for the EVAL pass! (selected: %s and %s)\n",
448  RTLIL::id2cstr(module->name), RTLIL::id2cstr(mod_it.first));
449  module = mod_it.second;
450  }
451  if (module == NULL)
452  log_cmd_error("Can't perform EVAL on an empty selection!\n");
453 
454  ConstEval ce(module);
455 
456  for (auto &it : sets) {
457  RTLIL::SigSpec lhs, rhs;
458  if (!RTLIL::SigSpec::parse_sel(lhs, design, module, it.first))
459  log_cmd_error("Failed to parse lhs set expression `%s'.\n", it.first.c_str());
460  if (!RTLIL::SigSpec::parse_rhs(lhs, rhs, module, it.second))
461  log_cmd_error("Failed to parse rhs set expression `%s'.\n", it.second.c_str());
462  if (!rhs.is_fully_const())
463  log_cmd_error("Right-hand-side set expression `%s' is not constant.\n", it.second.c_str());
464  if (lhs.size() != rhs.size())
465  log_cmd_error("Set expression with different lhs and rhs sizes: %s (%s, %d bits) vs. %s (%s, %d bits)\n",
466  it.first.c_str(), log_signal(lhs), lhs.size(), it.second.c_str(), log_signal(rhs), rhs.size());
467  ce.set(lhs, rhs.as_const());
468  }
469 
470  if (shows.size() == 0) {
471  for (auto &it : module->wires_)
472  if (it.second->port_output)
473  shows.push_back(it.second->name.str());
474  }
475 
476  if (tables.empty())
477  {
478  for (auto &it : shows) {
479  RTLIL::SigSpec signal, value, undef;
480  if (!RTLIL::SigSpec::parse_sel(signal, design, module, it))
481  log_cmd_error("Failed to parse show expression `%s'.\n", it.c_str());
482  value = signal;
483  if (set_undef) {
484  while (!ce.eval(value, undef)) {
485  log("Failed to evaluate signal %s: Missing value for %s. -> setting to undef\n", log_signal(signal), log_signal(undef));
486  ce.set(undef, RTLIL::Const(RTLIL::State::Sx, undef.size()));
487  undef = RTLIL::SigSpec();
488  }
489  log("Eval result: %s = %s.\n", log_signal(signal), log_signal(value));
490  } else {
491  if (!ce.eval(value, undef))
492  log("Failed to evaluate signal %s: Missing value for %s.\n", log_signal(signal), log_signal(undef));
493  else
494  log("Eval result: %s = %s.\n", log_signal(signal), log_signal(value));
495  }
496  }
497  }
498  else
499  {
500  RTLIL::SigSpec tabsigs, signal, value, undef;
501  std::vector<std::vector<std::string>> tab;
502  int tab_sep_colidx = 0;
503 
504  for (auto &it : shows) {
505  RTLIL::SigSpec sig;
506  if (!RTLIL::SigSpec::parse_sel(sig, design, module, it))
507  log_cmd_error("Failed to parse show expression `%s'.\n", it.c_str());
508  signal.append(sig);
509  }
510 
511  for (auto &it : tables) {
512  RTLIL::SigSpec sig;
513  if (!RTLIL::SigSpec::parse_sel(sig, design, module, it))
514  log_cmd_error("Failed to parse table expression `%s'.\n", it.c_str());
515  tabsigs.append(sig);
516  }
517 
518  std::vector<std::string> tab_line;
519  for (auto &c : tabsigs.chunks())
520  tab_line.push_back(log_signal(c));
521  tab_sep_colidx = tab_line.size();
522  for (auto &c : signal.chunks())
523  tab_line.push_back(log_signal(c));
524  tab.push_back(tab_line);
525  tab_line.clear();
526 
527  RTLIL::Const tabvals(0, tabsigs.size());
528  do
529  {
530  ce.push();
531  ce.set(tabsigs, tabvals);
532  value = signal;
533 
534  RTLIL::SigSpec this_undef;
535  while (!ce.eval(value, this_undef)) {
536  if (!set_undef) {
537  log("Failed to evaluate signal %s at %s = %s: Missing value for %s.\n", log_signal(signal),
538  log_signal(tabsigs), log_signal(tabvals), log_signal(this_undef));
539  return;
540  }
541  ce.set(this_undef, RTLIL::Const(RTLIL::State::Sx, this_undef.size()));
542  undef.append(this_undef);
543  this_undef = RTLIL::SigSpec();
544  }
545 
546  int pos = 0;
547  for (auto &c : tabsigs.chunks()) {
548  tab_line.push_back(log_signal(RTLIL::SigSpec(tabvals).extract(pos, c.width)));
549  pos += c.width;
550  }
551 
552  pos = 0;
553  for (auto &c : signal.chunks()) {
554  tab_line.push_back(log_signal(value.extract(pos, c.width)));
555  pos += c.width;
556  }
557 
558  tab.push_back(tab_line);
559  tab_line.clear();
560  ce.pop();
561 
562  tabvals = RTLIL::const_add(tabvals, RTLIL::Const(1), false, false, tabvals.bits.size());
563  }
564  while (tabvals.as_bool());
565 
566  std::vector<int> tab_column_width;
567  for (auto &row : tab) {
568  if (tab_column_width.size() < row.size())
569  tab_column_width.resize(row.size());
570  for (size_t i = 0; i < row.size(); i++)
571  tab_column_width[i] = std::max(tab_column_width[i], int(row[i].size()));
572  }
573 
574  log("\n");
575  bool first = true;
576  for (auto &row : tab) {
577  for (size_t i = 0; i < row.size(); i++) {
578  int k = int(i) < tab_sep_colidx ? tab_sep_colidx - i - 1 : i;
579  log(" %s%*s", k == tab_sep_colidx ? "| " : "", tab_column_width[k], row[k].c_str());
580  }
581  log("\n");
582  if (first) {
583  for (size_t i = 0; i < row.size(); i++) {
584  int k = int(i) < tab_sep_colidx ? tab_sep_colidx - i - 1 : i;
585  log(" %s", k == tab_sep_colidx ? "| " : "");
586  for (int j = 0; j < tab_column_width[k]; j++)
587  log("-");
588  }
589  log("\n");
590  first = false;
591  }
592  }
593 
594  log("\n");
595  if (undef.size() > 0) {
596  undef.sort_and_unify();
597  log("Assumend undef (x) value for the following singals: %s\n\n", log_signal(undef));
598  }
599  }
600  }
bool selected(T1 *module) const
Definition: rtlil.h:551
static bool parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str)
Definition: rtlil.cc:3058
void log_header(const char *format,...)
Definition: log.cc:188
RTLIL::Const as_const() const
Definition: rtlil.cc:2857
std::map< RTLIL::IdString, RTLIL::Wire * > wires_
Definition: rtlil.h:595
const char * log_signal(const RTLIL::SigSpec &sig, bool autoint)
Definition: log.cc:269
void log_error(const char *format,...)
Definition: log.cc:204
RTLIL::Module * module
Definition: abc.cc:94
int size() const
Definition: rtlil.h:1019
static std::string escape_id(std::string str)
Definition: rtlil.h:251
bool is_fully_const() const
Definition: rtlil.cc:2763
RTLIL::IdString name
Definition: rtlil.h:599
static const char * id2cstr(const RTLIL::IdString &str)
Definition: rtlil.h:267
void log_cmd_error(const char *format,...)
Definition: log.cc:211
std::map< RTLIL::IdString, RTLIL::Module * > modules_
Definition: rtlil.h:507
void sort_and_unify()
Definition: rtlil.cc:2291
#define NULL
void log(const char *format,...)
Definition: log.cc:180
RTLIL::SigSpec extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other=NULL) const
Definition: rtlil.cc:2414
std::vector< RTLIL::State > bits
Definition: rtlil.h:438
void append(const RTLIL::SigSpec &signal)
Definition: rtlil.cc:2523
RTLIL::Const const_add(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
Definition: calc.cc:464
static bool parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
Definition: rtlil.cc:3078
void extra_args(std::vector< std::string > args, size_t argidx, RTLIL::Design *design, bool select=true)
Definition: register.cc:128
const std::vector< RTLIL::SigChunk > & chunks() const
Definition: rtlil.h:1016

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void Pass::extra_args ( std::vector< std::string >  args,
size_t  argidx,
RTLIL::Design design,
bool  select = true 
)
inherited

Definition at line 128 of file register.cc.

129 {
130  for (; argidx < args.size(); argidx++)
131  {
132  std::string arg = args[argidx];
133 
134  if (arg.substr(0, 1) == "-")
135  cmd_error(args, argidx, "Unknown option or option in arguments.");
136 
137  if (!select)
138  cmd_error(args, argidx, "Extra argument.");
139 
140  handle_extra_select_args(this, args, argidx, args.size(), design);
141  break;
142  }
143  // cmd_log_args(args);
144 }
void cmd_error(const std::vector< std::string > &args, size_t argidx, std::string msg)
Definition: register.cc:110
void handle_extra_select_args(Pass *pass, std::vector< std::string > args, size_t argidx, size_t args_size, RTLIL::Design *design)
Definition: select.cc:803

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virtual void EvalPass::help ( )
inlinevirtual

Reimplemented from Pass.

Definition at line 363 of file eval.cc.

364  {
365  // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
366  log("\n");
367  log(" eval [options] [selection]\n");
368  log("\n");
369  log("This command evaluates the value of a signal given the value of all required\n");
370  log("inputs.\n");
371  log("\n");
372  log(" -set <signal> <value>\n");
373  log(" set the specified signal to the specified value.\n");
374  log("\n");
375  log(" -set-undef\n");
376  log(" set all unspecified source signals to undef (x)\n");
377  log("\n");
378  log(" -table <signal>\n");
379  log(" create a truth table using the specified input signals\n");
380  log("\n");
381  log(" -show <signal>\n");
382  log(" show the value for the specified signal. if no -show option is passed\n");
383  log(" then all output ports of the current module are used.\n");
384  log("\n");
385  }
void log(const char *format,...)
Definition: log.cc:180

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void Pass::init_register ( )
staticinherited

Definition at line 54 of file register.cc.

55 {
56  while (first_queued_pass) {
59  }
60 }
Pass * first_queued_pass
Definition: register.cc:31
Pass * next_queued_pass
Definition: register.h:60
virtual void run_register()
Definition: register.cc:48

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void Pass::post_execute ( Pass::pre_post_exec_state_t  state)
inherited

Definition at line 84 of file register.cc.

85 {
86  int64_t time_ns = PerformanceTimer::query() - state.begin_ns;
87  runtime_ns += time_ns;
88  current_pass = state.parent_pass;
89  if (current_pass)
90  current_pass->runtime_ns -= time_ns;
91 }
static int64_t query()
Definition: log.h:151
int64_t runtime_ns
Definition: register.h:37
Pass * current_pass
Definition: register.cc:32
Pass * parent_pass
Definition: register.h:40
int64_t begin_ns
Definition: register.h:41

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Pass::pre_post_exec_state_t Pass::pre_execute ( )
inherited

Definition at line 74 of file register.cc.

75 {
76  pre_post_exec_state_t state;
77  call_counter++;
78  state.begin_ns = PerformanceTimer::query();
79  state.parent_pass = current_pass;
80  current_pass = this;
81  return state;
82 }
static int64_t query()
Definition: log.h:151
Pass * current_pass
Definition: register.cc:32
int call_counter
Definition: register.h:36

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void Pass::run_register ( )
virtualinherited

Reimplemented in Backend, and Frontend.

Definition at line 48 of file register.cc.

49 {
50  log_assert(pass_register.count(pass_name) == 0);
51  pass_register[pass_name] = this;
52 }
std::string pass_name
Definition: register.h:29
#define log_assert(_assert_expr_)
Definition: log.h:85
std::map< std::string, Pass * > pass_register
Definition: register.cc:35

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Field Documentation

int Pass::call_counter
inherited

Definition at line 36 of file register.h.

Pass* Pass::next_queued_pass
inherited

Definition at line 60 of file register.h.

std::string Pass::pass_name
inherited

Definition at line 29 of file register.h.

int64_t Pass::runtime_ns
inherited

Definition at line 37 of file register.h.

std::string Pass::short_help
inherited

Definition at line 29 of file register.h.


The documentation for this struct was generated from the following file: