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Data Structures | Functions
genrtlil.cc File Reference
#include "kernel/log.h"
#include "kernel/utils.h"
#include "libs/sha1/sha1.h"
#include "ast.h"
#include <sstream>
#include <stdarg.h>
#include <algorithm>
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Data Structures

struct  AST_INTERNAL::ProcessGenerator
 

Functions

static RTLIL::SigSpec uniop2rtlil (AstNode *that, std::string type, int result_width, const RTLIL::SigSpec &arg, bool gen_attributes=true)
 
static void widthExtend (AstNode *that, RTLIL::SigSpec &sig, int width, bool is_signed)
 
static RTLIL::SigSpec binop2rtlil (AstNode *that, std::string type, int result_width, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right)
 
static RTLIL::SigSpec mux2rtlil (AstNode *that, const RTLIL::SigSpec &cond, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right)
 

Function Documentation

static RTLIL::SigSpec binop2rtlil ( AstNode *  that,
std::string  type,
int  result_width,
const RTLIL::SigSpec &  left,
const RTLIL::SigSpec &  right 
)
static

Definition at line 107 of file genrtlil.cc.

108 {
109  std::stringstream sstr;
110  sstr << type << "$" << that->filename << ":" << that->linenum << "$" << (autoidx++);
111 
112  RTLIL::Cell *cell = current_module->addCell(sstr.str(), type);
113  cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
114 
115  RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", result_width);
116  wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
117 
118  for (auto &attr : that->attributes) {
119  if (attr.second->type != AST_CONSTANT)
120  log_error("Attribute `%s' with non-constant value at %s:%d!\n",
121  attr.first.c_str(), that->filename.c_str(), that->linenum);
122  cell->attributes[attr.first] = attr.second->asAttrConst();
123  }
124 
125  cell->parameters["\\A_SIGNED"] = RTLIL::Const(that->children[0]->is_signed);
126  cell->parameters["\\B_SIGNED"] = RTLIL::Const(that->children[1]->is_signed);
127 
128  cell->parameters["\\A_WIDTH"] = RTLIL::Const(left.size());
129  cell->parameters["\\B_WIDTH"] = RTLIL::Const(right.size());
130 
131  cell->setPort("\\A", left);
132  cell->setPort("\\B", right);
133 
134  cell->parameters["\\Y_WIDTH"] = result_width;
135  cell->setPort("\\Y", wire);
136  return wire;
137 }
RTLIL::IdString::str
std::string str() const
Definition: rtlil.h:182
stringf
std::string stringf(const char *fmt,...)
Definition: yosys.cc:58
RTLIL::Module::addCell
RTLIL::Cell * addCell(RTLIL::IdString name, RTLIL::IdString type)
Definition: rtlil.cc:1353
RTLIL::Cell::name
RTLIL::IdString name
Definition: rtlil.h:853
RTLIL::Cell::setPort
void setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
Definition: rtlil.cc:1789
AST::AstNode::attributes
std::map< RTLIL::IdString, AstNode * > attributes
Definition: ast.h:152
log_error
void log_error(const char *format,...)
Definition: log.cc:204
RTLIL::Cell::parameters
std::map< RTLIL::IdString, RTLIL::Const > parameters
Definition: rtlil.h:856
RTLIL::SigSpec::size
int size() const
Definition: rtlil.h:1019
RTLIL::Module::addWire
RTLIL::Wire * addWire(RTLIL::IdString name, int width=1)
Definition: rtlil.cc:1331
AST::AstNode::filename
std::string filename
Definition: ast.h:175
AST::AstNode::children
std::vector< AstNode * > children
Definition: ast.h:149
AST::AstNode::linenum
int linenum
Definition: ast.h:176
AST_INTERNAL::current_module
AstModule * current_module
Definition: ast.cc:62
autoidx
YOSYS_NAMESPACE_BEGIN int autoidx
Definition: yosys.cc:51

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static RTLIL::SigSpec mux2rtlil ( AstNode *  that,
const RTLIL::SigSpec &  cond,
const RTLIL::SigSpec &  left,
const RTLIL::SigSpec &  right 
)
static

Definition at line 140 of file genrtlil.cc.

141 {
142  log_assert(cond.size() == 1);
143 
144  std::stringstream sstr;
145  sstr << "$ternary$" << that->filename << ":" << that->linenum << "$" << (autoidx++);
146 
147  RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$mux");
148  cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
149 
150  RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", left.size());
151  wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
152 
153  for (auto &attr : that->attributes) {
154  if (attr.second->type != AST_CONSTANT)
155  log_error("Attribute `%s' with non-constant value at %s:%d!\n",
156  attr.first.c_str(), that->filename.c_str(), that->linenum);
157  cell->attributes[attr.first] = attr.second->asAttrConst();
158  }
159 
160  cell->parameters["\\WIDTH"] = RTLIL::Const(left.size());
161 
162  cell->setPort("\\A", right);
163  cell->setPort("\\B", left);
164  cell->setPort("\\S", cond);
165  cell->setPort("\\Y", wire);
166 
167  return wire;
168 }
RTLIL::IdString::str
std::string str() const
Definition: rtlil.h:182
stringf
std::string stringf(const char *fmt,...)
Definition: yosys.cc:58
RTLIL::Module::addCell
RTLIL::Cell * addCell(RTLIL::IdString name, RTLIL::IdString type)
Definition: rtlil.cc:1353
RTLIL::Cell::name
RTLIL::IdString name
Definition: rtlil.h:853
RTLIL::Cell::setPort
void setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
Definition: rtlil.cc:1789
AST::AstNode::attributes
std::map< RTLIL::IdString, AstNode * > attributes
Definition: ast.h:152
log_error
void log_error(const char *format,...)
Definition: log.cc:204
RTLIL::Cell::parameters
std::map< RTLIL::IdString, RTLIL::Const > parameters
Definition: rtlil.h:856
RTLIL::SigSpec::size
int size() const
Definition: rtlil.h:1019
log_assert
#define log_assert(_assert_expr_)
Definition: log.h:85
RTLIL::Module::addWire
RTLIL::Wire * addWire(RTLIL::IdString name, int width=1)
Definition: rtlil.cc:1331
AST::AstNode::filename
std::string filename
Definition: ast.h:175
AST::AstNode::linenum
int linenum
Definition: ast.h:176
AST_INTERNAL::current_module
AstModule * current_module
Definition: ast.cc:62
autoidx
YOSYS_NAMESPACE_BEGIN int autoidx
Definition: yosys.cc:51

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static RTLIL::SigSpec uniop2rtlil ( AstNode *  that,
std::string  type,
int  result_width,
const RTLIL::SigSpec &  arg,
bool  gen_attributes = true 
)
static

Definition at line 44 of file genrtlil.cc.

45 {
46  std::stringstream sstr;
47  sstr << type << "$" << that->filename << ":" << that->linenum << "$" << (autoidx++);
48 
49  RTLIL::Cell *cell = current_module->addCell(sstr.str(), type);
50  cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
51 
52  RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", result_width);
53  wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
54 
55  if (gen_attributes)
56  for (auto &attr : that->attributes) {
57  if (attr.second->type != AST_CONSTANT)
58  log_error("Attribute `%s' with non-constant value at %s:%d!\n",
59  attr.first.c_str(), that->filename.c_str(), that->linenum);
60  cell->attributes[attr.first] = attr.second->asAttrConst();
61  }
62 
63  cell->parameters["\\A_SIGNED"] = RTLIL::Const(that->children[0]->is_signed);
64  cell->parameters["\\A_WIDTH"] = RTLIL::Const(arg.size());
65  cell->setPort("\\A", arg);
66 
67  cell->parameters["\\Y_WIDTH"] = result_width;
68  cell->setPort("\\Y", wire);
69  return wire;
70 }
RTLIL::IdString::str
std::string str() const
Definition: rtlil.h:182
stringf
std::string stringf(const char *fmt,...)
Definition: yosys.cc:58
RTLIL::Module::addCell
RTLIL::Cell * addCell(RTLIL::IdString name, RTLIL::IdString type)
Definition: rtlil.cc:1353
RTLIL::Cell::name
RTLIL::IdString name
Definition: rtlil.h:853
RTLIL::Cell::setPort
void setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
Definition: rtlil.cc:1789
AST::AstNode::attributes
std::map< RTLIL::IdString, AstNode * > attributes
Definition: ast.h:152
log_error
void log_error(const char *format,...)
Definition: log.cc:204
RTLIL::Cell::parameters
std::map< RTLIL::IdString, RTLIL::Const > parameters
Definition: rtlil.h:856
RTLIL::SigSpec::size
int size() const
Definition: rtlil.h:1019
RTLIL::Module::addWire
RTLIL::Wire * addWire(RTLIL::IdString name, int width=1)
Definition: rtlil.cc:1331
AST::AstNode::filename
std::string filename
Definition: ast.h:175
AST::AstNode::children
std::vector< AstNode * > children
Definition: ast.h:149
AST::AstNode::linenum
int linenum
Definition: ast.h:176
AST_INTERNAL::current_module
AstModule * current_module
Definition: ast.cc:62
autoidx
YOSYS_NAMESPACE_BEGIN int autoidx
Definition: yosys.cc:51

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static void widthExtend ( AstNode *  that,
RTLIL::SigSpec &  sig,
int  width,
bool  is_signed 
)
static

Definition at line 73 of file genrtlil.cc.

74 {
75  if (width <= sig.size()) {
76  sig.extend(width, is_signed);
77  return;
78  }
79 
80  std::stringstream sstr;
81  sstr << "$extend" << "$" << that->filename << ":" << that->linenum << "$" << (autoidx++);
82 
83  RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$pos");
84  cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
85 
86  RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", width);
87  wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
88 
89  if (that != NULL)
90  for (auto &attr : that->attributes) {
91  if (attr.second->type != AST_CONSTANT)
92  log_error("Attribute `%s' with non-constant value at %s:%d!\n",
93  attr.first.c_str(), that->filename.c_str(), that->linenum);
94  cell->attributes[attr.first] = attr.second->asAttrConst();
95  }
96 
97  cell->parameters["\\A_SIGNED"] = RTLIL::Const(is_signed);
98  cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig.size());
99  cell->setPort("\\A", sig);
100 
101  cell->parameters["\\Y_WIDTH"] = width;
102  cell->setPort("\\Y", wire);
103  sig = wire;
104 }
RTLIL::IdString::str
std::string str() const
Definition: rtlil.h:182
stringf
std::string stringf(const char *fmt,...)
Definition: yosys.cc:58
RTLIL::Module::addCell
RTLIL::Cell * addCell(RTLIL::IdString name, RTLIL::IdString type)
Definition: rtlil.cc:1353
RTLIL::Cell::name
RTLIL::IdString name
Definition: rtlil.h:853
RTLIL::Cell::setPort
void setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
Definition: rtlil.cc:1789
AST::AstNode::attributes
std::map< RTLIL::IdString, AstNode * > attributes
Definition: ast.h:152
log_error
void log_error(const char *format,...)
Definition: log.cc:204
RTLIL::Cell::parameters
std::map< RTLIL::IdString, RTLIL::Const > parameters
Definition: rtlil.h:856
RTLIL::SigSpec::size
int size() const
Definition: rtlil.h:1019
RTLIL::Module::addWire
RTLIL::Wire * addWire(RTLIL::IdString name, int width=1)
Definition: rtlil.cc:1331
NULL
#define NULL
Definition: NumberlikeArray.hh:6
AST::AstNode::filename
std::string filename
Definition: ast.h:175
RTLIL::SigSpec::extend
void extend(int width, bool is_signed=false)
Definition: rtlil.cc:2593
AST::AstNode::linenum
int linenum
Definition: ast.h:176
AST_INTERNAL::current_module
AstModule * current_module
Definition: ast.cc:62
autoidx
YOSYS_NAMESPACE_BEGIN int autoidx
Definition: yosys.cc:51

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