|
yosys-master
|
Data Structures | |
| struct | ProcessGenerator |
Variables | |
| bool | flag_dump_ast1 |
| bool | flag_dump_ast2 |
| bool | flag_dump_vlog |
| bool | flag_nolatches |
| bool | flag_nomem2reg |
| bool | flag_mem2reg |
| bool | flag_lib |
| bool | flag_noopt |
| bool | flag_icells |
| bool | flag_autowire |
| AstNode * | current_ast |
| AstNode * | current_ast_mod |
| std::map< std::string, AstNode * > | current_scope |
| const std::map< RTLIL::SigBit, RTLIL::SigBit > * | genRTLIL_subst_ptr = NULL |
| RTLIL::SigSpec | ignoreThisSignalsInInitial |
| AstNode * | current_top_block |
| AstNode * | current_block |
| AstNode * | current_block_child |
| AstModule * | current_module |
| AST::AstNode * AST_INTERNAL::current_ast |
| AST::AstNode * AST_INTERNAL::current_ast_mod |
| AST::AstNode * AST_INTERNAL::current_block |
| AST::AstNode * AST_INTERNAL::current_block_child |
| AST::AstModule * AST_INTERNAL::current_module |
| std::map< std::string, AST::AstNode * > AST_INTERNAL::current_scope |
| AST::AstNode * AST_INTERNAL::current_top_block |
| const std::map< RTLIL::SigBit, RTLIL::SigBit > * AST_INTERNAL::genRTLIL_subst_ptr = NULL |
| RTLIL::SigSpec AST_INTERNAL::ignoreThisSignalsInInitial |