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iopadmap.cc
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1 /*
2  * yosys -- Yosys Open SYnthesis Suite
3  *
4  * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5  *
6  * Permission to use, copy, modify, and/or distribute this software for any
7  * purpose with or without fee is hereby granted, provided that the above
8  * copyright notice and this permission notice appear in all copies.
9  *
10  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17  *
18  */
19 
20 #include "kernel/register.h"
21 #include "kernel/rtlil.h"
22 #include "kernel/log.h"
23 
24 USING_YOSYS_NAMESPACE
25 PRIVATE_NAMESPACE_BEGIN
26 
27 void split_portname_pair(std::string &port1, std::string &port2)
28 {
29  size_t pos = port1.find_first_of(':');
30  if (pos != std::string::npos) {
31  port2 = port1.substr(pos+1);
32  port1 = port1.substr(0, pos);
33  }
34 }
35 
36 struct IopadmapPass : public Pass {
37  IopadmapPass() : Pass("iopadmap", "technology mapping of i/o pads (or buffers)") { }
38  virtual void help()
39  {
40  log("\n");
41  log(" iopadmap [options] [selection]\n");
42  log("\n");
43  log("Map module inputs/outputs to PAD cells from a library. This pass\n");
44  log("can only map to very simple PAD cells. Use 'techmap' to further map\n");
45  log("the resulting cells to more sophisticated PAD cells.\n");
46  log("\n");
47  log(" -inpad <celltype> <portname>[:<portname>]\n");
48  log(" Map module input ports to the given cell type with\n");
49  log(" the given port name. if a 2nd portname is given, the\n");
50  log(" signal is passed through the pad call, using the 2nd\n");
51  log(" portname as output.\n");
52  log("\n");
53  log(" -outpad <celltype> <portname>[:<portname>]\n");
54  log(" -inoutpad <celltype> <portname>[:<portname>]\n");
55  log(" Similar to -inpad, but for output and inout ports.\n");
56  log("\n");
57  log(" -widthparam <param_name>\n");
58  log(" Use the specified parameter name to set the port width.\n");
59  log("\n");
60  log(" -nameparam <param_name>\n");
61  log(" Use the specified parameter to set the port name.\n");
62  log("\n");
63  log(" -bits\n");
64  log(" create individual bit-wide buffers even for ports that\n");
65  log(" are wider. (the default behavio is to create word-wide\n");
66  log(" buffers use -widthparam to set the word size on the cell.)\n");
67  log("\n");
68  }
69  virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
70  {
71  log_header("Executing IOPADMAP pass (mapping inputs/outputs to IO-PAD cells).\n");
72 
73  std::string inpad_celltype, inpad_portname, inpad_portname2;
74  std::string outpad_celltype, outpad_portname, outpad_portname2;
75  std::string inoutpad_celltype, inoutpad_portname, inoutpad_portname2;
76  std::string widthparam, nameparam;
77  bool flag_bits = false;
78 
79  size_t argidx;
80  for (argidx = 1; argidx < args.size(); argidx++)
81  {
82  std::string arg = args[argidx];
83  if (arg == "-inpad" && argidx+2 < args.size()) {
84  inpad_celltype = args[++argidx];
85  inpad_portname = args[++argidx];
86  split_portname_pair(inpad_portname, inpad_portname2);
87  continue;
88  }
89  if (arg == "-outpad" && argidx+2 < args.size()) {
90  outpad_celltype = args[++argidx];
91  outpad_portname = args[++argidx];
92  split_portname_pair(outpad_portname, outpad_portname2);
93  continue;
94  }
95  if (arg == "-inoutpad" && argidx+2 < args.size()) {
96  inoutpad_celltype = args[++argidx];
97  inoutpad_portname = args[++argidx];
98  split_portname_pair(inoutpad_portname, inoutpad_portname2);
99  continue;
100  }
101  if (arg == "-widthparam" && argidx+1 < args.size()) {
102  widthparam = args[++argidx];
103  continue;
104  }
105  if (arg == "-nameparam" && argidx+1 < args.size()) {
106  nameparam = args[++argidx];
107  continue;
108  }
109  if (arg == "-bits") {
110  flag_bits = true;
111  continue;
112  }
113  break;
114  }
115  extra_args(args, argidx, design);
116 
117  for (auto &it : design->modules_)
118  {
119  RTLIL::Module *module = it.second;
120 
121  if (!design->selected(module) || module->get_bool_attribute("\\blackbox"))
122  continue;
123 
124  for (auto &it2 : module->wires_)
125  {
126  RTLIL::Wire *wire = it2.second;
127 
128  if (!wire->port_id || !design->selected(module, wire))
129  continue;
130 
131  std::string celltype, portname, portname2;
132 
133  if (wire->port_input && !wire->port_output) {
134  if (inpad_celltype.empty()) {
135  log("Don't map input port %s.%s: Missing option -inpad.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name));
136  continue;
137  }
138  celltype = inpad_celltype;
139  portname = inpad_portname;
140  portname2 = inpad_portname2;
141  } else
142  if (!wire->port_input && wire->port_output) {
143  if (outpad_celltype.empty()) {
144  log("Don't map output port %s.%s: Missing option -outpad.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name));
145  continue;
146  }
147  celltype = outpad_celltype;
148  portname = outpad_portname;
149  portname2 = outpad_portname2;
150  } else
151  if (wire->port_input && wire->port_output) {
152  if (inoutpad_celltype.empty()) {
153  log("Don't map inout port %s.%s: Missing option -inoutpad.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name));
154  continue;
155  }
156  celltype = inoutpad_celltype;
157  portname = inoutpad_portname;
158  portname2 = inoutpad_portname2;
159  } else
160  log_abort();
161 
162  if (!flag_bits && wire->width != 1 && widthparam.empty()) {
163  log("Don't map multi-bit port %s.%s: Missing option -widthparam or -bits.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name));
164  continue;
165  }
166 
167  log("Mapping port %s.%s using %s.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name), celltype.c_str());
168 
169  RTLIL::Wire *new_wire = NULL;
170  if (!portname2.empty()) {
171  new_wire = module->addWire(NEW_ID, wire);
172  module->swap_names(new_wire, wire);
173  }
174 
175  if (flag_bits)
176  {
177  for (int i = 0; i < wire->width; i++)
178  {
179  RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(celltype));
180  cell->setPort(RTLIL::escape_id(portname), RTLIL::SigSpec(wire, i));
181  if (!portname2.empty())
182  cell->setPort(RTLIL::escape_id(portname2), RTLIL::SigSpec(new_wire, i));
183  if (!widthparam.empty())
184  cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(1);
185  if (!nameparam.empty())
186  cell->parameters[RTLIL::escape_id(nameparam)] = RTLIL::Const(stringf("%s[%d]", RTLIL::id2cstr(wire->name), i));
187  cell->attributes["\\keep"] = RTLIL::Const(1);
188  }
189  }
190  else
191  {
192  RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(celltype));
193  cell->setPort(RTLIL::escape_id(portname), RTLIL::SigSpec(wire));
194  if (!portname2.empty())
195  cell->setPort(RTLIL::escape_id(portname2), RTLIL::SigSpec(new_wire));
196  if (!widthparam.empty())
197  cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(wire->width);
198  if (!nameparam.empty())
199  cell->parameters[RTLIL::escape_id(nameparam)] = RTLIL::Const(RTLIL::id2cstr(wire->name));
200  cell->attributes["\\keep"] = RTLIL::Const(1);
201  }
202 
203  wire->port_id = 0;
204  wire->port_input = false;
205  wire->port_output = false;
206  }
207 
208  module->fixup_ports();
209  }
210  }
211 } IopadmapPass;
212 
213 PRIVATE_NAMESPACE_END
RTLIL::Design::selected
bool selected(T1 *module) const
Definition: rtlil.h:551
stringf
std::string stringf(const char *fmt,...)
Definition: yosys.cc:58
RTLIL::Module::addCell
RTLIL::Cell * addCell(RTLIL::IdString name, RTLIL::IdString type)
Definition: rtlil.cc:1353
log_header
void log_header(const char *format,...)
Definition: log.cc:188
RTLIL::Module::wires_
std::map< RTLIL::IdString, RTLIL::Wire * > wires_
Definition: rtlil.h:595
RTLIL::Cell::setPort
void setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
Definition: rtlil.cc:1789
RTLIL::Wire::port_input
bool port_input
Definition: rtlil.h:827
RTLIL::Wire::width
int width
Definition: rtlil.h:826
module
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Definition: abc.cc:94
RTLIL::Module::swap_names
void swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2)
Definition: rtlil.cc:1214
RTLIL::Wire::port_id
int port_id
Definition: rtlil.h:826
RTLIL::Cell::parameters
std::map< RTLIL::IdString, RTLIL::Const > parameters
Definition: rtlil.h:856
log_abort
#define log_abort()
Definition: log.h:84
RTLIL::escape_id
static std::string escape_id(std::string str)
Definition: rtlil.h:251
RTLIL::Wire::port_output
bool port_output
Definition: rtlil.h:827
split_portname_pair
USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN void split_portname_pair(std::string &port1, std::string &port2)
Definition: iopadmap.cc:27
PRIVATE_NAMESPACE_BEGIN
#define PRIVATE_NAMESPACE_BEGIN
Definition: yosys.h:97
IopadmapPass
IopadmapPass IopadmapPass
RTLIL::Module::fixup_ports
void fixup_ports()
Definition: rtlil.cc:1312
RTLIL::Module::addWire
RTLIL::Wire * addWire(RTLIL::IdString name, int width=1)
Definition: rtlil.cc:1331
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RTLIL::IdString name
Definition: rtlil.h:599
NEW_ID
#define NEW_ID
Definition: yosys.h:166
IopadmapPass::execute
virtual void execute(std::vector< std::string > args, RTLIL::Design *design)
Definition: iopadmap.cc:69
PRIVATE_NAMESPACE_END
#define PRIVATE_NAMESPACE_END
Definition: yosys.h:98
Pass
Definition: register.h:27
RTLIL::Wire::name
RTLIL::IdString name
Definition: rtlil.h:825
RTLIL::id2cstr
static const char * id2cstr(const RTLIL::IdString &str)
Definition: rtlil.h:267
USING_YOSYS_NAMESPACE
#define USING_YOSYS_NAMESPACE
Definition: yosys.h:102
RTLIL::Design::modules_
std::map< RTLIL::IdString, RTLIL::Module * > modules_
Definition: rtlil.h:507
NULL
#define NULL
Definition: NumberlikeArray.hh:6
log
void log(const char *format,...)
Definition: log.cc:180
IopadmapPass::help
virtual void help()
Definition: iopadmap.cc:38
Pass::extra_args
void extra_args(std::vector< std::string > args, size_t argidx, RTLIL::Design *design, bool select=true)
Definition: register.cc:128