torc-master
 All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Friends Macros Pages
VirtexBitstreamUnitTest.cpp
Go to the documentation of this file.
1 // Torc - Copyright 2011-2013 University of Southern California. All Rights Reserved.
2 // $HeadURL$
3 // $Id$
4 
5 // This program is free software: you can redistribute it and/or modify it under the terms of the
6 // GNU General Public License as published by the Free Software Foundation, either version 3 of the
7 // License, or (at your option) any later version.
8 //
9 // This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
10 // without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
11 // the GNU General Public License for more details.
12 //
13 // You should have received a copy of the GNU General Public License along with this program. If
14 // not, see <http://www.gnu.org/licenses/>.
15 
16 /// \file
17 /// \brief Unit test for the VirtexBitstream class.
18 
19 #include <boost/test/unit_test.hpp>
20 #include "torc/bitstream/VirtexBitstream.hpp"
21 #include "torc/bitstream/Virtex5.hpp"
22 #include "torc/bitstream/TestHelpers.hpp"
23 #include "torc/common/DirectoryTree.hpp"
24 #include "torc/common/DeviceDesignator.hpp"
25 #include "torc/bitstream/OutputStreamHelpers.hpp"
26 #include "torc/common/TestHelpers.hpp"
27 #include <fstream>
28 #include <iostream>
29 
30 /// \todo Remove this #include
31 #include "torc/bitstream/Virtex.hpp"
32 #include "torc/bitstream/VirtexE.hpp"
33 #include "torc/bitstream/Virtex2.hpp"
34 #include "torc/bitstream/Virtex2P.hpp"
35 #include "torc/bitstream/Virtex4.hpp"
36 #include "torc/bitstream/Virtex5.hpp"
37 #include "torc/bitstream/Virtex6.hpp"
38 #include "torc/bitstream/Virtex7.hpp"
39 
40 namespace torc {
41 namespace bitstream {
42 
43 BOOST_AUTO_TEST_SUITE(bitstream)
44 
45 /// \brief Unit test for the VirtexBitstream class CRC calculation.
46 BOOST_AUTO_TEST_CASE(VirtexBitstreamCrcUnitTest) {
47  // check the CRC generation
48  boost::filesystem::path regressionPath = torc::common::DirectoryTree::getExecutablePath()
49  / "torc" / "bitstream";
50  BOOST_CHECK(checkCRC<Virtex>(regressionPath / "VirtexUnitTest.reference.bit"));
51  BOOST_CHECK(checkCRC<VirtexE>(regressionPath / "VirtexEUnitTest.reference.bit"));
52  BOOST_CHECK(checkCRC<Virtex2>(regressionPath / "Virtex2UnitTest.reference.bit"));
53  BOOST_CHECK(checkCRC<Virtex2P>(regressionPath / "Virtex2PUnitTest.reference.bit"));
54  BOOST_CHECK(checkCRC<Virtex4>(regressionPath / "Virtex4UnitTest.reference.bit"));
55  BOOST_CHECK(checkCRC<Virtex5>(regressionPath / "Virtex5UnitTest.reference.bit"));
56  BOOST_CHECK(checkCRC<Virtex6>(regressionPath / "Virtex6UnitTest.reference.bit"));
57  BOOST_CHECK(checkCRC<Virtex7>(regressionPath / "Virtex7UnitTest.reference.bit"));
58 }
59 
60 /// \brief Unit test for the VirtexBitstream class.
61 BOOST_AUTO_TEST_CASE(VirtexBitstreamUnitTest) {
62 
63  // build the file paths
64  boost::filesystem::path referencePath = torc::common::DirectoryTree::getExecutablePath()
65  / "torc" / "bitstream" / "Virtex5UnitTest.reference.bit";
66  boost::filesystem::path generatedPath = torc::common::DirectoryTree::getExecutablePath()
67  / "regression" / "VirtexBitstreamUnitTest.generated.bit";
68 
69  // read the reference bitstream
70  std::fstream fileStream1(referencePath.string().c_str(), std::ios::binary | std::ios::in);
71  BOOST_REQUIRE(fileStream1.good());
72  Virtex5 bitstream1;
73  bitstream1.read(fileStream1, false);
74  // find the type 2 write packet
75  VirtexPacket frameContents;
76  Virtex5::const_iterator p = bitstream1.begin();
77  Virtex5::const_iterator e = bitstream1.end();
78  while(p < e) {
79  if(p->isType2() && p->isWrite()) { frameContents = *p; break; }
80  p++;
81  }
82 
83  // declare a bitstream of unspecified architectures
84  VirtexBitstream bitstream;
85  // prepare the bitstream header
86  bitstream.setDesignName("Virtex5UnitTest.reference.ncd;UserID=0xFFFFFFFF");
87  bitstream.setDeviceName("5vlx20tff323");
88  bitstream.setDesignDate("2010/10/08");
89  bitstream.setDesignTime("15:06:11");
90 
91  // construct and add packets to the bitstream
92  VirtexPacket dummy(Virtex5::eSynchronizationDummy);
93  VirtexPacket nop(VirtexPacket::makeHeader(Virtex5::ePacketType1, Virtex5::eOpcodeNOP,
94  0, 0));
95  // dummy words
96  bitstream.insert(bitstream.end(), 8, dummy);
97  // bus width detect
98  bitstream.push_back(VirtexPacket(Virtex5::eSynchronizationBusWidthSync));
99  bitstream.push_back(VirtexPacket(Virtex5::eSynchronizationBusWidthDetect));
100  bitstream.push_back(dummy);
101  bitstream.push_back(dummy);
102  // sync
103  bitstream.push_back(VirtexPacket(Virtex5::eSynchronizationSync));
104  bitstream.push_back(nop);
105  // warm boot register
106  bitstream.push_back(VirtexPacket::makeType1Write(Virtex5::eRegisterWBSTAR, 0));
107  // NULL command
108  bitstream.push_back(VirtexPacket::makeType1Write(Virtex5::eRegisterCMD, Virtex5::eCommandNULL));
109  bitstream.push_back(nop);
110  // reset CRC command
111  bitstream.push_back(VirtexPacket::makeType1Write(Virtex5::eRegisterCMD, Virtex5::eCommandRCRC));
112  bitstream.push_back(nop);
113  bitstream.push_back(nop);
114  // watchdog timer
115  bitstream.push_back(VirtexPacket::makeType1Write(Virtex5::eRegisterTIMER, 0));
116  // undocumented register 19
117  bitstream.push_back(VirtexPacket::makeType1Write(19, 0));
118  // configuration options register 0
119  bitstream.push_back(VirtexPacket::makeType1Write(Virtex5::eRegisterCOR0,
120  Virtex5::makeSubfield(Virtex5::eRegisterCOR0, "CRC", "Enable") |
121  Virtex5::makeSubfield(Virtex5::eRegisterCOR0, "DONE_status", "DonePin") |
122  Virtex5::makeSubfield(Virtex5::eRegisterCOR0, "DonePipe", "No") |
123  Virtex5::makeSubfield(Virtex5::eRegisterCOR0, "DriveDone", "No") |
124  Virtex5::makeSubfield(Virtex5::eRegisterCOR0, "Capture", "Continuous") |
125  Virtex5::makeSubfield(Virtex5::eRegisterCOR0, "ConfigRate", "[UNKNOWN 0]") |
126  Virtex5::makeSubfield(Virtex5::eRegisterCOR0, "StartupClk", "Cclk") |
127  Virtex5::makeSubfield(Virtex5::eRegisterCOR0, "DONE_cycle", "4") |
128  Virtex5::makeSubfield(Virtex5::eRegisterCOR0, "Match_cycle", "NoWait") |
129  Virtex5::makeSubfield(Virtex5::eRegisterCOR0, "LCK_cycle", "NoWait") |
130  Virtex5::makeSubfield(Virtex5::eRegisterCOR0, "GTS_cycle", "5") |
131  Virtex5::makeSubfield(Virtex5::eRegisterCOR0, "GWE_cycle", "6") |
132  0));
133  // configuration options register 1
134  bitstream.push_back(VirtexPacket::makeType1Write(Virtex5::eRegisterCOR1,
135  Virtex5::makeSubfield(Virtex5::eRegisterCOR1, "PersistDeassertAtDesynch", "Disabled") |
136  Virtex5::makeSubfield(Virtex5::eRegisterCOR1, "InitAsCRCErrorPin", "Disabled") |
137  Virtex5::makeSubfield(Virtex5::eRegisterCOR1, "ContinuousReadbackCRC", "Disabled") |
138  Virtex5::makeSubfield(Virtex5::eRegisterCOR1, "BPI_1st_read_cycle", "1") |
139  Virtex5::makeSubfield(Virtex5::eRegisterCOR1, "BPI_page_size", "1") |
140  0));
141  // write the ID code
142  bitstream.push_back(VirtexPacket::makeType1Write(Virtex5::eRegisterIDCODE, 0x02a56093));
143  // clock and rate switch command
144  bitstream.push_back(VirtexPacket::makeType1Write(Virtex5::eRegisterCMD,
145  Virtex5::eCommandSWITCH));
146  bitstream.push_back(nop);
147  // control register 0 mask
148  bitstream.push_back(VirtexPacket::makeType1Write(Virtex5::eRegisterMASK,
149  Virtex5::makeSubfield(Virtex5::eRegisterMASK, "ICAP_sel", "Protected") |
150  Virtex5::makeSubfield(Virtex5::eRegisterMASK, "OverTempPowerDown", "Protected") |
151  Virtex5::makeSubfield(Virtex5::eRegisterMASK, "GLUTMASK", "Protected") |
152  Virtex5::makeSubfield(Virtex5::eRegisterMASK, "Encrypt", "Protected") |
153  Virtex5::makeSubfield(Virtex5::eRegisterMASK, "Security", "Protected") |
154  Virtex5::makeSubfield(Virtex5::eRegisterMASK, "Persist", "Protected") |
155  Virtex5::makeSubfield(Virtex5::eRegisterMASK, "GTS_USER_B", "Protected") |
156  0x00400000 | // no documentation available for this subfield
157  0));
158  // control register 0
159  bitstream.push_back(VirtexPacket::makeType1Write(Virtex5::eRegisterCTL0,
160  Virtex5::makeSubfield(Virtex5::eRegisterCTL0, "ICAP_sel", "Top") |
161  Virtex5::makeSubfield(Virtex5::eRegisterCTL0, "OverTempPowerDown", "Disable") |
162  Virtex5::makeSubfield(Virtex5::eRegisterCTL0, "GLUTMASK", "Masked") |
163  Virtex5::makeSubfield(Virtex5::eRegisterCTL0, "Encrypt", "No") |
164  Virtex5::makeSubfield(Virtex5::eRegisterCTL0, "Security", "None") |
165  Virtex5::makeSubfield(Virtex5::eRegisterCTL0, "Persist", "No") |
166  Virtex5::makeSubfield(Virtex5::eRegisterCTL0, "GTS_USER_B", "IoDisabled") |
167  0x00400000 | // no documentation available for this subfield
168  0));
169  // control register 1 mask
170  bitstream.push_back(VirtexPacket::makeType1Write(Virtex5::eRegisterMASK, 0));
171  // control register 1
172  bitstream.push_back(VirtexPacket::makeType1Write(Virtex5::eRegisterCTL1, 0));
173  // more NOPs
174  bitstream.insert(bitstream.end(), 8, nop);
175  // frame address register
176  bitstream.push_back(VirtexPacket::makeType1Write(Virtex5::eRegisterFAR, 0));
177  // enable configuration write command
178  bitstream.push_back(VirtexPacket::makeType1Write(Virtex5::eRegisterCMD, Virtex5::eCommandWCFG));
179  bitstream.push_back(nop);
180  // write 0 bytes to FDRI (in preparation for type 2 write packet)
181  bitstream.push_back(VirtexPacket::makeNullType1Write(Virtex5::eRegisterFDRI));
182  // write 0 bytes to FDRI (in preparation for type 2 write packet)
183 // // note that we do not release the buffer as it will be taken over by the packet
184 // size_t length = 0x0002fa06;
185 // uint32_t* buffer = new uint32_t[length];
186 // uint32_t* ptr = buffer + length - 1;
187 // while(ptr >= buffer) *ptr-- = 0;
188 // bitstream.push_back(VirtexPacket::makeType2Write(0x0002fa06, buffer));
189  bitstream.push_back(frameContents);
190  // write the CRC value
191  bitstream.push_back(VirtexPacket::makeType1Write(Virtex5::eRegisterCRC, 0x2d63e9d));
192  // restore command
193  bitstream.push_back(VirtexPacket::makeType1Write(Virtex5::eRegisterCMD,
194  Virtex5::eCommandGRESTORE));
195  bitstream.push_back(nop);
196  // last frame command
197  bitstream.push_back(VirtexPacket::makeType1Write(Virtex5::eRegisterCMD,
198  Virtex5::eCommandLFRM));
199  bitstream.insert(bitstream.end(), 100, nop);
200  // another restore command
201  bitstream.push_back(VirtexPacket::makeType1Write(Virtex5::eRegisterCMD,
202  Virtex5::eCommandGRESTORE));
203  bitstream.insert(bitstream.end(), 30, nop);
204  // start command
205  bitstream.push_back(VirtexPacket::makeType1Write(Virtex5::eRegisterCMD,
206  Virtex5::eCommandSTART));
207  bitstream.push_back(nop);
208  // frame address register
209  bitstream.push_back(VirtexPacket::makeType1Write(Virtex5::eRegisterFAR, 0x00ef8000));
210  // control register 0 mask
211  bitstream.push_back(VirtexPacket::makeType1Write(Virtex5::eRegisterMASK,
212  Virtex5::makeSubfield(Virtex5::eRegisterMASK, "ICAP_sel", "Protected") |
213  Virtex5::makeSubfield(Virtex5::eRegisterMASK, "OverTempPowerDown", "Protected") |
214  Virtex5::makeSubfield(Virtex5::eRegisterMASK, "GLUTMASK", "Protected") |
215  Virtex5::makeSubfield(Virtex5::eRegisterMASK, "Encrypt", "Protected") |
216  Virtex5::makeSubfield(Virtex5::eRegisterMASK, "Security", "Protected") |
217  Virtex5::makeSubfield(Virtex5::eRegisterMASK, "Persist", "Protected") |
218  Virtex5::makeSubfield(Virtex5::eRegisterMASK, "GTS_USER_B", "Protected") |
219  0x00400000 | // no documentation available for this subfield
220  0));
221  // control register 0
222  bitstream.push_back(VirtexPacket::makeType1Write(Virtex5::eRegisterCTL0,
223  Virtex5::makeSubfield(Virtex5::eRegisterCTL0, "ICAP_sel", "Top") |
224  Virtex5::makeSubfield(Virtex5::eRegisterCTL0, "OverTempPowerDown", "Disable") |
225  Virtex5::makeSubfield(Virtex5::eRegisterCTL0, "GLUTMASK", "Masked") |
226  Virtex5::makeSubfield(Virtex5::eRegisterCTL0, "Encrypt", "No") |
227  Virtex5::makeSubfield(Virtex5::eRegisterCTL0, "Security", "None") |
228  Virtex5::makeSubfield(Virtex5::eRegisterCTL0, "Persist", "No") |
229  Virtex5::makeSubfield(Virtex5::eRegisterCTL0, "GTS_USER_B", "IoDisabled") |
230  0x00400000 | // no documentation available for this subfield
231  0));
232  // write the CRC value
233  bitstream.push_back(VirtexPacket::makeType1Write(Virtex5::eRegisterCRC, 0x0c90449e));
234  // desynch command
235  bitstream.push_back(VirtexPacket::makeType1Write(Virtex5::eRegisterCMD,
236  Virtex5::eCommandDESYNCH));
237  bitstream.insert(bitstream.end(), 61, nop);
238 
239  // write the bitstream back out
240  std::fstream outputStream(generatedPath.string().c_str(), std::ios::binary | std::ios::out);
241  BOOST_REQUIRE(outputStream.good());
242  bitstream.write(outputStream);
243  outputStream.flush();
244 
245  /* read the bitstream
246  std::fstream fileStream2(generatedPath.string().c_str(), std::ios::binary | std::ios::in);
247  BOOST_REQUIRE(fileStream2.good());
248  Virtex5 bitstream2;
249  bitstream2.read(fileStream2, false);
250  // write the bitstream digest to the console
251  std::cout << bitstream2 << std::endl;
252  */
253  // compare the reference and generated XDL
254  BOOST_CHECK(torc::common::fileContentsAreEqual(generatedPath, referencePath));
255 
256 }
257 
258 BOOST_AUTO_TEST_SUITE_END()
259 
260 } // namespace bitstream
261 } // namespace torc
262 
263 /*
264 Design Virtex5UnitTest.reference.ncd;UserID=0xFFFFFFFF (5vlx20tff323) @ 2010/10/08 15:06:11: 781400 bytes (195350 words)
265  00000070: DUMMY
266  00000074: DUMMY
267  00000078: DUMMY
268  0000007c: DUMMY
269  00000080: DUMMY
270  00000084: DUMMY
271  00000088: DUMMY
272  0000008c: DUMMY
273  00000090: BUS WIDTH SYNC
274  00000094: BUS WIDTH DETECT
275  00000098: DUMMY
276  0000009c: DUMMY
277  000000a0: SYNC
278  000000a4: NOP x 1
279  000000a8: TYPE1 WRITE WBSTAR: 00000000 (RevisionSelectTristate:Disabled, NextRevisionSelect:00)
280  000000b0: TYPE1 WRITE CMD NULL
281  000000b8: NOP x 1
282  000000bc: TYPE1 WRITE CMD RCRC
283  000000c4: NOP x 2
284  000000cc: TYPE1 WRITE TIMER: 00000000 (TimerForUser:Disabled, TimerForConfig:Disabled)
285  000000d4: TYPE1 WRITE [UNKNOWN REG 19]: 00000000
286  000000dc: TYPE1 WRITE COR0: 00003fe5 (CRC:Enable, DONE_status:DonePin, DonePipe:No, DriveDone:No, Capture:Continuous, ConfigRate:[UNKNOWN 0], StartupClk:Cclk, DONE_cycle:4, Match_cycle:NoWait, LCK_cycle:NoWait, GTS_cycle:5, GWE_cycle:6)
287  000000e4: TYPE1 WRITE COR1: 00000000 (PersistDeassertAtDesynch:Disabled, InitAsCRCErrorPin:Disabled, ContinuousReadbackCRC:Disabled, BPI_1st_read_cycle:1, BPI_page_size:1)
288  000000ec: TYPE1 WRITE IDCODE: 02a56093
289  000000f4: TYPE1 WRITE CMD SWITCH
290  000000fc: NOP x 1
291  00000100: TYPE1 WRITE MASK: 00400000 (ICAP_sel:Protected, OverTempPowerDown:Protected, GLUTMASK:Protected, Encrypt:Protected, Security:Protected, Persist:Protected, GTS_USER_B:Protected)
292  00000108: TYPE1 WRITE CTL0: 00400000 (ICAP_sel:Top, OverTempPowerDown:Disable, GLUTMASK:Masked, Encrypt:No, Security:None, Persist:No, GTS_USER_B:IoDisabled)
293  00000110: TYPE1 WRITE MASK: 00000000 ()
294  00000118: TYPE1 WRITE CTL1: 00000000 ()
295  00000120: NOP x 8
296  00000140: TYPE1 WRITE FAR: 00000000
297  00000148: TYPE1 WRITE CMD WCFG
298  00000150: NOP x 1
299  00000154: TYPE1 WRITE FDRI: 00000000 words
300  00000158: TYPE2 WRITE FDRI: 0002fa06 words
301  000be974: TYPE1 WRITE CRC: 02d63e9d
302  000be97c: TYPE1 WRITE CMD GRESTORE
303  000be984: NOP x 1
304  000be988: TYPE1 WRITE CMD DGHIGH/LFRM
305  000be990: NOP x 100
306  000beb20: TYPE1 WRITE CMD GRESTORE
307  000beb28: NOP x 30
308  000beba0: TYPE1 WRITE CMD START
309  000beba8: NOP x 1
310  000bebac: TYPE1 WRITE FAR: 00ef8000
311  000bebb4: TYPE1 WRITE MASK: 00400000 (ICAP_sel:Protected, OverTempPowerDown:Protected, GLUTMASK:Protected, Encrypt:Protected, Security:Protected, Persist:Protected, GTS_USER_B:Protected)
312  000bebbc: TYPE1 WRITE CTL0: 00400000 (ICAP_sel:Top, OverTempPowerDown:Disable, GLUTMASK:Masked, Encrypt:No, Security:None, Persist:No, GTS_USER_B:IoDisabled)
313  000bebc4: TYPE1 WRITE CRC: 0c90449e
314  000bebcc: TYPE1 WRITE CMD DESYNCH
315  000bebd4: NOP x 61
316 */
torc::bitstream::Bitstream::setDesignTime
void setDesignTime(const string &inDesignTime)
Set the design time.
Definition: bitstream/Bitstream.hpp:329
OutputStreamHelpers.hpp
Header for torc::bitstream output stream helpers.
torc::bitstream::VirtexBitstream
Virtex-class bitstream.
Definition: VirtexBitstream.hpp:35
torc::bitstream::Virtex5::makeSubfield
static uint32_t makeSubfield(ERegister inRegister, const std::string &inSubfield, const std::string &inSetting)
Return the masked value for a subfield of the specified register.
Definition: Virtex5.cpp:355
VirtexE.hpp
Header for the VirtexE class.
VirtexBitstream.hpp
Header for the VirtexBitstream class.
Virtex4.hpp
Header for the Virtex4 class.
Virtex2P.hpp
Header for the Virtex2P class.
DirectoryTree.hpp
Header for the DirectoryTree class.
torc::bitstream::VirtexPacket::makeNullType1Write
static VirtexPacket makeNullType1Write(uint32_t inAddress)
Construct a null type 1 write packet.
Definition: VirtexPacket.hpp:188
Virtex6.hpp
Header for the Virtex6 class.
Virtex5.hpp
Header for the Virtex5 class.
DeviceDesignator.hpp
Header for the DeviceDesignator class.
TestHelpers.hpp
Header for Boost.Test helper functions.
torc::bitstream::VirtexBitstream::insert
iterator insert(iterator position, const value_type &val)
Regular std::vector inserter.
Definition: VirtexBitstream.hpp:116
TestHelpers.hpp
Header for Boost.Test helper functions.
torc::bitstream::Virtex5
Virtex5 bitstream.
Definition: Virtex5.hpp:41
torc::bitstream::Bitstream::setDesignName
void setDesignName(const string &inDesignName)
Set the design name.
Definition: bitstream/Bitstream.hpp:323
torc::bitstream::Bitstream::setDesignDate
void setDesignDate(const string &inDesignDate)
Set the design date.
Definition: bitstream/Bitstream.hpp:327
torc::bitstream::path
boost::filesystem::path path
Definition: LibGenFactory.hpp:36
torc::bitstream::VirtexPacket::makeType1Write
static VirtexPacket makeType1Write(uint32_t inAddress, uint32_t inWord)
Construct a type 1 write packet.
Definition: VirtexPacket.hpp:192
Virtex.hpp
Header for the Virtex class.
torc::bitstream::Bitstream::write
void write(std::ostream &inStream, uint8_t inVal)
Write a uint8_t to the stream.
Definition: bitstream/Bitstream.hpp:67
Virtex2.hpp
Header for the Virtex2 class.
torc::common::fileContentsAreEqual
bool fileContentsAreEqual(const boost::filesystem::path &inA, const boost::filesystem::path &inB)
Compare the raw contents of two files to determine whether they are identical.
Definition: common/TestHelpers.cpp:43
torc::bitstream::VirtexPacket
Bitstream packet for Virtex class architectures.
Definition: VirtexPacket.hpp:76
torc::bitstream::VirtexPacket::makeHeader
static uint32_t makeHeader(EPacketType inType, EOpcode inOpcode, uint32_t inAddress, uint32_t inCount)
Construct a packet header.
Definition: VirtexPacket.hpp:215
torc::bitstream::BOOST_AUTO_TEST_CASE
BOOST_AUTO_TEST_CASE(hexCharacterToDec)
Definition: Virtex5AssemblerUnitTest.cpp:31
torc::bitstream::Bitstream::read
virtual void read(std::istream &inStream, bool inCleanDateAndTime=true)
Read the bitstream header and packets from a stream.
Definition: bitstream/Bitstream.hpp:266
torc::bitstream::Bitstream::setDeviceName
void setDeviceName(const string &inDeviceName)
Set the device name.
Definition: bitstream/Bitstream.hpp:325
torc::common::DirectoryTree::getExecutablePath
static const boost::filesystem::path & getExecutablePath(void)
Returns the absolute path to the executable directory.
Definition: DirectoryTree.hpp:58
Virtex7.hpp
Header for the Virtex7 class.