yosys-master
|
Data Fields | |
RTLIL::SigBit | bit_d |
RTLIL::SigBit | bit_clk |
RTLIL::SigBit | bit_arst |
bool | clk_polarity |
bool | arst_polarity |
RTLIL::State | arst_value |
RTLIL::Cell * | cell |
RTLIL::State dff_map_bit_info_t::arst_value |
RTLIL::SigBit dff_map_bit_info_t::bit_arst |
RTLIL::SigBit dff_map_bit_info_t::bit_clk |
RTLIL::SigBit dff_map_bit_info_t::bit_d |
RTLIL::Cell* dff_map_bit_info_t::cell |