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add.cc File Reference
#include "kernel/yosys.h"
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Data Structures

struct  AddPass
 

Functions

USING_YOSYS_NAMESPACE static
PRIVATE_NAMESPACE_BEGIN void 		add_wire (RTLIL::Design *design, RTLIL::Module *module, std::string name, int width, bool flag_input, bool flag_output, bool flag_global)
 

Variables

AddPass AddPass
 

Function Documentation

USING_YOSYS_NAMESPACE static PRIVATE_NAMESPACE_BEGIN void add_wire ( RTLIL::Design *  design,
RTLIL::Module *  module,
std::string  name,
int  width,
bool  flag_input,
bool  flag_output,
bool  flag_global 
)
static

Definition at line 25 of file add.cc.

26 {
27  RTLIL::Wire *wire = NULL;
28  name = RTLIL::escape_id(name);
29 
30  if (module->count_id(name) != 0)
31  {
32  if (module->wires_.count(name) > 0)
33  wire = module->wires_.at(name);
34 
35  if (wire != NULL && wire->width != width)
36  wire = NULL;
37 
38  if (wire != NULL && wire->port_input != flag_input)
39  wire = NULL;
40 
41  if (wire != NULL && wire->port_output != flag_output)
42  wire = NULL;
43 
44  if (wire == NULL)
45  log_cmd_error("Found incompatible object with same name in module %s!\n", module->name.c_str());
46 
47  log("Module %s already has such an object.\n", module->name.c_str());
48  }
49  else
50  {
51  wire = module->addWire(name, width);
52  wire->port_input = flag_input;
53  wire->port_output = flag_output;
54 
55  if (flag_input || flag_output) {
56  wire->port_id = module->wires_.size();
57  module->fixup_ports();
58  }
59 
60  log("Added wire %s to module %s.\n", name.c_str(), module->name.c_str());
61  }
62 
63  if (!flag_global)
64  return;
65 
66  for (auto &it : module->cells_)
67  {
68  if (design->modules_.count(it.second->type) == 0)
69  continue;
70 
71  RTLIL::Module *mod = design->modules_.at(it.second->type);
72  if (!design->selected_whole_module(mod->name))
73  continue;
74  if (mod->get_bool_attribute("\\blackbox"))
75  continue;
76  if (it.second->hasPort(name))
77  continue;
78 
79  it.second->setPort(name, wire);
80  log("Added connection %s to cell %s.%s (%s).\n", name.c_str(), module->name.c_str(), it.first.c_str(), it.second->type.c_str());
81  }
82 }
RTLIL::IdString::c_str
const char * c_str() const
Definition: rtlil.h:178
RTLIL::Module::wires_
std::map< RTLIL::IdString, RTLIL::Wire * > wires_
Definition: rtlil.h:595
RTLIL::Wire::port_input
bool port_input
Definition: rtlil.h:827
RTLIL::Wire::width
int width
Definition: rtlil.h:826
RTLIL::Wire::port_id
int port_id
Definition: rtlil.h:826
RTLIL::escape_id
static std::string escape_id(std::string str)
Definition: rtlil.h:251
RTLIL::Wire::port_output
bool port_output
Definition: rtlil.h:827
RTLIL::Module::fixup_ports
void fixup_ports()
Definition: rtlil.cc:1312
RTLIL::Module::addWire
RTLIL::Wire * addWire(RTLIL::IdString name, int width=1)
Definition: rtlil.cc:1331
RTLIL::Module::name
RTLIL::IdString name
Definition: rtlil.h:599
RTLIL::Design::selected_whole_module
bool selected_whole_module(RTLIL::IdString mod_name) const
Definition: rtlil.cc:388
log_cmd_error
void log_cmd_error(const char *format,...)
Definition: log.cc:211
RTLIL::Module::count_id
virtual size_t count_id(RTLIL::IdString id)
Definition: rtlil.cc:472
RTLIL::Design::modules_
std::map< RTLIL::IdString, RTLIL::Module * > modules_
Definition: rtlil.h:507
NULL
#define NULL
Definition: NumberlikeArray.hh:6
RTLIL::Module::cells_
std::map< RTLIL::IdString, RTLIL::Cell * > cells_
Definition: rtlil.h:596
log
void log(const char *format,...)
Definition: log.cc:180

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Variable Documentation

AddPass AddPass