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calc.cc File Reference
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Functions

static YOSYS_NAMESPACE_BEGIN void extend_u0 (RTLIL::Const &arg, int width, bool is_signed)
 
static BigInteger const2big (const RTLIL::Const &val, bool as_signed, int &undef_bit_pos)
 
static RTLIL::Const big2const (const BigInteger &val, int result_len, int undef_bit_pos)
 
static RTLIL::State logic_and (RTLIL::State a, RTLIL::State b)
 
static RTLIL::State logic_or (RTLIL::State a, RTLIL::State b)
 
static RTLIL::State logic_xor (RTLIL::State a, RTLIL::State b)
 
static RTLIL::State logic_xnor (RTLIL::State a, RTLIL::State b)
 
static RTLIL::Const logic_wrapper (RTLIL::State(*logic_func)(RTLIL::State, RTLIL::State), RTLIL::Const arg1, RTLIL::Const arg2, bool signed1, bool signed2, int result_len=-1)
 
static RTLIL::Const logic_reduce_wrapper (RTLIL::State initial, RTLIL::State(*logic_func)(RTLIL::State, RTLIL::State), const RTLIL::Const &arg1, int result_len)
 
static RTLIL::Const const_shift_worker (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool sign_ext, int direction, int result_len)
 
static RTLIL::Const const_shift_shiftx (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool, bool signed2, int result_len, RTLIL::State other_bits)
 

Function Documentation

static RTLIL::Const big2const ( const BigInteger val,
int  result_len,
int  undef_bit_pos 
)
static

Definition at line 61 of file calc.cc.

62 {
63  if (undef_bit_pos >= 0)
64  return RTLIL::Const(RTLIL::State::Sx, result_len);
65 
66  BigUnsigned mag = val.getMagnitude();
67  RTLIL::Const result(0, result_len);
68 
69  if (!mag.isZero())
70  {
71  if (val.getSign() < 0)
72  {
73  mag--;
74  for (int i = 0; i < result_len; i++)
75  result.bits[i] = mag.getBit(i) ? RTLIL::State::S0 : RTLIL::State::S1;
76  }
77  else
78  {
79  for (int i = 0; i < result_len; i++)
80  result.bits[i] = mag.getBit(i) ? RTLIL::State::S1 : RTLIL::State::S0;
81  }
82  }
83 
84 #if 0
85  if (undef_bit_pos >= 0)
86  for (int i = undef_bit_pos; i < result_len; i++)
87  result.bits[i] = RTLIL::State::Sx;
88 #endif
89 
90  return result;
91 }
const BigUnsigned & getMagnitude() const
Definition: BigInteger.hh:83
bool isZero() const
Definition: BigUnsigned.hh:97
Sign getSign() const
Definition: BigInteger.hh:80
bool getBit(Index bi) const
Definition: BigUnsigned.hh:105

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static BigInteger const2big ( const RTLIL::Const val,
bool  as_signed,
int &  undef_bit_pos 
)
static

Definition at line 42 of file calc.cc.

43 {
44  BigInteger result = 0, this_bit = 1;
45  for (size_t i = 0; i < val.bits.size(); i++) {
46  if (val.bits[i] == RTLIL::State::S1) {
47  if (as_signed && i+1 == val.bits.size())
48  result -= this_bit;
49  else
50  result += this_bit;
51  }
52  else if (val.bits[i] != RTLIL::State::S0) {
53  if (undef_bit_pos < 0)
54  undef_bit_pos = i;
55  }
56  this_bit *= 2;
57  }
58  return result;
59 }
std::vector< RTLIL::State > bits
Definition: rtlil.h:438

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static RTLIL::Const const_shift_shiftx ( const RTLIL::Const arg1,
const RTLIL::Const arg2,
bool  ,
bool  signed2,
int  result_len,
RTLIL::State  other_bits 
)
static

Definition at line 324 of file calc.cc.

325 {
326  int undef_bit_pos = -1;
327  BigInteger offset = const2big(arg2, signed2, undef_bit_pos);
328 
329  if (result_len < 0)
330  result_len = arg1.bits.size();
331 
332  RTLIL::Const result(RTLIL::State::Sx, result_len);
333  if (undef_bit_pos >= 0)
334  return result;
335 
336  for (int i = 0; i < result_len; i++) {
337  BigInteger pos = BigInteger(i) + offset;
338  if (pos < 0 || pos >= arg1.bits.size())
339  result.bits[i] = other_bits;
340  else
341  result.bits[i] = arg1.bits[pos.toInt()];
342  }
343 
344  return result;
345 }
static BigInteger const2big(const RTLIL::Const &val, bool as_signed, int &undef_bit_pos)
Definition: calc.cc:42
int toInt() const
Definition: BigInteger.cc:131
std::vector< RTLIL::State > bits
Definition: rtlil.h:438

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static RTLIL::Const const_shift_worker ( const RTLIL::Const arg1,
const RTLIL::Const arg2,
bool  sign_ext,
int  direction,
int  result_len 
)
static

Definition at line 271 of file calc.cc.

272 {
273  int undef_bit_pos = -1;
274  BigInteger offset = const2big(arg2, false, undef_bit_pos) * direction;
275 
276  if (result_len < 0)
277  result_len = arg1.bits.size();
278 
279  RTLIL::Const result(RTLIL::State::Sx, result_len);
280  if (undef_bit_pos >= 0)
281  return result;
282 
283  for (int i = 0; i < result_len; i++) {
284  BigInteger pos = BigInteger(i) + offset;
285  if (pos < 0)
286  result.bits[i] = RTLIL::State::S0;
287  else if (pos >= arg1.bits.size())
288  result.bits[i] = sign_ext ? arg1.bits.back() : RTLIL::State::S0;
289  else
290  result.bits[i] = arg1.bits[pos.toInt()];
291  }
292 
293  return result;
294 }
static BigInteger const2big(const RTLIL::Const &val, bool as_signed, int &undef_bit_pos)
Definition: calc.cc:42
int toInt() const
Definition: BigInteger.cc:131
std::vector< RTLIL::State > bits
Definition: rtlil.h:438

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static YOSYS_NAMESPACE_BEGIN void extend_u0 ( RTLIL::Const arg,
int  width,
bool  is_signed 
)
static

Definition at line 29 of file calc.cc.

30 {
32 
33  if (arg.bits.size() > 0 && is_signed)
34  padding = arg.bits.back();
35 
36  while (int(arg.bits.size()) < width)
37  arg.bits.push_back(padding);
38 
39  arg.bits.resize(width);
40 }
std::vector< RTLIL::State > bits
Definition: rtlil.h:438
State
Definition: rtlil.h:29

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static RTLIL::State logic_and ( RTLIL::State  a,
RTLIL::State  b 
)
static

Definition at line 93 of file calc.cc.

94 {
95  if (a == RTLIL::State::S0) return RTLIL::State::S0;
96  if (b == RTLIL::State::S0) return RTLIL::State::S0;
97  if (a != RTLIL::State::S1) return RTLIL::State::Sx;
98  if (b != RTLIL::State::S1) return RTLIL::State::Sx;
99  return RTLIL::State::S1;
100 }

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static RTLIL::State logic_or ( RTLIL::State  a,
RTLIL::State  b 
)
static

Definition at line 102 of file calc.cc.

103 {
104  if (a == RTLIL::State::S1) return RTLIL::State::S1;
105  if (b == RTLIL::State::S1) return RTLIL::State::S1;
106  if (a != RTLIL::State::S0) return RTLIL::State::Sx;
107  if (b != RTLIL::State::S0) return RTLIL::State::Sx;
108  return RTLIL::State::S0;
109 }

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static RTLIL::Const logic_reduce_wrapper ( RTLIL::State  initial,
RTLIL::State(*)(RTLIL::State, RTLIL::State logic_func,
const RTLIL::Const arg1,
int  result_len 
)
static

Definition at line 185 of file calc.cc.

186 {
187  RTLIL::State temp = initial;
188 
189  for (size_t i = 0; i < arg1.bits.size(); i++)
190  temp = logic_func(temp, arg1.bits[i]);
191 
192  RTLIL::Const result(temp);
193  while (int(result.bits.size()) < result_len)
194  result.bits.push_back(RTLIL::State::S0);
195  return result;
196 }
std::vector< RTLIL::State > bits
Definition: rtlil.h:438
State
Definition: rtlil.h:29

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static RTLIL::Const logic_wrapper ( RTLIL::State(*)(RTLIL::State, RTLIL::State logic_func,
RTLIL::Const  arg1,
RTLIL::Const  arg2,
bool  signed1,
bool  signed2,
int  result_len = -1 
)
static

Definition at line 146 of file calc.cc.

148 {
149  if (result_len < 0)
150  result_len = std::max(arg1.bits.size(), arg2.bits.size());
151 
152  extend_u0(arg1, result_len, signed1);
153  extend_u0(arg2, result_len, signed2);
154 
155  RTLIL::Const result(RTLIL::State::Sx, result_len);
156  for (size_t i = 0; i < size_t(result_len); i++) {
157  RTLIL::State a = i < arg1.bits.size() ? arg1.bits[i] : RTLIL::State::S0;
158  RTLIL::State b = i < arg2.bits.size() ? arg2.bits[i] : RTLIL::State::S0;
159  result.bits[i] = logic_func(a, b);
160  }
161 
162  return result;
163 }
static YOSYS_NAMESPACE_BEGIN void extend_u0(RTLIL::Const &arg, int width, bool is_signed)
Definition: calc.cc:29
std::vector< RTLIL::State > bits
Definition: rtlil.h:438
State
Definition: rtlil.h:29

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static RTLIL::State logic_xnor ( RTLIL::State  a,
RTLIL::State  b 
)
static

Definition at line 118 of file calc.cc.

119 {
120  if (a != RTLIL::State::S0 && a != RTLIL::State::S1) return RTLIL::State::Sx;
121  if (b != RTLIL::State::S0 && b != RTLIL::State::S1) return RTLIL::State::Sx;
122  return a == b ? RTLIL::State::S1 : RTLIL::State::S0;
123 }

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static RTLIL::State logic_xor ( RTLIL::State  a,
RTLIL::State  b 
)
static

Definition at line 111 of file calc.cc.

112 {
113  if (a != RTLIL::State::S0 && a != RTLIL::State::S1) return RTLIL::State::Sx;
114  if (b != RTLIL::State::S0 && b != RTLIL::State::S1) return RTLIL::State::Sx;
115  return a != b ? RTLIL::State::S1 : RTLIL::State::S0;
116 }

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