Go to the source code of this file.
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static YOSYS_NAMESPACE_BEGIN void | extend_u0 (RTLIL::Const &arg, int width, bool is_signed) |
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static BigInteger | const2big (const RTLIL::Const &val, bool as_signed, int &undef_bit_pos) |
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static RTLIL::Const | big2const (const BigInteger &val, int result_len, int undef_bit_pos) |
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static RTLIL::State | logic_and (RTLIL::State a, RTLIL::State b) |
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static RTLIL::State | logic_or (RTLIL::State a, RTLIL::State b) |
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static RTLIL::State | logic_xor (RTLIL::State a, RTLIL::State b) |
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static RTLIL::State | logic_xnor (RTLIL::State a, RTLIL::State b) |
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static RTLIL::Const | logic_wrapper (RTLIL::State(*logic_func)(RTLIL::State, RTLIL::State), RTLIL::Const arg1, RTLIL::Const arg2, bool signed1, bool signed2, int result_len=-1) |
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static RTLIL::Const | logic_reduce_wrapper (RTLIL::State initial, RTLIL::State(*logic_func)(RTLIL::State, RTLIL::State), const RTLIL::Const &arg1, int result_len) |
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static RTLIL::Const | const_shift_worker (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool sign_ext, int direction, int result_len) |
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static RTLIL::Const | const_shift_shiftx (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool, bool signed2, int result_len, RTLIL::State other_bits) |
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Definition at line 61 of file calc.cc.
63 if (undef_bit_pos >= 0)
74 for (
int i = 0; i < result_len; i++)
79 for (
int i = 0; i < result_len; i++)
85 if (undef_bit_pos >= 0)
86 for (
int i = undef_bit_pos; i < result_len; i++)
const BigUnsigned & getMagnitude() const
bool getBit(Index bi) const
Definition at line 42 of file calc.cc.
45 for (
size_t i = 0; i < val.
bits.size(); i++) {
47 if (as_signed && i+1 == val.
bits.size())
53 if (undef_bit_pos < 0)
std::vector< RTLIL::State > bits
Definition at line 324 of file calc.cc.
326 int undef_bit_pos = -1;
330 result_len = arg1.
bits.size();
333 if (undef_bit_pos >= 0)
336 for (
int i = 0; i < result_len; i++) {
338 if (pos < 0 || pos >= arg1.
bits.size())
339 result.bits[i] = other_bits;
static BigInteger const2big(const RTLIL::Const &val, bool as_signed, int &undef_bit_pos)
std::vector< RTLIL::State > bits
Definition at line 271 of file calc.cc.
273 int undef_bit_pos = -1;
277 result_len = arg1.
bits.size();
280 if (undef_bit_pos >= 0)
283 for (
int i = 0; i < result_len; i++) {
287 else if (pos >= arg1.
bits.size())
static BigInteger const2big(const RTLIL::Const &val, bool as_signed, int &undef_bit_pos)
std::vector< RTLIL::State > bits
Definition at line 29 of file calc.cc.
33 if (arg.
bits.size() > 0 && is_signed)
34 padding = arg.
bits.back();
36 while (
int(arg.
bits.size()) < width)
37 arg.
bits.push_back(padding);
39 arg.
bits.resize(width);
std::vector< RTLIL::State > bits
Definition at line 185 of file calc.cc.
189 for (
size_t i = 0; i < arg1.
bits.size(); i++)
190 temp = logic_func(temp, arg1.
bits[i]);
193 while (
int(result.bits.size()) < result_len)
std::vector< RTLIL::State > bits
Definition at line 146 of file calc.cc.
150 result_len = std::max(arg1.
bits.size(), arg2.
bits.size());
156 for (
size_t i = 0; i < size_t(result_len); i++) {
159 result.bits[i] = logic_func(a, b);
static YOSYS_NAMESPACE_BEGIN void extend_u0(RTLIL::Const &arg, int width, bool is_signed)
std::vector< RTLIL::State > bits