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physical_types.h
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1 /*
2  Data types describing the physical components on the FPGA architecture.
3 
4  We assume an island style FPGA where complex logic blocks are arranged in a grid and each side of the logic block has access to the inter-block interconnect. To keep the logic blocks general,
5  we allow arbitrary hierarchy, modes, primitives, and interconnect within each complex logic block. The data structures here describe the properties of the island-style FPGA as well as the details on
6  hierarchy, modes, primitives, and intconnect within each logic block.
7 
8  Data structures that flesh out
9 
10  The data structures that store the
11 
12  Key data types:
13  t_type_descriptor: describes a placeable complex logic block,
14  pb_type: describes the types of physical blocks within the t_type_descriptor in a hierarchy where the top block is the complex block and the leaf blocks implement one logical block
15  pb_graph_node: is a flattened version of pb_type so a pb_type with 10 instances will have 10 pb_graph_nodes representing each instance
16 
17  Additional notes:
18 
19  The interconnect specified in the architecture file gets flattened out in the pb_graph_node netlist. Each pb_graph_node contains pb_graph_pins which allow it to connect to other pb_graph_nodes.
20  These pins are in connected to other pins through pb_graph_edges. The pin connections are based on what is specified in the <interconnect> tags of the architecture file.
21 
22  Date: February 19, 2009
23  Authors: Jason Luu and Kenneth Kent
24  */
25 
26 #ifndef PHYSICAL_TYPES_H
27 #define PHYSICAL_TYPES_H
28 
29 #include "logic_types.h"
30 #include "util.h"
31 
32 typedef struct s_clock_arch t_clock_arch;
34 typedef struct s_power_arch t_power_arch;
38 typedef struct s_mode_power t_mode_power;
40 typedef struct s_port_power t_port_power;
42 typedef struct s_mode t_mode;
44 
45 /*************************************************************************************************/
46 /* FPGA basic definitions */
47 /*************************************************************************************************/
48 
49 /* Pins describe I/O into clustered logic block.
50  A pin may be unconnected, driving a net or in the fanout, respectively. */
51 enum e_pin_type {
52  OPEN = -1, DRIVER = 0, RECEIVER = 1
53 };
54 
55 /* Type of interconnect within complex block: Complete for everything connected (full crossbar), direct for one-to-one connections, and mux for many-to-one connections */
58 };
59 
60 /* Orientations. */
61 enum e_side {
62  TOP = 0, RIGHT = 1, BOTTOM = 2, LEFT = 3
63 };
64 
65 /* pin location distributions */
68 };
69 
70 /* pb_type class */
73 };
74 
75 /* Annotations for pin-to-pin connections */
80 };
83 };
91 };
94 };
97 };
98 
99 /* Power Estimation type for a PB */
101  POWER_METHOD_UNDEFINED = 0, POWER_METHOD_IGNORE, /* Ignore power of this PB, and all children PB */
102  POWER_METHOD_SUM_OF_CHILDREN, /* Ignore power of this PB, but consider children */
103  POWER_METHOD_AUTO_SIZES, /* Transistor-level, auto-sized buffers/wires */
104  POWER_METHOD_SPECIFY_SIZES, /* Transistor-level, user-specified buffers/wires */
105  POWER_METHOD_TOGGLE_PINS, /* Dynamic: Energy per pin toggle, Static: Absolute */
106  POWER_METHOD_C_INTERNAL, /* Dynamic: Equiv. Internal capacitance, Static: Absolute */
107  POWER_METHOD_ABSOLUTE /* Dynamic: Aboslute, Static: Absolute */
108 };
111 
112 /*************************************************************************************************/
113 /* FPGA grid layout data types */
114 /*************************************************************************************************/
115 /* Definition of how to place physical logic block in the grid
116  grid_loc_type - where the type goes and which numbers are valid
117  start_col - the absolute value of the starting column from the left to fill,
118  used with COL_REPEAT
119  repeat - the number of columns to skip before placing the same type,
120  used with COL_REPEAT. 0 means do not repeat
121  rel_col - the fractional column to place type
122  priority - in the event of conflict, which type gets picked?
123  */
126 };
127 typedef struct s_grid_loc_def {
130  int repeat;
131  float col_rel;
132  int priority;
134 
135 /* Data type definitions */
136 /* Grid info */
137 struct s_clb_grid {
138  boolean IsAuto;
139  float Aspect;
140  int W;
141  int H;
142 };
143 
144 /************************* POWER ***********************************/
145 
146 /* Global clock architecture */
147 struct s_clock_arch {
149  t_clock_network *clock_inf; /* Details about each clock */
150 };
151 
152 /* Architecture information for a single clock */
154  boolean autosize_buffer; /* autosize clock buffers */
155  float buffer_size; /* if not autosized, the clock buffer size */
156  float C_wire; /* Wire capacitance (per meter) */
157 
158  float prob; /* Static probability of net assigned to this clock */
159  float dens; /* Switching density of net assigned to this clock */
160  float period; /* Period of clock */
161 };
162 
163 /* Power-related architecture information */
164 struct s_power_arch {
165  float C_wire_local; /* Capacitance of local interconnect (per meter) */
166  //int seg_buffer_split; /* Split segment for distributed buffer (no split=1) */
171  float FF_size;
173 };
174 
175 /* Power usage for an entity */
177  float dynamic;
178  float leakage;
179 };
180 
181 /*************************************************************************************************/
182 /* FPGA Physical Logic Blocks data types */
183 /*************************************************************************************************/
184 
185 /* A class of CLB pins that share common properties
186  * port_name: name of this class of pins
187  * type: DRIVER or RECEIVER (what is this pinclass?) *
188  * num_pins: The number of logically equivalent pins forming this *
189  * class. *
190  * pinlist[]: List of clb pin numbers which belong to this class. */
191 struct s_class {
193  int num_pins;
194  int *pinlist; /* [0..num_pins - 1] */
195 };
196 typedef struct s_class t_class;
197 
198 /* Cluster timing delays:
199  * C_ipin_cblock: Capacitance added to a routing track by the isolation *
200  * buffer between a track and the Cblocks at an (i,j) loc. *
201  * T_ipin_cblock: Delay through an input pin connection box (from a *
202  * routing track to a logic block input pin). */
203 typedef struct s_timing_inf {
207  char * SDCFile; /* only here for convenience of passing to path_delay.c */
208 } t_timing_inf;
209 
210 struct s_pb_type;
211 /* declare before definition because pb_type contains modes and modes contain pb_types*/
212 
213 /** Describes I/O and clock ports
214  * name: name of the port
215  * model_port: associated model port
216  * is_clock: whether or not this port is a clock
217  * is_non_clock_global: Applies to top level pb_type, this pin is not a clock but is a global signal (useful for stuff like global reset signals, perhaps useful for VCC and GND)
218  * num_pins: the number of pins this port has
219  * parent_pb_type: pointer to the parent pb_type
220  * port_class: port belongs to recognized set of ports in class library
221  * index: port index by index in array of parent pb_type
222  * port_index_by_type index of port by type (index by input, output, or clock)
223  * equivalence:
224  */
225 struct s_port {
226  char* name;
228  enum PORTS type;
229  boolean is_clock;
231  int num_pins;
232  boolean equivalent;
234  char * port_class;
235 
236  int index;
238  char *chain_name;
239 
241 };
242 typedef struct s_port t_port;
243 
244 /**
245  * Info placed between pins that can be processed later for additional information
246  * value: value/property pair
247  * prop: value/property pair
248  * type: type of annotation
249  * format: formatting of data
250  * input_pins: input pins as string affected by annotation
251  * output_pins: output pins as string affected by annotation
252  * clock_pin: clock as string affected by annotation
253  */
255  char ** value; /* [0..num_value_prop_pairs - 1] */
256  int * prop; /* [0..num_value_prop_pairs - 1] */
258 
261 
262  char * input_pins;
263  char * output_pins;
264  char * clock;
265 
266  int line_num; /* used to report what line number this annotation is found in architecture file */
267 };
269 
270 struct s_pb_graph_edge;
271 
272 /** Describes interconnect edge inside a cluster
273  * type: type of the interconnect
274  * name: indentifier for interconnect
275  * input_string: input string verbatim to parse later
276  * output_string: input string output to parse later
277  * annotations: Annotations for delay, power, etc
278  * num_annotations: Total number of annotations
279  * infer_annotations: This interconnect is autogenerated, if true,
280  infer pack_patterns such as carry-chains and forced packs based on interconnect linked to it
281  * parent_mode_index: Mode of parent as int
282  */
285  char *name;
286 
289 
290  t_pin_to_pin_annotation *annotations; /* [0..num_annotations-1] */
293 
294  int line_num; /* Interconnect is processed later, need to know what line number it messed up on to give proper error message */
295 
297 
298  /* Power related members */
300 
302 };
304 
306 
308 
309  /* These are not necessarily power-related; however, at the moment
310  * only power estimation uses them
311  */
317 };
318 
321 
322  struct s_pb_graph_pin *** input_pins; // [0..num_input_ports-1][0..num_pins_per_port-1]
323  struct s_pb_graph_pin *** output_pins; // [0..num_output_ports-1][0..num_pins_per_port-1]
324 };
325 
326 /** Describes mode
327  * name: name of the mode
328  * pb_type_children: pb_types it contains
329  * interconnect: interconnect of parent pb_type to children pb_types or children to children pb_types
330  * num_interconnect: Total number of interconnect tags specified by user
331  * parent_pb_type: Which parent contains this mode
332  * index: Index of mode in array with other modes
333  */
334 struct s_mode {
335  char* name;
336  struct s_pb_type *pb_type_children; /* [0..num_child_pb_types] */
341  int index;
342 
343  /* Power releated members */
345 };
346 
347 struct s_mode_power {
348  t_power_usage power_usage; /* Power usage of this mode */
349 };
350 
351 /* Identify pb pin type for timing purposes */
359 };
360 
361 /** Describes a pb graph pin
362  * port: pointer to the port that this pin is associated with
363  * pin_number: pin number of the port that this pin is associated with
364  * input edges: [0..num_input_edges - 1]edges incoming
365  * num_input_edges: number edges incoming
366  * output edges: [0..num_output_edges - 1]edges out_going
367  * num_output_edges: number edges out_going
368  * parent_node: parent pb_graph_node
369  * pin_count_in_cluster: Unique number for pin inside cluster
370  */
374  struct s_pb_graph_edge** input_edges; /* [0..num_input_edges] */
376  struct s_pb_graph_edge** output_edges; /* [0..num_output_edges] */
378 
381 
382  int scratch_pad; /* temporary data structure useful to store traversal info */
383 
384  /* timing information */
385  enum e_pb_graph_pin_type type; /* Is a sequential logic element (TRUE), inpad/outpad (TRUE), or neither (FALSE) */
386  float tsu_tco; /* For sequential logic elements, this is the setup time (if input) or clock-to-q time (if output) */
387  struct s_pb_graph_pin** pin_timing; /* primitive ipin to opin timing */
388  float *pin_timing_del_max; /* primitive ipin to opin timing */
389  int num_pin_timing; /* primitive ipin to opin timing */
390 
391  /* Applies to clusters only */
393 
394  /* Applies to pins of primitive only */
395  int *parent_pin_class; /* [0..depth-1] the grouping of pins that this particular pin belongs to */
396  /* Applies to output pins of primitives only */
397  struct s_pb_graph_pin ***list_of_connectable_input_pin_ptrs; /* [0..depth-1][0..num_connectable_primtive_input_pins-1] what input pins this output can connect to without exiting cluster at given depth */
398  int *num_connectable_primtive_input_pins; /* [0..depth-1] number of input pins that this output pin can reach without exiting cluster at given depth */
399 
400  boolean is_forced_connection; /* This output pin connects to one and only one input pin */
401 
403 };
405 
407  /* Transistor-level Power Properties */
408  float C_wire;
409  float buffer_size;
410 
411  /* Pin-Toggle Power Properties */
413 };
414 
415 typedef enum {
423 
424 typedef enum {
430 
431 struct s_port_power {
432  /* Transistor-Level Power Properties */
433 
434  // Wire
436  union {
437  float C;
440  } wire;
441 
442  // Buffer
444  float buffer_size;
445 
446  /* Pin-Toggle Power Properties */
451  boolean reverse_scaled; /* Scale by (1-prob) */
452 };
453 
454 struct s_pb_graph_node;
455 
456 /** Describes a pb graph edge, this is a "fat" edge which means it supports bused based connections
457  * input_pins: array of pb_type graph input pins ptrs entering this edge
458  * num_input_pins: Number of input pins entering this edge
459  * output_pins: array of pb_type graph output pins ptrs entering this edge
460  * num_output_pins: Number of output pins entering this edge
461  */
467 
468  /* timing information */
469  float delay_max;
470  float delay_min;
471  float capacitance;
472 
473  /* who drives this edge */
477 
478  /* pack pattern info */
479  char **pack_pattern_names; /*[0..num_pack_patterns(of_edge)-1]*/
480  int *pack_pattern_indices; /*[0..num_pack_patterns(of_edge)-1]*/
482  boolean infer_pattern; /*If TRUE, infer pattern based on patterns connected to it*/
483 
484 };
486 
488 
489 /* This structure stores the physical block graph nodes for a pb_type and mode of a cluster
490  * pb_type: Pointer to the type of pb graph node this belongs to
491  * mode: parent mode of operation
492  * placement_index: there are a certain number of pbs available, this gives the index of the node
493  * child_pb_graph_nodes: array of children pb graph nodes organized into modes
494  * parent_pb_graph_node: parent pb graph node
495  */
499 
501 
502  t_pb_graph_pin **input_pins; /* [0..num_input_ports-1] [0..num_port_pins-1]*/
503  t_pb_graph_pin **output_pins; /* [0..num_output_ports-1] [0..num_port_pins-1]*/
504  t_pb_graph_pin **clock_pins; /* [0..num_clock_ports-1] [0..num_port_pins-1]*/
505 
509 
510  int *num_input_pins; /* [0..num_input_ports - 1] */
511  int *num_output_pins; /* [0..num_output_ports - 1] */
512  int *num_clock_pins; /* [0..num_clock_ports - 1] */
513 
514  struct s_pb_graph_node ***child_pb_graph_nodes; /* [0..num_modes-1][0..num_pb_type_in_mode-1][0..num_pb-1] */
516 
517  int total_pb_pins; /* only valid for top-level */
518 
519  void *temp_scratch_pad; /* temporary data, useful for keeping track of things when traversing data structure */
520  struct s_cluster_placement_primitive *cluster_placement_primitive; /* pointer to indexing structure useful during packing stage */
521 
522  int *input_pin_class_size; /* Stores the number of pins that belong to a particular input pin class */
523  int num_input_pin_class; /* number of pin classes that this input pb_graph_node has */
524  int *output_pin_class_size; /* Stores the number of pins that belong to a particular output pin class */
525  int num_output_pin_class; /* number of output pin classes that this pb_graph_node has */
526 
527  /* Interconnect instances for this pb
528  * Only used for power
529  */
531  t_interconnect_pins ** interconnect_pins; /* [0..num_modes-1][0..num_interconnect_in_mode] */
532 };
533 
535  float transistor_cnt_pb_children; /* Total transistor size of this pb */
536  float transistor_cnt_interc; /* Total transistor size of the interconnect in this pb */
538 };
539 
540 /** Describes a physical block type
541  * name: name of the physical block type
542  * num_pb: maximum number of instances of this physical block type sharing one parent
543  * blif_model: the string in the blif circuit that corresponds with this pb type
544  * class_type: Special library name
545  * modes: Different modes accepted
546  * ports: I/O and clock ports
547  * num_clock_pins: A count of the total number of clock pins
548  * int num_input_pins: A count of the total number of input pins
549  * int num_output_pins: A count of the total number of output pins
550  * timing: Timing matrix of block [0..num_inputs-1][0..num_outputs-1]
551  * parent_mode: mode of the parent block
552  */
553 struct s_pb_type {
554  char* name;
555  int num_pb;
556  char *blif_model;
559 
560  t_mode *modes; /* [0..num_modes-1] */
562  t_port *ports; /* [0..num_ports] */
564 
566  int num_input_pins; /* inputs not including clock pins */
568 
570  int depth; /* depth of pb_type */
571 
573  t_pin_to_pin_annotation *annotations; /* [0..num_annotations-1] */
575 
576  /* Power related members */
578 };
579 typedef struct s_pb_type t_pb_type;
580 
582  /* Type of power estimation for this pb */
584 
585  t_power_usage absolute_power_per_instance; /* User-provided absolute power per block */
586 
587  float C_internal; /*Internal capacitance of the pb */
588  int leakage_default_mode; /* Default mode for leakage analysis, if block has no set mode */
589 
590  t_power_usage power_usage; /* Total power usage of this pb type */
591  t_power_usage power_usage_bufs_wires; /* Power dissipated in local buffers and wire switching (Subset of total power) */
592 };
593 
594 /* Describes the type for a physical logic block
595  name: unique identifier for type
596  num_pins: Number of pins for the block
597  capacity: Number of blocks of this type that can occupy one grid tile.
598  This is primarily used for IO pads.
599  height: Height of large block in grid tiles
600  pinloc: Is set to 1 if a given pin exists on a certain position of a block.
601  num_class: Number of logically-equivalent pin classes
602  class_inf: Information of each logically-equivalent class
603  pin_class: The class a pin belongs to
604  is_global_pin: Whether or not a pin is global (hence not routed)
605  is_Fc_frac: True if Fc fractional, else Fc absolute
606  is_Fc_out_full_flex: True means opins will connect to all available segments
607  pb_type: Internal subblocks and routing information for this physical block
608  pb_graph_head: Head of DAG of pb_types_nodes and their edges
609 
610  area: Describes how much area this logic block takes, if undefined, use default
611  type_timing_inf: timing information unique to this type
612  num_drivers: Total number of output drivers supplied
613  num_receivers: Total number of input receivers supplied
614  index: Keep track of type in array for easy access
615  */
616 struct s_type_descriptor /* TODO rename this. maybe physical type descriptor or complex logic block or physical logic block*/
617 {
618  char *name;
619  int num_pins;
620  int capacity;
621 
622  int height;
623 
624  int ***pinloc; /* [0..height-1][0..3][0..num_pins-1] */
625  int *pin_height; /* [0..num_pins-1] */
626  int **num_pin_loc_assignments; /* [0..height-1][0..3] */
627  char ****pin_loc_assignments; /* [0..height-1][0..3][0..num_tokens-1][0..string_name] */
629 
631  struct s_class *class_inf; /* [0..num_class-1] */
632  int *pin_class; /* [0..num_pins-1] */
633 
634  boolean *is_global_pin; /* [0..num_pins-1] */
635 
636  boolean *is_Fc_frac; /* [0..num_pins-1] */
637  boolean *is_Fc_full_flex; /* [0..num_pins-1] */
638  float *Fc; /* [0..num_pins-1] */
639 
640  /* Clustering info */
643 
644  /* Grid location info */
645  struct s_grid_loc_def *grid_loc_def; /* [0..num_def-1] */
647  float area;
648 
649  /* This info can be determined from class_inf and pin_class but stored for faster access */
652 
653  int index; /* index of type descriptor in array (allows for index referencing) */
654 };
656 typedef const struct s_type_descriptor *t_type_ptr;
657 
658 /*************************************************************************************************/
659 /* FPGA Routing architecture */
660 /*************************************************************************************************/
661 
662 /* Description of routing channel distribution across the FPGA, only available for global routing
663  * Width is standard dev. for Gaussian. xpeak is where peak *
664  * occurs. dc is the dc offset for Gaussian and pulse waveforms. */
665 enum e_stat {
667 };
668 typedef struct s_chan {
669  enum e_stat type;
670  float peak;
671  float width;
672  float xpeak;
673  float dc;
674 } t_chan;
675 
676 /* chan_width_io: The relative width of the I/O channel between the pads *
677  * and logic array. *
678  * chan_x_dist: Describes the x-directed channel width distribution. *
679  * chan_y_dist: Describes the y-directed channel width distribution. */
680 typedef struct s_chan_width_dist {
685 
688 };
691 };
693 enum e_Fc_type {
695 };
696 
697 /* Lists all the important information about a certain segment type. Only *
698  * used if the route_type is DETAILED. [0 .. det_routing_arch.num_segment] *
699  * frequency: ratio of tracks which are of this segment type. *
700  * length: Length (in clbs) of the segment. *
701  * wire_switch: Index of the switch type that connects other wires *to* *
702  * this segment. *
703  * opin_switch: Index of the switch type that connects output pins (OPINs) *
704  * *to* this segment. *
705  * frac_cb: The fraction of logic blocks along its length to which this *
706  * segment can connect. (i.e. internal population). *
707  * frac_sb: The fraction of the length + 1 switch blocks along the segment *
708  * to which the segment can connect. Segments that aren't long *
709  * lines must connect to at least two switch boxes. *
710  * Cmetal: Capacitance of a routing track, per unit logic block length. *
711  * Rmetal: Resistance of a routing track, per unit logic block length.
712  * (UDSD by AY) drivers: How do signals driving a routing track connect to *
713  * the track? */
714 typedef struct s_segment_inf {
716  int length;
717  short wire_switch;
718  short opin_switch;
719  float frac_cb;
720  float frac_sb;
721  boolean longline;
722  float Rmetal;
723  float Cmetal;
725  boolean *cb;
726  int cb_len;
727  boolean *sb;
728  int sb_len;
729  //float Cmetal_per_m; /* Wire capacitance (per meter) */
730 } t_segment_inf;
731 
732 /* Lists all the important information about a switch type. *
733  * [0 .. Arch.num_switch] *
734  * buffered: Does this switch include a buffer? *
735  * R: Equivalent resistance of the buffer/switch. *
736  * Cin: Input capacitance. *
737  * Cout: Output capacitance. *
738  * Tdel: Intrinsic delay. The delay through an unloaded switch is *
739  * Tdel + R * Cout. *
740  * mux_trans_size: The area of each transistor in the segment's driving mux *
741  * measured in minimum width transistor units *
742  * buf_size: The area of the buffer. If set to zero, area should be *
743  * calculated from R */
744 typedef struct s_switch_inf {
745  boolean buffered;
746  float R;
747  float Cin;
748  float Cout;
749  float Tdel;
751  float buf_size;
752  char *name;
755 } t_switch_inf;
756 
757 /* Lists all the important information about a direct chain connection. *
758  * [0 .. det_routing_arch.num_direct] *
759  * name: Name of this direct chain connection *
760  * from_pin: The type of the pin that drives this chain connection *
761  In the format of <block_name>.<pin_name> *
762  * to_pin: The type of pin that is driven by this chain connection *
763  In the format of <block_name>.<pin_name> *
764  * x_offset: The x offset from the source to the sink of this connection *
765  * y_offset: The y offset from the source to the sink of this connection *
766  * line: The line number in the .arch file that specifies this *
767  * particular placement macro. *
768  */
769 typedef struct s_direct_inf {
770  char *name;
771  char *from_pin;
772  char *to_pin;
773  int x_offset;
774  int y_offset;
775  int z_offset;
776  int line;
777 } t_direct_inf;
778 
779 /* Detailed routing architecture */
780 typedef struct s_arch t_arch;
781 struct s_arch {
784  float R_minW_nmos;
785  float R_minW_pmos;
786  int Fs;
802 };
803 
804 #endif
805 
boolean is_clock
PORTS
Definition: logic_types.h:18
t_clock_network * clock_inf
t_interconnect * interconnect
t_pb_graph_pin ** clock_pins
enum e_pb_type_class class_type
e_pin_to_pin_delay_annotations
t_port_power * port_power
t_power_arch * power
e_stat
char * name
int num_pins
t_model_ports * model_port
char * chain_name
boolean equivalent
struct s_pb_type * pb_type_children
union s_port_power::@5 wire
enum e_power_estimation_method_ e_power_estimation_method
e_pin_to_pin_pack_pattern_annotations
struct s_direct_inf t_direct_inf
struct s_pb_graph_node * parent_pb_graph_node
e_power_estimation_method estimation_method
int * output_pin_class_size
t_direct_inf * Directs
boolean infer_annotations
enum e_power_estimation_method_ t_power_estimation_method
struct s_class * class_inf
t_model * model_library
float ipin_mux_trans_size
float R_minW_nmos
t_mode * modes
float T_ipin_cblock
t_power_usage power_usage
struct s_segment_inf t_segment_inf
float * pin_timing_del_max
t_model * models
float logical_effort_factor
t_pb_graph_pin ** output_pins
int num_interconnect
enum e_switch_block_type t_switch_block_type
struct s_pb_graph_edge ** output_edges
t_chan_width_dist Chans
e_power_estimation_method_
struct s_grid_loc_def * grid_loc_def
e_pin_location_distr
e_switch_block_type
boolean timing_analysis_enabled
t_pb_graph_node_power * pb_node_power
e_grid_loc_type
t_pb_type_power * pb_type_power
struct s_clb_grid clb_grid
e_side
enum PORTS type
e_pin_to_pin_annotation_format
char * blif_model
struct s_pb_graph_pin ** pin_timing
t_pb_graph_pin ** output_pins
t_model * model
t_interconnect * interconnect
t_pb_graph_pin * scaled_by_pin
enum e_pin_to_pin_annotation_format format
enum e_pin_location_distr pin_location_distribution
float transistors_per_SRAM_bit
enum e_pb_graph_pin_type type
struct s_cluster_placement_primitive * cluster_placement_primitive
enum e_directionality directionality
enum e_pin_to_pin_annotation_type type
t_interconnect * interconnect
float relative_length
float mux_trans_size
e_pb_type_class
struct s_pb_graph_pin *** output_pins
t_mode * parent_mode
float local_interc_factor
t_power_usage absolute_power_per_instance
float peak
struct s_pb_graph_edge ** input_edges
float dc
t_pin_to_pin_annotation * annotations
int num_annotations
struct s_chan t_chan
int * num_connectable_primtive_input_pins
t_clock_arch * clocks
float xpeak
int * pinlist
const struct s_type_descriptor * t_type_ptr
float R_minW_pmos
float grid_logic_tile_area
char * name
struct s_pb_graph_node * parent_node
e_pb_graph_pin_type
boolean IsAuto
struct s_switch_inf * Switches
e_pin_to_pin_annotation_type
char **** pin_loc_assignments
enum e_interconnect type
e_pin_type
t_pin_to_pin_annotation * annotations
boolean reverse_scaled
t_segment_inf * Segments
struct s_pb_graph_node *** child_pb_graph_nodes
int num_pb_type_children
int scaled_by_port_pin_idx
struct s_pb_graph_pin *** list_of_connectable_input_pin_ptrs
int * pack_pattern_indices
boolean is_forced_connection
int port_index_by_type
float absolute_length
float LUT_transistor_size
struct s_pb_type * pb_type
char ** pack_pattern_names
t_pb_graph_pin ** input_pins
e_pin_to_pin_capacitance_annotations
e_power_buffer_type
struct s_pb_type * pb_type
t_mode * parent_mode
struct s_pb_type * parent_pb_type
float energy_per_toggle
int ** num_pin_loc_assignments
struct s_chan_width_dist t_chan_width_dist
e_power_buffer_type buffer_type
t_port * ports
enum e_grid_loc_type grid_loc_type
struct s_timing_inf t_timing_inf
boolean pin_toggle_initialized
struct s_pb_graph_pin *** input_pins
float width
float power_buffer_size
int num_segments
int * input_pin_class_size
boolean autosize_buffer
t_pb_graph_node * pb_graph_head
e_Fc_type
struct s_switch_inf t_switch_inf
enum e_pin_type type
e_power_buffer_type power_buffer_type
enum e_stat type
float max_internal_delay
t_port * scaled_by_port
t_power_usage power_usage
e_power_wire_type wire_type
struct s_grid_loc_def t_grid_loc_def
int num_output_pins
t_power_usage power_usage
boolean buffered
int num_switches
boolean * is_global_pin
t_power_usage power_usage_bufs_wires
e_interconnect
float C_ipin_cblock
struct s_pb_type * parent_pb_type
t_mode_power * mode_power
float mux_transistor_size
boolean * is_Fc_full_flex
char * port_class
int num_input_pins
boolean is_non_clock_global
t_interconnect_power * interconnect_power
t_pb_graph_pin_power * pin_power
e_power_wire_type
t_pb_graph_pin ** input_pins
int num_clock_pins
int num_directs
t_interconnect_pins ** interconnect_pins
enum e_switch_block_type SBType
e_directionality