read_blif.h File Reference

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Functions
void	read_and_process_blif (char *blif_file, boolean sweep_hanging_nets_and_inputs, t_model *user_models, t_model *library_models, boolean read_activity_file, char *activity_file)
void	echo_input (char *blif_file, char *echo_file, t_model *library_models)
void	dum_parse (char *buf)

Function Documentation

void dum_parse

(

char *

buf

)

Definition at line 358 of file read_blif.c.

                          {

    /* Continue parsing to the end of this (possibly continued) line. */

    while (my_strtok(NULL, TOKENS, blif, buf) != NULL )
        ;
}

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void echo_input	(	char *	blif_file,
		char *	echo_file,
		t_model *	library_models
	)

Definition at line 980 of file read_blif.c.

                                                                           {

    /* Echo back the netlist data structures to file input.echo to *
     * allow the user to look at the internal state of the program *
     * and check the parsing.                                      */

    int i, j;
    FILE *fp;
    t_model_ports *port;
    t_model *latch_model;
    t_model *logic_model;
    t_model *cur;
    int *lut_distribution;
    int num_absorbable_latch;
    int inet;

    cur = library_models;
    logic_model = latch_model = NULL;
    while (cur) {
        if (strcmp(cur->name, MODEL_LOGIC) == 0) {
            logic_model = cur;
            assert(logic_model->inputs->next == NULL);
        } else if (strcmp(cur->name, MODEL_LATCH) == 0) {
            latch_model = cur;
            assert(latch_model->inputs->size == 1);
        }
        cur = cur->next;
    }

    lut_distribution = (int*) my_calloc(logic_model->inputs[0].size + 1,
            sizeof(int));
    num_absorbable_latch = 0;
    for (i = 0; i < num_logical_blocks; i++) {
        if (logical_block[i].model == logic_model) {
            if (logic_model == NULL )
                continue;
            for (j = 0; j < logic_model->inputs[0].size; j++) {
                if (logical_block[i].input_nets[0][j] == OPEN) {
                    break;
                }
            }
            lut_distribution[j]++;
        } else if (logical_block[i].model == latch_model) {
            if (latch_model == NULL )
                continue;
            inet = logical_block[i].input_nets[0][0];
            if (vpack_net[inet].num_sinks == 1
                    && logical_block[vpack_net[inet].node_block[0]].model
                            == logic_model) {
                num_absorbable_latch++;
            }
        }
    }

    vpr_printf(TIO_MESSAGE_INFO, "Input netlist file: '%s', model: %s\n",
            blif_file, model);
    vpr_printf(TIO_MESSAGE_INFO, "Primary inputs: %d, primary outputs: %d\n",
            num_p_inputs, num_p_outputs);
    vpr_printf(TIO_MESSAGE_INFO, "LUTs: %d, latches: %d, subckts: %d\n",
            num_luts, num_latches, num_subckts);
    vpr_printf(TIO_MESSAGE_INFO, "# standard absorbable latches: %d\n",
            num_absorbable_latch);
    vpr_printf(TIO_MESSAGE_INFO, "\t");
    for (i = 0; i < logic_model->inputs[0].size + 1; i++) {
        if (i > 0)
            vpr_printf(TIO_MESSAGE_DIRECT, ", ");
        vpr_printf(TIO_MESSAGE_DIRECT, "LUT size %d = %d", i,
                lut_distribution[i]);
    }
    vpr_printf(TIO_MESSAGE_DIRECT, "\n");
    vpr_printf(TIO_MESSAGE_INFO, "Total blocks: %d, total nets: %d\n",
            num_logical_blocks, num_logical_nets);

    fp = my_fopen(echo_file, "w", 0);

    fprintf(fp, "Input netlist file: '%s', model: %s\n", blif_file, model);
    fprintf(fp,
            "num_p_inputs: %d, num_p_outputs: %d, num_luts: %d, num_latches: %d\n",
            num_p_inputs, num_p_outputs, num_luts, num_latches);
    fprintf(fp, "num_logical_blocks: %d, num_logical_nets: %d\n",
            num_logical_blocks, num_logical_nets);

    fprintf(fp, "\nNet\tName\t\t#Pins\tDriver\tRecvs.\n");
    for (i = 0; i < num_logical_nets; i++) {
        fprintf(fp, "\n%d\t%s\t", i, vpack_net[i].name);
        if (strlen(vpack_net[i].name) < 8)
            fprintf(fp, "\t"); /* Name field is 16 chars wide */
        fprintf(fp, "%d", vpack_net[i].num_sinks + 1);
        for (j = 0; j <= vpack_net[i].num_sinks; j++)
            fprintf(fp, "\t(%d,%d,%d)", vpack_net[i].node_block[j],
                    vpack_net[i].node_block_port[j],
                    vpack_net[i].node_block_pin[j]);
    }

    fprintf(fp, "\n\nBlocks\t\tBlock type legend:\n");
    fprintf(fp, "\t\tINPAD = %d\tOUTPAD = %d\n", VPACK_INPAD, VPACK_OUTPAD);
    fprintf(fp, "\t\tCOMB = %d\tLATCH = %d\n", VPACK_COMB, VPACK_LATCH);
    fprintf(fp, "\t\tEMPTY = %d\n", VPACK_EMPTY);

    for (i = 0; i < num_logical_blocks; i++) {
        fprintf(fp, "\nblock %d %s ", i, logical_block[i].name);
        fprintf(fp, "\ttype: %d ", logical_block[i].type);
        fprintf(fp, "\tmodel name: %s\n", logical_block[i].model->name);

        port = logical_block[i].model->inputs;

        while (port) {
            fprintf(fp, "\tinput port: %s \t", port->name);
            for (j = 0; j < port->size; j++) {
                if (logical_block[i].input_nets[port->index][j] == OPEN)
                    fprintf(fp, "OPEN ");
                else
                    fprintf(fp, "%d ",
                            logical_block[i].input_nets[port->index][j]);
            }
            fprintf(fp, "\n");
            port = port->next;
        }

        port = logical_block[i].model->outputs;
        while (port) {
            fprintf(fp, "\toutput port: %s \t", port->name);
            for (j = 0; j < port->size; j++) {
                if (logical_block[i].output_nets[port->index][j] == OPEN) {
                    fprintf(fp, "OPEN ");
                } else {
                    fprintf(fp, "%d ",
                            logical_block[i].output_nets[port->index][j]);
                }
            }
            fprintf(fp, "\n");
            port = port->next;
        }

        fprintf(fp, "\tclock net: %d\n", logical_block[i].clock_net);
    }
    fclose(fp);
}

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void read_and_process_blif	(	char *	blif_file,
		boolean	sweep_hanging_nets_and_inputs,
		t_model *	user_models,
		t_model *	library_models,
		boolean	read_activity_file,
		char *	activity_file
	)

Definition at line 1765 of file read_blif.c.

                                                                                   {

    /* begin parsing blif input file */
    read_blif(blif_file, sweep_hanging_nets_and_inputs, user_models,
            library_models, read_activity_file, activity_file);

    /* TODO: Do check blif here 
     eg. 
     for (i = 0; i < num_logical_blocks; i++) {
     if (logical_block[i].model->num_inputs > max_subblock_inputs) {
     vpr_printf(TIO_MESSAGE_ERROR, "logical_block %s of model %s has %d inputs but architecture only supports subblocks up to %d inputs.\n",
     logical_block[i].name, logical_block[i].model->name, logical_block[i].model->num_inputs, max_subblock_inputs);
     exit(1);
     }
     }
     */

    if (getEchoEnabled() && isEchoFileEnabled(E_ECHO_BLIF_INPUT)) {
        echo_input(blif_file, getEchoFileName(E_ECHO_BLIF_INPUT),
                library_models);
    } else
        ;

    absorb_buffer_luts();
    compress_netlist(); /* remove unused inputs */

    /* NB:  It's important to mark clocks and such *after* compressing the   *
     * netlist because the vpack_net numbers, etc. may be changed by removing      *
     * unused inputs .  */

    show_blif_stats(user_models, library_models);
    free(logical_block_input_count);
    free(logical_block_output_count);
    free(model);
    logical_block_input_count = NULL;
    logical_block_output_count = NULL;
    model = NULL;
}

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