19 #ifndef TORC_ARCHITECTURE_VPREXPORTER_HPP
20 #define TORC_ARCHITECTURE_VPREXPORTER_HPP
27 namespace architecture {
95 #endif // TORC_ARCHITECTURE_VPREXPORTER_HPP
Encapsulation of a tile index in an unsigned 32-bit integer.
VPR node temporary class.
TileCol mMaxTileCol
Maximum column bounds.
Encapsulation of a tile row in an unsigned 16-bit integer.
VprExporter(DDB &inDDB)
Public constructor.
std::string string
Imported type name.
Encapsulation of a tile column in an unsigned 16-bit integer.
Device database, including complete wiring and logic support.
Device database exporter for the University of Toronto's VPR.
xilinx::TileRow TileRow
Imported type name.
xilinx::WireCount WireCount
Imported type name.
fstream mStream
Output file stream for VPR data.
Encapsulation of wire attribute flags in an unsigned 16-bit integer.
void operator()(void)
Exports routing graph information for VPR v6.0.
std::fstream fstream
Imported type name.
Encapsulation of a wire index in an unsigned 16-bit integer.
Encapsulation of a device tile and wire pair.
const Tiles & mTiles
Reference to the database Tiles object.
Tile map, tile type, and wire information for the family and device.
Encapsulation of a wire count in an unsigned 16-bit integer.
Encapsulation of a tile count in an unsigned 32-bit integer.
xilinx::TileCount TileCount
Imported type name.
DDB & mDDB
Reference to the database object.
TileCol mMinTileCol
Minimum column bounds.
TileRow mMaxTileRow
Maximum row bounds.
xilinx::TileIndex TileIndex
Imported type name.
std::vector< string > StringVector
Vector type.
Encapsulation of a tile type index in an unsigned 16-bit integer.
xilinx::TileCol TileCol
Imported type name.
TileRow mMinTileRow
Minimum row bounds.
Header for the DDB class.
xilinx::WireFlags WireFlags
Imported type name.
std::vector< uint32_t > Uint32Vector
Vector type.
Segment and irregular arc data for the device.
xilinx::WireIndex WireIndex
Imported type name.
xilinx::TileTypeIndex TileTypeIndex
Imported type name.
const Segments & mSegments
Reference to the database Segments object.
Device database types for Xilinx architectures.