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Virtex4.cpp
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1 // Torc - Copyright 2011-2013 University of Southern California. All Rights Reserved.
2 // $HeadURL$
3 // $Id$
4 
5 // This program is free software: you can redistribute it and/or modify it under the terms of the
6 // GNU General Public License as published by the Free Software Foundation, either version 3 of the
7 // License, or (at your option) any later version.
8 //
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11 // the GNU General Public License for more details.
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14 // not, see <http://www.gnu.org/licenses/>.
15 
16 /// \file
17 /// \brief Source for the Virtex4 class.
18 
20 #include <iostream>
21 
22 /// \todo Warning: this will need to be moved elsewhere.
26 #include <fstream>
27 
28 
29 namespace torc {
30 namespace bitstream {
31 
32  const char* Virtex4::sPacketTypeName[ePacketTypeCount] = {
33  "[UNKNOWN TYPE 0]", "TYPE1", "TYPE2", "[UNKNOWN TYPE 3]", "[UNKNOWN TYPE 4]",
34  "[UNKNOWN TYPE 5]", "[UNKNOWN TYPE 6]", "[UNKNOWN TYPE 7]"
35  };
36 
37  const char* Virtex4::sOpcodeName[eOpcodeCount] = {
38  "NOP", "READ", "WRITE", "RESERVED"
39  };
40 
41  const char* Virtex4::sRegisterName[eRegisterCount] = {
42  "CRC", "FAR", "FDRI", "FDRO", "CMD", "CTL", "MASK", "STAT", "LOUT", "COR", "MFWR", "CBC",
43  "IDCODE", "AXSS"
44  };
45 
46  const char* Virtex4::sCommandName[eCommandCount] = {
47  "NULL", "WCFG", "MFWR", "LFRM", "RCFG", "START", "RCAP", "RCRC", "AGHIGH", "SWITCH",
48  "GRESTORE", "SHUTDOWN", "GCAPTURE", "DESYNC"
49  };
50 
51 #define VALUES (const char*[])
52 
53  /// \see Configuration Options Register Description: UG071, v1.10, April 8, 2008, Table 7-10.
54  const Bitstream::Subfield Virtex4::sCOR[] = {
55  {0x00000007, 0, "GWE_cycle", "GWE_CYCLE", 5,
56  // bitgen: 6, 1, 2, 3, 4, 5, Done, Keep
57  // config: 001:"2", 010:"3", 011:"4", 100:"5", 101:"6"
58  VALUES{"[UNDEFINED 0]", "2", "3", "4", "5", "6", "[UNDEFINED 6]", "[UNDEFINED 7]", 0}},
59  {0x00000038, 3, "GTS_cycle", "GTS_CYCLE", 4,
60  // bitgen: 5, 1, 2, 3, 4, 6, Done, Keep
61  // config: 001:"2", 010:"3", 011:"4", 100:"5", 101:"6"
62  VALUES{"[UNDEFINED 0]", "2", "3", "4", "5", "6", "[UNDEFINED 6]", "[UNDEFINED 7]", 0}},
63  {0x000001c0, 6, "LCK_cycle", "LOCK_CYCLE", 7,
64  // bitgen: NoWait, 0, 1, 2, 3, 4, 5, 6
65  // config: 000:"1", 001:"2", 010:"3", 011:"4", 100:"5", 101:"6", 111:"NO_WAIT"
66  VALUES{"1", "2", "3", "4", "5", "6", "[UNDEFINED 6]", "NoWait", 0}},
67  {0x00000E00, 9, "Match_cycle", "MATCH_CYCLE", 7,
68  // bitgen: Auto, NoWait, 0, 1, 2, 3, 4, 5, 6
69  // config: 000:"1", 001:"2", 010:"3", 011:"4", 100:"5", 101:"6", 111:"NO_WAIT"
70  VALUES{"1", "2", "3", "4", "5", "6", "[UNDEFINED 6]", "NoWait", 0}},
71  {0x00007000, 12, "DONE_cycle", "DONE_CYCLE", 3,
72  // bitgen: 4, 1, 2, 3, 5, 6
73  // config: 001:"2", 010:"3", 011:"4", 100:"5", 101:"6"
74  VALUES{"[UNDEFINED 0]", "2", "3", "4", "5", "6", "[UNDEFINED 6]", "[UNDEFINED 7]", 0}},
75  {0x00018000, 15, "StartupClk", "SSCLKSRC", 0,
76  // bitgen: Cclk, UserClk, JtagClk
77  // config: 00:"CCLK", 01:"UserClk", 1x:"JTAGClk"
78  VALUES{"Cclk", "UserClk", "JtagClk", "JtagClk", 0}},
79  {0x007e0000, 17, "ConfigRate", "OSCFSEL", 0,
80  // bitgen: 4, 5, 7, 8, 9, 10, 13, 15, 20, 26, 30, 34, 41, 45, 51, 55, 60
81  // config: values undefined
82  VALUES{
83  "[UNKNOWN 0]", "[UNKNOWN 1]", "[UNKNOWN 2]", "[UNKNOWN 3]",
84  "[UNKNOWN 4]", "[UNKNOWN 5]", "[UNKNOWN 6]", "[UNKNOWN 7]",
85  "[UNKNOWN 8]", "[UNKNOWN 9]", "[UNKNOWN 10]", "[UNKNOWN 11]",
86  "[UNKNOWN 12]", "[UNKNOWN 13]", "[UNKNOWN 14]", "[UNKNOWN 15]",
87  "[UNKNOWN 16]", "[UNKNOWN 17]", "[UNKNOWN 18]", "[UNKNOWN 19]",
88  "[UNKNOWN 20]", "[UNKNOWN 21]", "[UNKNOWN 22]", "[UNKNOWN 23]",
89  "[UNKNOWN 24]", "[UNKNOWN 25]", "[UNKNOWN 26]", "[UNKNOWN 27]",
90  "[UNKNOWN 28]", "[UNKNOWN 29]", "[UNKNOWN 30]", "[UNKNOWN 31]",
91  0}},
92  {0x00800000, 23, "Capture", "SINGLE", 0,
93  // bitgen: n/a -- this comes from the CAPTURE site ONESHOT setting
94  // config: 0:"Readback is not single-shot", 1:"Readback is single-shot"
95  VALUES{"Continuous", "OneShot", 0}},
96  {0x01000000, 24, "DriveDone", "DRIVE_DONE", 0,
97  // bitgen: No, Yes
98  // config: 0:"DONE pin is open drain", 1:"DONE is actively driven high"
99  VALUES{"No", "Yes", 0}},
100  {0x02000000, 25, "DonePipe", "DONE_PIPE", 0,
101  // bitgen: No, Yes
102  // config: 0:"No pipeline stage for DONEIN", 1:"Add pipeline stage for DONEIN"
103  VALUES{"No", "Yes", 0}},
104  {0x10000000, 28, "CRC", "CRC_BYPASS", 0,
105  // bitgen: Enable, Disable
106  // config: 0:"CRC enabled", 1:"CRC disabled"
107  VALUES{"Enable", "Disable", 0}},
108  {0, 0, 0, 0, 0, 0}
109  };
110 
111  /// \see Status Register Description: UG071, v1.10, April 8, 2008, Table 7-9.
112  /// \note The "bitgen" names attempt to mimic the general bitgen convention.
113  const Bitstream::Subfield Virtex4::sSTAT[] = {
114  {0x00000001, 0, "CRC_error", "CRC_ERROR", 0,
115  // bitgen: n/a
116  // config: 0:"No CRC error", 1:"CRC error"
117  VALUES{"No", "Yes", 0}},
118  {0x00000002, 1, "DecryptorSecuritySet", "PART_SECURED", 0,
119  // bitgen: n/a
120  // config: 0:"Decryptor security not set", 1:"Decryptor security set"
121  VALUES{"No", "Yes", 0}},
122  {0x00000004, 2, "DCM_locked", "DCM_LOCK", 0,
123  // bitgen: n/a
124  // config: 0:"DCMs not locked", 1:"DCMs are locked"
125  VALUES{"No", "Yes", 0}},
126  {0x00000008, 3, "DCI_matched", "DCI_MATCH", 0,
127  // bitgen: n/a
128  // config: 0:"DCI not matched", 1:"DCI matched
129  VALUES{"No", "Yes", 0}},
130  {0x00000010, 4, "StartupFinished", "EOS", 0,
131  // bitgen: n/a
132  // config: 0:"Startup sequence has not finished", 1:"Startup sequence has finished"
133  VALUES{"No", "Yes", 0}},
134  {0x00000020, 5, "GTS_CFG_B", "GTS_CFG_B", 0,
135  // bitgen: n/a
136  // config: 0:"All I/Os are placed in high-Z state", 1:"All I/Os behave as configured"
137  VALUES{"IoDisabled", "IoEnabled", 0}},
138  {0x00000040, 6, "GWE", "GWE", 0,
139  // bitgen: n/a
140  // config: 0:"FFs and block RAM are write disabled", 1:"FFs and block RAM are write
141  // enabled"
142  VALUES{"WriteDisabled", "WriteEnabled", 0}},
143  {0x00000080, 7, "GHIGH_B", "GHIGH_B", 0,
144  // bitgen: n/a
145  // config: 0:"GHIGH_B asserted", 1:"GHIGH_B deasserted"
146  VALUES{"InterconnectDisabled", "InterconnectEnabled", 0}},
147  {0x00000700, 8, "Mode", "MODE", 0,
148  // bitgen: n/a
149  // config: Status of the MODE pins (M2:M0)
150  VALUES{"MasterSerial", "SlaveSelectMap32", "[UNDEFINED 2]", "MasterSelectMap",
151  "[UNDEFINED 3]", "JTAG", "SlaveSelectMap8", "[UNDEFINED 6]", "SlaveSerial", 0}},
152  {0x00000800, 11, "INIT_complete", "INIT_COMPLETE", 0,
153  // bitgen: n/a
154  // config: 0:"Initializations has not finished", 1:"Initialization finished"
155  VALUES{"No", "Yes", 0}},
156  {0x00001000, 12, "INIT", "INIT", 0,
157  // bitgen: n/a
158  // config: Value on INIT pin
159  VALUES{"Deasserted", "Asserted", 0}},
160  {0x00002000, 13, "DONE_released", "RELEASE_DONE", 0,
161  // bitgen: n/a
162  // config: 0:"DONE signal not released", 1:"DONE signal released"
163  VALUES{"DrivenLow", "Released", 0}},
164  {0x00004000, 14, "DONE", "DONE", 0,
165  // bitgen: n/a
166  // config: Value on DONE pin
167  VALUES{"NotDone", "Done", 0}},
168  {0x00008000, 15, "ID_error", "ID_ERROR", 0,
169  // bitgen: n/a
170  // config: 0:"No IE_ERROR", 1:"ID_ERROR"
171  VALUES{"NoError", "Error", 0}},
172  {0x00010000, 16, "Decrypt_error", "DEC_ERROR", 0,
173  // bitgen: n/a
174  // config: 0:"No DEC_ERROR", 1:"DEC_ERROR"
175  VALUES{"NoError", "Error", 0}},/*,
176  {0x00020000, 17, "Reserved", "Reserved", 0,
177  // bitgen: n/a
178  // config: undefined
179  VALUES{0}}*/
180  {0, 0, 0, 0, 0, 0}
181  };
182 
183  /// \see Control Register Description: UG071, v1.10, April 8, 2008, Table 7-7.
184  const Bitstream::Subfield Virtex4::sCTL[] = {
185  {0x00000001, 0, "GTS_USER_B", "GTS_USER_B", 0,
186  // bitgen: n/a?
187  // config: 0:"I/Os placed in high-Z state", 1:"I/Os active"
188  VALUES{"IoDisabled", "IoActive", 0}},
189  {0x00000008, 3, "Persist", "PERSIST", 0,
190  // bitgen: No, Yes
191  // config: 0:"No (default)", 1:"Yes"
192  VALUES{"No", "Yes", 0}},
193  {0x00000030, 4, "Security", "SBITS", 0,
194  // bitgen: None, Level1, Level2
195  // config: 00:"Read/Write OK (default)", 01:"Readback disabled", 1x:"Readback disabled,
196  // writing disabled except CRC register."
197  VALUES{"None", "Level1", "Level2", "Level2", 0}},
198  {0x00000100, 8, "GLUTMASK", "GLUTMASK", 0,
199  // bitgen: n/a
200  // config: 0:"Readback all 0s from SRL16 and Distributed RAM. Use with active device
201  // readback.", 1:"Readback dynamic values from SRL16 and Distributed RAM. Use with
202  // shutdown readback."
203  VALUES{"Masked", "Dynamic", 0}},
204  {0x40000000, 30, "ICAP_sel", "ICAP_SEL", 0,
205  // bitgen: n/a
206  // config: 0:"Top ICAP Port Enabled (default)", 1:"Bottom ICAP Port Enabled"
207  VALUES{"Top", "Bottom", 0}},
208  {0, 0, 0, 0, 0, 0}
209  };
210 
211  /// \see Control Mask Register Description: Inferred from Table 7-7.
212  const Bitstream::Subfield Virtex4::sMASK[] = {
213  {0x00000001, 0, "GTS_USER_B", "GTS_USER_B", 0, VALUES{"Protected", "Writable", 0}},
214  {0x00000008, 3, "Persist", "PERSIST", 0, VALUES{"Protected", "Writable", 0}},
215  {0x00000080, 4, "Security", "SBITS", 0,
216  VALUES{"Protected", "[UNKNOWN 1]", "[UNKNOWN 2]", "Writable", 0}},
217  {0x00000100, 8, "GLUTMASK", "GLUTMASK", 0, VALUES{"Protected", "Writable", 0}},
218  {0x40000000, 30, "ICAP_sel", "ICAP_SEL", 0, VALUES{"Protected", "Writable", 0}},
219  {0, 0, 0, 0, 0, 0}
220  };
221 
222  /// \brief Return the masked value for a subfield of the specified register.
223  uint32_t Virtex4::makeSubfield(ERegister inRegister, const std::string& inSubfield,
224  const std::string& inSetting) {
225  const Subfield* subfields;
226  switch(inRegister) {
227  case eRegisterCOR: subfields = sCOR; break;
228  case eRegisterSTAT: subfields = sSTAT; break;
229  case eRegisterCTL: subfields = sCTL; break;
230  case eRegisterMASK: subfields = sMASK; break;
231  default: return 0;
232  }
233  for(uint32_t field = 0; subfields[field].mMask != 0; field++) {
234  const Subfield& subfield = subfields[field];
235  if(inSubfield != subfield.mBitgenName && inSubfield != subfield.mConfigGuideName)
236  continue;
237  const char** ptr = subfield.mValues;
238  for(uint32_t i = 0; *ptr != 0; i++, ptr++) {
239  if(inSetting == *ptr) return (i << subfield.mShift) & subfield.mMask;
240  }
241  }
242  return 0;
243  }
244 
245 
246 // bool Virtex4::readPackets(std::istream& inStream) {
247 // uint32_t bitstreamWordLength = mBitstreamByteLength >> 2;
248 // uint32_t cumulativeWordLength = 0;
249 // while(cumulativeWordLength < bitstreamWordLength) {
250 // push_back(VirtexPacket::read(inStream));
251 // cumulativeWordLength += back().getWordSize();
252 // }
253 // return true;
254 // }
255 
256 //#define GENERATE_STATIC_DEVICE_INFO
257 #ifndef GENERATE_STATIC_DEVICE_INFO
258 
259  extern DeviceInfo xc4vfx12;
260  extern DeviceInfo xc4vfx20;
261  extern DeviceInfo xc4vfx40;
262  extern DeviceInfo xc4vfx60;
263  extern DeviceInfo xc4vfx100;
264  extern DeviceInfo xc4vfx140;
265  extern DeviceInfo xc4vlx15;
266  extern DeviceInfo xc4vlx25;
267  extern DeviceInfo xc4vlx40;
268  extern DeviceInfo xc4vlx60;
269  extern DeviceInfo xc4vlx80;
270  extern DeviceInfo xc4vlx100;
271  extern DeviceInfo xc4vlx160;
272  extern DeviceInfo xc4vlx200;
273  extern DeviceInfo xc4vsx25;
274  extern DeviceInfo xc4vsx35;
275  extern DeviceInfo xc4vsx55;
276 
277  void Virtex4::initializeDeviceInfo(const std::string& inDeviceName) {
278  using namespace torc::common;
279  switch(mDevice) {
280  if(false) ;
281  case eXC4VFX12: setDeviceInfo(xc4vfx12); break;
282  case eXC4VFX20: setDeviceInfo(xc4vfx20); break;
283  case eXC4VFX40: setDeviceInfo(xc4vfx40); break;
284  case eXC4VFX60: setDeviceInfo(xc4vfx60); break;
285  case eXC4VFX100: setDeviceInfo(xc4vfx100); break;
286  case eXC4VFX140: setDeviceInfo(xc4vfx140); break;
287  case eXC4VLX15: setDeviceInfo(xc4vlx15); break;
288  case eXC4VLX25: setDeviceInfo(xc4vlx25); break;
289  case eXC4VLX40: setDeviceInfo(xc4vlx40); break;
290  case eXC4VLX60: setDeviceInfo(xc4vlx60); break;
291  case eXC4VLX80: setDeviceInfo(xc4vlx80); break;
292  case eXC4VLX100: setDeviceInfo(xc4vlx100); break;
293  case eXC4VLX160: setDeviceInfo(xc4vlx160); break;
294  case eXC4VLX200: setDeviceInfo(xc4vlx200); break;
295  case eXC4VSX25: setDeviceInfo(xc4vsx25); break;
296  case eXC4VSX35: setDeviceInfo(xc4vsx35); break;
297  case eXC4VSX55: setDeviceInfo(xc4vsx55); break;
298  default: break;
299  }
300  }
301 
302 #else
303 
304  void Virtex4::initializeDeviceInfo(const std::string& inDeviceName) {
305 
311 
312  // look up the device tile map
313  torc::architecture::DDB ddb(inDeviceName);
314  const torc::architecture::Tiles& tiles = ddb.getTiles();
315  uint32_t tileCount = tiles.getTileCount();
316  uint16_t rowCount = tiles.getRowCount();
317  uint16_t colCount = tiles.getColCount();
318  ColumnTypeVector columnTypes;
319 
320  // set up the tile index and name mappings, and the index to column def mapping
321  typedef std::map<TileTypeIndex, std::string> TileTypeIndexToName;
322  typedef std::map<std::string, TileTypeIndex> TileTypeNameToIndex;
323  TileTypeIndexToName tileTypeIndexToName;
324  TileTypeNameToIndex tileTypeNameToIndex;
325  TileTypeCount tileTypeCount = tiles.getTileTypeCount();
326  for(TileTypeIndex tileTypeIndex(0); tileTypeIndex < tileTypeCount; tileTypeIndex++) {
327  const std::string tileTypeName = tiles.getTileTypeName(tileTypeIndex);
328  tileTypeIndexToName[tileTypeIndex] = tileTypeName;
329  tileTypeNameToIndex[tileTypeName] = tileTypeIndex;
330  TileTypeNameToColumnType::iterator ttwp = mTileTypeNameToColumnType.find(tileTypeName);
331  TileTypeNameToColumnType::iterator ttwe = mTileTypeNameToColumnType.end();
332  if(ttwp != ttwe) mTileTypeIndexToColumnType[tileTypeIndex] = EColumnType(ttwp->second);
333  }
334 
335  // identify every column that contains known frames
336  columnTypes.resize(colCount);
337  mFrameRowCount = 0;
338  for(uint32_t blockType = 0; blockType < eFarBlockTypeCount; blockType++) {
339  for(TileCol col; col < colCount; col++) {
340  columnTypes[col] = eColumnTypeEmpty;
341  TileTypeIndexToColumnType::iterator ttwe = mTileTypeIndexToColumnType.end();
342  TileTypeIndexToColumnType::iterator ttwp = ttwe;
343  for(TileRow row; row < rowCount; row++) {
344  // look up the tile info
345  const torc::architecture::TileInfo& tileInfo
346  = tiles.getTileInfo(tiles.getTileIndex(row, col));
347  TileTypeIndex tileTypeIndex = tileInfo.getTypeIndex();
348  // determine whether the tile type widths are defined
349  ttwp = mTileTypeIndexToColumnType.find(tileTypeIndex);
350  if(ttwp != ttwe) {
351  uint32_t width = mColumnDefs[ttwp->second][blockType];
352  mFrameRowCount += width;
353  //std::cout << " " << tiles.getTileTypeName(tileInfo.getTypeIndex())
354  // << ": " << width << " (" << mFrameRowCount << ")" << std::endl;
355  columnTypes[col] = static_cast<EColumnType>(ttwp->second);
356  break;
357  }
358  }
359  }
360  //std::cout << std::endl;
361  if(blockType == 2) break;
362  }
363 
365  boost::filesystem::path generatedMap = workingPath / (inDeviceName + ".map.csv");
366  std::fstream tilemapStream(generatedMap.string().c_str(), std::ios::out);
367  for(TileRow row; row < rowCount; row++) {
368  for(TileCol col; col < colCount; col++) {
369  const torc::architecture::TileInfo& tileInfo
370  = tiles.getTileInfo(tiles.getTileIndex(row, col));
371  TileTypeIndex tileTypeIndex = tileInfo.getTypeIndex();
372  tilemapStream << tiles.getTileTypeName(tileTypeIndex);
373  if(col + 1 < colCount) tilemapStream << ",";
374  }
375  tilemapStream << std::endl;
376  }
377  tilemapStream.close();
378 
379  // update bitstream device information
380  setDeviceInfo(DeviceInfo(tileCount, rowCount, colCount, columnTypes));
381  }
382 
383 #endif
384 
386 
387  bool debug = 0;
388  uint32_t farRowCount = (mDeviceInfo.getRowCount() / 18) >> 1;
389  uint32_t frameIndex = 0;
390  for(uint32_t i = 0; i < Virtex4::eFarBlockTypeCount; i++) {
392  uint32_t blockFrameIndexBounds = 0;
393  //Set first frame index to 0
394  uint32_t bitIndex = 0;
395  uint32_t xdlIndex = 0;
396  mBitColumnIndexes[i].push_back(bitIndex);
397  mXdlColumnIndexes[i].push_back(xdlIndex);
398  bool blockUsed = false;
399  for(uint32_t half = 0; half < 2; half++) {
400  for(uint32_t farRow = 0; farRow < farRowCount; farRow++) {
401  //build the columns
402  uint32_t farMajor = 0;
404  uint16_t finalColumn = mDeviceInfo.getColCount()-1;
405  uint32_t xdlColumnCount = 0;
406  uint32_t bitColumnCount = 0;
407  for(ColumnIndex col; col < mDeviceInfo.getColCount(); col++) {
408  uint32_t width = mColumnDefs[mDeviceInfo.getColumnTypes()[col]][i];
409  //Allocate the frame maps
410  for(uint32_t farMinor = 0; farMinor < width; farMinor++) {
411  Virtex4::FrameAddress far(Virtex4::EFarTopBottom(half), blockType,
412  farRow, farMajor, farMinor);
413  mFrameIndexToAddress[frameIndex] = far;
414  mFrameAddressToIndex[far] = frameIndex;
415  frameIndex++;
416  blockFrameIndexBounds++;
417  }
418  if(width > 0) {
419  farMajor++;
420  blockUsed = true;
421  }
422 
423  //Extract frame indexes for 1 row
424  if(farRow == 0 && half == 0) {
425  //Indexes for Bitstream Columns, only stores non-empty tile types
427  mXdlColumnToBitColumn[xdlColumnCount] = bitColumnCount;
428  bitColumnCount++;
429  bitIndex += width;
430  mBitColumnIndexes[i].push_back(bitIndex);
431  if(col == finalColumn) {
432  bitIndex += getRowPadFrames();
433  mBitColumnIndexes[i].push_back(bitIndex);
434  }
435  }
436  //Indexes for XDL Columns, stores interconnect and tile indexes for
437  //non-empty tiles
438  xdlIndex += width;
439  mXdlColumnIndexes[i].push_back(xdlIndex);
440  xdlColumnCount++;
441  if(col == finalColumn)
442  {
443  xdlIndex += getRowPadFrames();
444  mXdlColumnIndexes[i].push_back(xdlIndex);
445  }
446  }
447  }
448  // account for two pad frames after each frame row
449  if(blockUsed) {
450  frameIndex += getRowPadFrames();
451  blockFrameIndexBounds += getRowPadFrames();
452  }
453  if(debug) std::cout << "Last frame index: [" << i << ", " << frameIndex
454  << "]" << std::endl;
455  }
456  }
457  //stores frame index bounds for each block type
458  mBlockFrameIndexBounds[i] = blockFrameIndexBounds;
459  if(debug) std::cout << "***Block frame index bounds: " << mBlockFrameIndexBounds[i] << std::endl;
460  }
461  //Test to check proper indexing
462  if(debug) {
463  for(uint32_t i = 0; i < Virtex4::eFarBlockTypeCount; i++) {
464  for(uint32_t j = 0; j < mBitColumnIndexes[i].size(); j++)
465  std::cout << "Bit Value at index: (" << i << ", " << j << ") : " << mBitColumnIndexes[i][j] << std::endl;
466  for(uint32_t k = 0; k < mXdlColumnIndexes[i].size(); k++)
467  std::cout << "Xdl Value at index: (" << i << ", " << k << ") : " << mXdlColumnIndexes[i][k] << std::endl;
468  }
469  }
470  }
471 
473  // 0000004b: DUMMY
474  // 0000004f: SYNC
475  // 00000053: NOP x 1
476  // 00000057: TYPE1 WRITE CMD RCRC
477  // 0000005f: NOP x 2
478  // 00000067: TYPE1 WRITE COR: 00043fe5 (CRC:Enable, DonePipe:No, DriveDone:No,
479  // Capture:Continuous, ConfigRate:[UNKNOWN 2], StartupClk:Cclk, DONE_cycle:4,
480  // Match_cycle:NoWait, LCK_cycle:NoWait, GTS_cycle:5, GWE_cycle:6)
481  // 0000006f: TYPE1 WRITE IDCODE: 01eb4093
482  // 00000077: TYPE1 WRITE CMD SWITCH
483  // 0000007f: NOP x 1
484  // 00000083: TYPE1 WRITE MASK: 00000600 (ICAP_sel:Protected, GLUTMASK:Protected,
485  // Security:Protected, Persist:Protected, GTS_USER_B:Protected)
486  // 0000008b: TYPE1 WRITE CTL: 00000600 (ICAP_sel:Top, GLUTMASK:Masked, Security:None,
487  // Persist:No, GTS_USER_B:IoDisabled)
488  // 00000093: NOP x 1150
489  // 0000128b: TYPE1 WRITE MASK: 00000600 (ICAP_sel:Protected, GLUTMASK:Protected,
490  // Security:Protected, Persist:Protected, GTS_USER_B:Protected)
491  // 00001293: TYPE1 WRITE CTL: 00000000 (ICAP_sel:Top, GLUTMASK:Masked, Security:None,
492  // Persist:No, GTS_USER_B:IoDisabled)
493  // 0000129b: TYPE1 WRITE CMD NULL
494  // 000012a3: NOP x 1
495 
496  // declare the packet vector and define a NOP packet
497  typedef VirtexFrame::word_t word_t;
498  VirtexPacketVector packets;
502  // dummy and sync words
503  packets.push_back(dummy);
504  packets.push_back(VirtexPacket(eSynchronizationSync));
505  packets.push_back(nop);
506  // reset CRC command
508  packets.push_back(nop);
509  packets.push_back(nop);
510  // configuration options register
511  packets.push_back(VirtexPacket::makeType1Write(eRegisterCOR,
512  makeSubfield(eRegisterCOR, "CRC", "Enable") |
513  makeSubfield(eRegisterCOR, "DonePipe", "No") |
514  makeSubfield(eRegisterCOR, "DriveDone", "No") |
515  makeSubfield(eRegisterCOR, "Capture", "Continuous") |
516  makeSubfield(eRegisterCOR, "ConfigRate", "[UNKNOWN 2]") |
517  makeSubfield(eRegisterCOR, "StartupClk", "Cclk") |
518  makeSubfield(eRegisterCOR, "DONE_cycle", "4") |
519  makeSubfield(eRegisterCOR, "Match_cycle", "NoWait") |
520  makeSubfield(eRegisterCOR, "LCK_cycle", "NoWait") |
521  makeSubfield(eRegisterCOR, "GTS_cycle", "5") |
522  makeSubfield(eRegisterCOR, "GWE_cycle", "6") |
523  0));
524  // write the ID code
525  packets.push_back(VirtexPacket::makeType1Write(eRegisterIDCODE, 0x00000000));
526  // clock and rate switch command
528  packets.push_back(nop);
529  // control register mask
530  packets.push_back(VirtexPacket::makeType1Write(eRegisterMASK,
531  makeSubfield(eRegisterMASK, "ICAP_sel", "Protected") |
532  makeSubfield(eRegisterMASK, "GLUTMASK", "Protected") |
533  makeSubfield(eRegisterMASK, "Security", "Protected") |
534  makeSubfield(eRegisterMASK, "Persist", "Protected") |
535  makeSubfield(eRegisterMASK, "GTS_USER_B", "Protected") |
536  0x00000600 /* these bits are not defined in the configuration guide */ |
537  0));
538  // control register
539  packets.push_back(VirtexPacket::makeType1Write(eRegisterCTL,
540  makeSubfield(eRegisterCTL, "ICAP_sel", "Top") |
541  makeSubfield(eRegisterCTL, "GLUTMASK", "Masked") |
542  makeSubfield(eRegisterCTL, "Security", "None") |
543  makeSubfield(eRegisterCTL, "Persist", "No") |
544  makeSubfield(eRegisterCTL, "GTS_USER_B", "IoDisabled") |
545  0x00000600 /* these bits are not defined in the configuration guide */ |
546  0));
547  packets.insert(packets.end(), 1150, nop);
548  // control register mask
549  packets.push_back(VirtexPacket::makeType1Write(eRegisterMASK,
550  makeSubfield(eRegisterMASK, "ICAP_sel", "Protected") |
551  makeSubfield(eRegisterMASK, "GLUTMASK", "Protected") |
552  makeSubfield(eRegisterMASK, "Security", "Protected") |
553  makeSubfield(eRegisterMASK, "Persist", "Protected") |
554  makeSubfield(eRegisterMASK, "GTS_USER_B", "Protected") |
555  0x00000600 /* these bits are not defined in the configuration guide */ |
556  0));
557  // control register
558  packets.push_back(VirtexPacket::makeType1Write(eRegisterCTL,
559  makeSubfield(eRegisterCTL, "ICAP_sel", "Top") |
560  makeSubfield(eRegisterCTL, "GLUTMASK", "Masked") |
561  makeSubfield(eRegisterCTL, "Security", "None") |
562  makeSubfield(eRegisterCTL, "Persist", "No") |
563  makeSubfield(eRegisterCTL, "GTS_USER_B", "IoDisabled") |
564  0x00000000 /* these bits are not defined in the configuration guide */ |
565  0));
566  // NULL command
568  packets.push_back(nop);
569  // return the packet vector
570  return packets;
571  }
572 
574  // 00280d63: TYPE1 WRITE CRC: 789d0d51
575  // 00280d6b: TYPE1 WRITE CMD GRESTORE
576  // 00280d73: NOP x 1
577  // 00280d77: TYPE1 WRITE CMD LFRM
578  // 00280d7f: NOP x 100
579  // 00280f0f: TYPE1 WRITE CMD GRESTORE
580  // 00280f17: NOP x 1
581  // 00280f1b: TYPE1 WRITE CMD NULL
582  // 00280f23: NOP x 1
583  // 00280f27: TYPE1 WRITE FAR: 00010f00
584  // 00280f2f: TYPE1 WRITE CMD START
585  // 00280f37: NOP x 1
586  // 00280f3b: TYPE1 WRITE MASK: 00000000 (ICAP_sel:Protected, GLUTMASK:Protected,
587  // Security:Protected, Persist:Protected, GTS_USER_B:Protected)
588  // 00280f43: TYPE1 WRITE CTL: 00000000 (ICAP_sel:Top, GLUTMASK:Masked, Security:None,
589  // Persist:No, GTS_USER_B:IoDisabled)
590  // 00280f4b: TYPE1 WRITE CRC: 50ea82c0
591  // 00280f53: TYPE1 WRITE CMD DESYNC
592  // 00280f5b: NOP x 16
593 
594  // declare the packet vector and define a NOP packet
595  typedef VirtexFrame::word_t word_t;
596  VirtexPacketVector packets;
598  // write a placeholder CRC value
599  packets.push_back(VirtexPacket::makeType1Write(eRegisterCRC, 0));
600  // restore command
602  packets.push_back(nop);
603  // last frame command
605  packets.insert(packets.end(), 100, nop);
606  // restore command
608  packets.push_back(nop);
609  // NULL command
611  packets.push_back(nop);
612  // frame address register
613  packets.push_back(VirtexPacket::makeType1Write(eRegisterFAR,
614  eFarMaskBlockType | eFarMaskRow)); // is this what the configuration controller wants?
615  // start command
617  packets.push_back(nop);
618  // control register 0 mask
619  packets.push_back(VirtexPacket::makeType1Write(eRegisterMASK,
620  makeSubfield(eRegisterMASK, "ICAP_sel", "Protected") |
621  makeSubfield(eRegisterMASK, "GLUTMASK", "Protected") |
622  makeSubfield(eRegisterMASK, "Security", "Protected") |
623  makeSubfield(eRegisterMASK, "Persist", "Protected") |
624  makeSubfield(eRegisterMASK, "GTS_USER_B", "Protected") |
625  0));
626  // control register 0
627  packets.push_back(VirtexPacket::makeType1Write(eRegisterCTL,
628  makeSubfield(eRegisterCTL, "ICAP_sel", "Top") |
629  makeSubfield(eRegisterCTL, "GLUTMASK", "Masked") |
630  makeSubfield(eRegisterCTL, "Security", "None") |
631  makeSubfield(eRegisterCTL, "Persist", "No") |
632  makeSubfield(eRegisterCTL, "GTS_USER_B", "IoDisabled") |
633  0));
634  // write the CRC value
635  packets.push_back(VirtexPacket::makeType1Write(eRegisterCRC, 0x00000000));
636  // desynch command
638  packets.insert(packets.end(), 16, nop);
639  // return the packet vector
640  return packets;
641  }
642 
644  // Packets marked S pertain to shutdown bitstreams only
645  // 0000004b: DUMMY
646  // 0000004f: SYNC
647  // 00000053: NOP x 1
648  // 00000057: TYPE1 WRITE CMD RCRC
649  // 0000005f: NOP x 2
650  // 00000067: TYPE1 WRITE IDCODE: 01eb4093
651  // S 0000006f: TYPE1 WRITE COR: 00043fe5 (CRC:Enable, DonePipe:No, DriveDone:No,
652  // Capture:Continuous, ConfigRate:[UNKNOWN 2], StartupClk:Cclk, DONE_cycle:4,
653  // Match_cycle:NoWait, LCK_cycle:NoWait, GTS_cycle:5, GWE_cycle:6)
654  // S 00000077: TYPE1 WRITE CMD SHUTDOWN
655  // S 0000007f: NOP x 1
656  // S 00000083: TYPE1 WRITE CRC: 7f2b44a8
657  // S 0000008b: NOP x 4
658  // S 0000009b: TYPE1 WRITE CMD AGHIGH
659  // S 000000a3: NOP x 1
660 
661  // declare the packet vector and define a NOP packet
662  typedef VirtexFrame::word_t word_t;
663  VirtexPacketVector packets;
667  // dummy and sync words
668  packets.push_back(dummy);
669  packets.push_back(VirtexPacket(eSynchronizationSync));
670  packets.push_back(nop);
671  // reset CRC command
673  packets.push_back(nop);
674  packets.push_back(nop);
675  // write the ID code
676  packets.push_back(VirtexPacket::makeType1Write(eRegisterIDCODE, 0x00000000));
677  // extra for shutdown bitstreams
678  if(inBitstreamType == eBitstreamTypePartialShutdown) {
679  // configuration options register 0
680  packets.push_back(VirtexPacket::makeType1Write(eRegisterCOR,
681  makeSubfield(eRegisterCOR, "CRC", "Enable") |
682  makeSubfield(eRegisterCOR, "DonePipe", "No") |
683  makeSubfield(eRegisterCOR, "DriveDone", "No") |
684  makeSubfield(eRegisterCOR, "Capture", "Continuous") |
685  makeSubfield(eRegisterCOR, "ConfigRate", "[UNKNOWN 2]") |
686  makeSubfield(eRegisterCOR, "StartupClk", "Cclk") |
687  makeSubfield(eRegisterCOR, "DONE_cycle", "4") |
688  makeSubfield(eRegisterCOR, "Match_cycle", "NoWait") |
689  makeSubfield(eRegisterCOR, "LCK_cycle", "NoWait") |
690  makeSubfield(eRegisterCOR, "GTS_cycle", "5") |
691  makeSubfield(eRegisterCOR, "GWE_cycle", "6") |
692  0));
693  // shutdown command
695  packets.push_back(nop);
696  // write the CRC value
697  packets.push_back(VirtexPacket::makeType1Write(eRegisterCRC, 0x00000000));
698  packets.insert(packets.end(), 4, nop);
699  // aghigh command
701  packets.push_back(nop);
702  }
703  // return the packet vector
704  return packets;
705  }
706 
708  // Packets marked S pertain to shutdown bitstreams only
709  // S 00004db7: TYPE1 WRITE CMD GRESTORE
710  // S 00004dbf: NOP x 1
711  // 00004dc3: TYPE1 WRITE CMD LFRM
712  // 00004dcb: NOP x 101
713  // S 00004f5f: TYPE1 WRITE CMD GRESTORE
714  // S 00004f67: NOP x 1
715  // S 00004f6b: TYPE1 WRITE CMD START
716  // S 00004f73: NOP x 1
717  // 00004f77: TYPE1 WRITE CRC: f729c893
718  // 00004f7f: TYPE1 WRITE CMD DESYNC
719  // 00004f87: NOP x 4
720 
721  // declare the packet vector and define a NOP packet
722  typedef VirtexFrame::word_t word_t;
723  VirtexPacketVector packets;
725  // extra for shutdown bitstreams
726  if(inBitstreamType == eBitstreamTypePartialShutdown) {
727  // restore command
729  packets.push_back(nop);
730  }
731  // last frame command
733  packets.insert(packets.end(), 101, nop);
734  // extra for shutdown bitstreams
735  if(inBitstreamType == eBitstreamTypePartialShutdown) {
736  // restore command
738  packets.push_back(nop);
739  // start command
741  packets.push_back(nop);
742  }
743  // write the CRC value
744  packets.push_back(VirtexPacket::makeType1Write(eRegisterCRC, 0x00000000));
745  // desynch command
747  if(inBitstreamType == eBitstreamTypePartialShutdown) {
748  packets.insert(packets.end(), 4, nop);
749  } else {
750  packets.insert(packets.end(), 1, nop);
751  }
752  // return the packet vector
753  return packets;
754  }
755 
757  boost::shared_array<uint32_t> frameWords;
758  // walk the bitstream and extract all frames
759  Virtex4::iterator p = begin();
760  Virtex4::iterator e = end();
761  while(p < e) {
762  const VirtexPacket& packet = *p++;
763  if(packet.isType2() && packet.isWrite())
764  frameWords = packet.getWords();
765  }
766  uint32_t index = 0;
767  for (uint32_t i = 0; i < Bitstream::eBlockTypeCount; i++) {
768  // all frames of block type are extracted
769  uint32_t padExtra = getRowPadFrames() * getFrameRowCount();
770  for (uint32_t j = 0; j < mBlockFrameIndexBounds[i] + padExtra; j++) {
772  (new VirtexFrame(getFrameLength(), &frameWords[index])));
773  index += getFrameLength();
774  }
775  }
776  }
777 
779  uint32_t inFrameRow) {
780  if(inFrameRow > getFrameRowCount()) return VirtexFrameBlocks();
781 
782  // index and extract frames
783  int32_t bitColumnIndex[inBlockCount];
784  int32_t bitColumnBound[inBlockCount];
785  for(uint32_t i = 0; i < inBlockCount; i++) {
786  // adjust for the frame row
787  uint32_t lastIndex = mBitColumnIndexes[i].back();
788  uint32_t indexOffset = inFrameRow * (lastIndex ? (lastIndex + getRowPadFrames()) : 0);
789  // column Index of given frame index
790  bitColumnIndex[i] = mBitColumnIndexes[i][inBitCol] + indexOffset;
791  // frame bounds for given column type
792  bitColumnBound[i] = mColumnDefs[mDeviceInfo.getColumnTypes()[inBitCol]][i];
793  }
794  // extract the tile frames for the specified FAR
795  VirtexFrameBlocks frameBlocks;
796  for(uint32_t i = 0; i < inBlockCount; i++) {
797  int startIndex = bitColumnIndex[i];
798  for(int j = 0; j < bitColumnBound[i]; j++)
799  frameBlocks.mBlock[i].push_back(mFrameBlocks.mBlock[i][startIndex+j]);
800  }
801  return frameBlocks;
802  }
803 
805  uint32_t inFrameRow) {
806  if(inFrameRow > getFrameRowCount()) return VirtexFrameBlocks();
807 
808  // index and extract frames
809  int32_t xdlColumnIndex[inBlockCount];
810  int32_t xdlColumnBound[inBlockCount];
811  for(uint32_t i = 0; i < inBlockCount; i++) {
812  // adjust for the frame row
813  uint32_t lastIndex = mXdlColumnIndexes[i].back();
814  uint32_t indexOffset = inFrameRow * (lastIndex ? (lastIndex + getRowPadFrames()) : 0);
815  // column Index of given frame index
816  xdlColumnIndex[i] = mXdlColumnIndexes[i][inXdlCol] + indexOffset;
817  // frame bounds for given column type
818  xdlColumnBound[i] = mColumnDefs[mDeviceInfo.getColumnTypes()[inXdlCol]][i];
819  //std::cout << " block: " << i << ", start: " << xdlColumnIndex[i] << ", width: "
820  // << xdlColumnBound[i] << " ==== XDL column: " << inXdlCol << ", bit column: "
821  // << mXdlColumnToBitColumn[inXdlCol] << std::endl;
822  }
823  // extract the tile frames for the specified FAR
824  VirtexFrameBlocks frameBlocks;
825  for(uint32_t i = 0; i < inBlockCount; i++) {
826  int startIndex = xdlColumnIndex[i];
827  for(int j = 0; j < xdlColumnBound[i]; j++)
828  frameBlocks.mBlock[i].push_back(mFrameBlocks.mBlock[i][startIndex+j]);
829  }
830  return frameBlocks;
831  }
832 
833 } // namespace bitstream
834 } // namespace torc
ColumnDefVector mColumnDefs
Column type widths.
static const char * sOpcodeName[eOpcodeCount]
Packet opcode names.
Definition: Virtex4.hpp:101
DeviceInfo xc4vlx40
virtual VirtexPacketVector generatePartialBitstreamPrefix(EBitstreamType inBitstreamType)
Return a packet vector with the partial bitstream prefix.
Definition: Virtex4.cpp:643
Encapsulation of a tile row in an unsigned 16-bit integer.
EFarTopBottom
Frame Address Register top and bottom constants.
Definition: Virtex4.hpp:77
virtual uint32_t getFrameRowCount(void) const
Return the number of frame rows for the current device.
Definition: Virtex4.hpp:198
TileTypeNameToColumnType mTileTypeNameToColumnType
virtual void initializeDeviceInfo(const std::string &inDeviceName)
Initialize the device information.
Definition: Virtex4.cpp:277
std::map< uint32_t, uint32_t > mXdlColumnToBitColumn
Map of XDL column indexes to bitstream column indexes.
Definition: Virtex4.hpp:281
ERegister
Configuration register enumeration.
Definition: Virtex4.hpp:56
Encapsulation of a tile column in an unsigned 16-bit integer.
DeviceInfo xc4vfx40
Device database, including complete wiring and logic support.
Definition: DDB.hpp:42
FrameIndexToAddress mFrameIndexToAddress
Map of frame indexes to frame addresses.
Definition: Virtex4.hpp:271
TileTypeCount getTileTypeCount(void) const
Returns the tile type count for this device.
Definition: Tiles.hpp:151
Header for the Virtex4 class.
TileRow getRowCount(void) const
Returns the row count for this device.
Definition: Tiles.hpp:153
EColumnType
Major column types.
Definition: Virtex4.hpp:84
virtual uint32_t getRowPadFrames(void) const
Return the number of pad frames after each row.
Definition: Virtex4.hpp:202
Header for the DirectoryTree class.
virtual void initializeFrameMaps(void)
Initialize the maps between frame indexes and frame addresses. This is generally only useful for int...
Definition: Virtex4.cpp:385
VirtexFrameBlocks mFrameBlocks
Input Frame blocks.
virtual VirtexPacketVector generatePartialBitstreamSuffix(EBitstreamType inBitstreamType)
Return a packet vector with the partial bitstream suffix.
Definition: Virtex4.cpp:707
uint16_t getRowCount(void) const
Returns the row count.
Definition: DeviceInfo.hpp:112
Frame< uint32_t > VirtexFrame
Virtex frame type.
Definition: Frame.hpp:104
const TileInfo & getTileInfo(TileIndex inTileIndex) const
Returns the TileInfo object for the specified tile.
Definition: Tiles.hpp:137
VirtexFrameBlocks getXdlFrames(uint32_t inBlockCount, uint32_t inXdlCol, uint32_t inFrameRow=0)
Returns frames for queried xdl coordinates.
Definition: Virtex4.cpp:804
TileTypeIndexToColumnType mTileTypeIndexToColumnType
DeviceInfo xc4vsx25
virtual VirtexPacketVector generateFullBitstreamSuffix(void)
Return a packet vector with the full bitstream suffix.
Definition: Virtex4.cpp:573
Static device information class for Xilinx bitstreams. This class facilitates the creation of frame ...
Definition: DeviceInfo.hpp:75
static const char * sPacketTypeName[ePacketTypeCount]
Packet type names.
Definition: Virtex4.hpp:99
uint16_t getColCount(void) const
Returns the column count.
Definition: DeviceInfo.hpp:114
VirtexFrameBlocks getBitstreamFrames(uint32_t inBlockCount, uint32_t inBitCol, uint32_t inFrameRow=0)
Returns frames for queried bitstream coordinates.
Definition: Virtex4.cpp:778
DeviceInfo xc4vfx60
DeviceInfo xc4vsx55
static const char * sCommandName[eCommandCount]
Configuration command names.
Definition: Virtex4.hpp:105
TileCount getTileCount(void) const
Returns the tile count for this device.
Definition: Tiles.hpp:149
EDevice mDevice
Bitstream device enumeration.
#define VALUES
Definition: Virtex4.cpp:51
static const Subfield sCTL[]
Control Register (CTL) subfields.
Definition: Virtex4.hpp:111
DEPRECATED void initializeFullFrameBlocks(void)
Loads full bitstream frames into block data structure.
Definition: Virtex4.cpp:756
DeviceInfo xc4vsx35
std::string string
uint32_t mFrameRowCount
Number of frame rows.
Definition: Virtex4.hpp:283
uint32_t mBlockFrameIndexBounds[Virtex4::eFarBlockTypeCount]
Array to hold frame index boundaries for blocks.
Definition: Virtex4.hpp:279
uint32_t mShift
The subfield LSB position.
static const char * sRegisterName[eRegisterCount]
Configuration register names.
Definition: Virtex4.hpp:103
const char * mConfigGuideName
The subfield name documented in the configuration guide.
boost::uint32_t uint32_t
Imported type name.
VirtexFrame::word_t word_t
FrameSet word type.
Definition: FrameSet.hpp:85
static const Subfield sSTAT[]
Status Register (STAT) subfields.
Definition: Virtex4.hpp:109
uint32_t mMask
The subfield bit mask.
FrameAddressToIndex mFrameAddressToIndex
Map of frame addressee to frame indexes.
Definition: Virtex4.hpp:273
virtual uint32_t getFrameLength(void) const
Return the frame length for the current device.
Definition: Virtex4.hpp:200
DeviceInfo xc4vlx200
EFarBlockType
Frame Address Register block type constants.
Definition: Virtex4.hpp:79
DeviceInfo mDeviceInfo
Device information.
Tile map, tile type, and wire information for the family and device.
Definition: Tiles.hpp:36
FrameSet< FRAME_TYPE > mBlock[Bitstream::eBlockTypeCount]
FrameSets for each of the eight block types.
Definition: FrameSet.hpp:88
Encapsulation of a tile count in an unsigned 32-bit integer.
DeviceInfo xc4vlx15
Encapsulation of a tile within a device tile map.
Definition: TileInfo.hpp:33
EBitstreamType
The bitstream type to generate. Use eBitstreamFull to fully reconfigure a device, eBitstreamTypePartialActive to partially reconfigure it while it continues to run, or eBitstreamTypePartialShutdown to partially recongifure it after shutting it down.
const char * getTileTypeName(TileTypeIndex inTileTypeIndex) const
Returns the tile type name for the given tile type index.
Definition: Tiles.hpp:164
const ColumnTypeVector & getColumnTypes(void) const
Returns the column type vector.
Definition: DeviceInfo.hpp:116
boost::filesystem::path path
const TileTypeIndex & getTypeIndex(void) const
Returns the tile type index for this tile.
Definition: TileInfo.hpp:92
IndexVector mBitColumnIndexes[Virtex4::eFarBlockTypeCount]
Vector to store frame indexes of XDL columns.
Definition: Virtex4.hpp:275
static const Subfield sMASK[]
Control Mask Register (MASK) subfields.
Definition: Virtex4.hpp:113
DeviceInfo xc4vlx160
boost::shared_ptr< VirtexFrame > FrameSharedPtr
Shared pointer encapsulation of a Frame.
Definition: FrameSet.hpp:44
std::vector< VirtexPacket > VirtexPacketVector
Vector of Virtex packets.
static VirtexPacket makeType1Write(uint32_t inAddress, uint32_t inWord)
Construct a type 1 write packet.
const char * mBitgenName
The subfield name documented in bitgen.
DeviceInfo xc4vfx100
IndexVector mXdlColumnIndexes[Virtex4::eFarBlockTypeCount]
Vector to store frame indexes of Bitstream columns.
Definition: Virtex4.hpp:277
static const boost::filesystem::path & getWorkingPath(void)
Returns the absolute path to the working directory.
Encapsulation of a tile type count in an unsigned 16-bit integer.
const WordSharedArray getWords(void) const
brief Returns the raw packet words, including the header word.
static uint32_t makeSubfield(ERegister inRegister, const std::string &inSubfield, const std::string &inSetting)
Return the masked value for a subfield of the specified register.
Definition: Virtex4.cpp:223
DeviceInfo xc4vlx25
TileCol getColCount(void) const
Returns the column count for this device.
Definition: Tiles.hpp:155
Encapsulation of a tile type index in an unsigned 16-bit integer.
static const Subfield sCOR[]
Configuration Options Register (COR) subfields.
Definition: Virtex4.hpp:107
boost::uint16_t uint16_t
Imported type name.
Header for the DDB class.
FrameBlocks< VirtexFrame > VirtexFrameBlocks
Virtex frame blocks type.
Definition: FrameSet.hpp:91
Template base for encapsulated integers, to enforce strong typing.
void setDeviceInfo(const DeviceInfo &rhs)
Assign static device information for the current bitstream.
Bitstream packet for Virtex class architectures.
static uint32_t makeHeader(EPacketType inType, EOpcode inOpcode, uint32_t inAddress, uint32_t inCount)
Construct a packet header.
boost::uint32_t uint32_t
Imported type name.
Definition: Virtex4.hpp:50
DeviceInfo xc4vfx12
DeviceInfo xc4vlx80
DeviceInfo xc4vlx100
const char ** mValues
The allowable subfield values.
DeviceInfo xc4vfx20
DeviceInfo xc4vfx140
virtual VirtexPacketVector generateFullBitstreamPrefix(void)
Return a packet vector with the full bitstream prefix.
Definition: Virtex4.cpp:472
DeviceInfo xc4vlx60
TileIndex getTileIndex(TileRow inRow, TileCol inCol) const
Returns the tile index for the given [row,column] pair.
Definition: Tiles.hpp:161
WORD_TYPE word_t
Frame word type.
Definition: Frame.hpp:48
Device database types for Xilinx architectures.