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Virtex5.cpp
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1 // Torc - Copyright 2011-2013 University of Southern California. All Rights Reserved.
2 // $HeadURL$
3 // $Id$
4 
5 // This program is free software: you can redistribute it and/or modify it under the terms of the
6 // GNU General Public License as published by the Free Software Foundation, either version 3 of the
7 // License, or (at your option) any later version.
8 //
9 // This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
10 // without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
11 // the GNU General Public License for more details.
12 //
13 // You should have received a copy of the GNU General Public License along with this program. If
14 // not, see <http://www.gnu.org/licenses/>.
15 
17 #include <iostream>
18 
19 
20 /// \todo Warning: this will need to be moved elsewhere.
24 #include <fstream>
25 
26 
27 namespace torc {
28 namespace bitstream {
29 
30  const char* Virtex5::sPacketTypeName[ePacketTypeCount] = {
31  "[UNKNOWN TYPE 0]", "TYPE1", "TYPE2", "[UNKNOWN TYPE 3]", "[UNKNOWN TYPE 4]",
32  "[UNKNOWN TYPE 5]", "[UNKNOWN TYPE 6]", "[UNKNOWN TYPE 7]"
33  };
34 
35  const char* Virtex5::sOpcodeName[eOpcodeCount] = {
36  "NOP", "READ", "WRITE", "RESERVED"
37  };
38 
39  const char* Virtex5::sRegisterName[eRegisterCount] = {
40  "CRC", "FAR", "FDRI", "FDRO", "CMD", "CTL0", "MASK", "STAT", "LOUT", "COR0", "MFWR", "CBC",
41  "IDCODE", "AXSS", "COR1", "CSOB", "WBSTAR", "TIMER", "[UNKNOWN REG 18]",
42  "[UNKNOWN REG 19]", "[UNKNOWN REG 20]", "[UNKNOWN REG 21]", "BOOTSTS", "[UNKNOWN REG 23]",
43  "CTL1"
44  };
45 
46  const char* Virtex5::sCommandName[eCommandCount] = {
47  "NULL", "WCFG", "MFW", "DGHIGH/LFRM", "RCFG", "START", "RCAP", "RCRC", "AGHIGH", "SWITCH",
48  "GRESTORE", "SHUTDOWN", "GCAPTURE", "DESYNCH", "Reserved", "IPROG", "[UNKNOWN CMD 16]",
49  "LTIMER"
50  };
51 
52 #define VALUES (const char*[])
53 
54  /// \see Control Register 0 (CTL0): UG191, v3.7, June 24, 2009, Figure 6-1.
55  const Bitstream::Subfield Virtex5::sCTL0[] = {
56  {0x00000001, 0, "GTS_USER_B", "GTS_USER_B", 0,
57  // bitgen: n/a?
58  // config: 0:"I/Os 3-stated", 1:"I/Os active"
59  VALUES{"IoDisabled", "IoActive", 0}},
60  {0x00000008, 3, "Persist", "PERSIST", 0,
61  // bitgen: No, Yes
62  // config: 0:"No (default)", 1:"Yes"
63  VALUES{"No", "Yes", 0}},
64  {0x00000030, 4, "Security", "SBITS", 0,
65  // bitgen: None, Level1, Level2
66  // config: 00:"Read/Write OK (default)", 01:"Readback disabled", 1x:"Both writes and
67  // read disabled."
68  VALUES{"None", "Level1", "Level2", "Level2", 0}},
69  {0x00000040, 6, "Encrypt", "DEC", 0,
70  // bitgen: No, Yes
71  // config: AES Decryptor enable bit
72  VALUES{"No", "Yes", 0}},
73  {0x00000100, 8, "GLUTMASK", "GLUTMASK", 0,
74  // bitgen: n/a
75  // config: 0:"Readback all 0s from SRL16 and Distributed RAM. Use with active device
76  // readback.", 1:"Readback dynamic values from SRL16 and Distributed RAM. Use with
77  // shutdown readback."
78  VALUES{"Masked", "Dynamic", 0}},
79  {0x00001000, 12, "OverTempPowerDown", "OverTempPowerDown", 0,
80  // bitgen: Disable, Enable
81  // config: Enables the System Monitor Over-Temperature power down.
82  VALUES{"Disable", "Enable", 0}},
83  {0x40000000, 30, "ICAP_sel", "ICAP_SEL", 0,
84  // bitgen: n/a
85  // config: 0:"Top ICAP Port Enabled (default)", 1:"Bottom ICAP Port Enabled"
86  VALUES{"Top", "Bottom", 0}},
87  {0, 0, 0, 0, 0, 0}
88  };
89 
90  /// \see Control Register 0 (CTL0): UG191, v3.7, June 24, 2009, Figure 6-1.
91  const Bitstream::Subfield Virtex5::sMASK0[] = {
92  {0x00000001, 0, "GTS_USER_B", "GTS_USER_B", 0, VALUES{"Protected", "Writable", 0}},
93  {0x00000008, 3, "Persist", "PERSIST", 0, VALUES{"Protected", "Writable", 0}},
94  {0x00000030, 4, "Security", "SBITS", 0,
95  VALUES{"Protected", "[UNKNOWN 1]", "[UNKNOWN 2]", "Writable", 0}},
96  {0x00000040, 6, "Encrypt", "DEC", 0, VALUES{"Protected", "Writable", 0}},
97  {0x00000100, 8, "GLUTMASK", "GLUTMASK", 0, VALUES{"Protected", "Writable", 0}},
98  {0x00001000, 12, "OverTempPowerDown", "OverTempPowerDown", 0, VALUES{"Protected",
99  "Writable", 0}},
100  {0x40000000, 30, "ICAP_sel", "ICAP_SEL", 0, VALUES{"Protected", "Writable", 0}},
101  {0, 0, 0, 0, 0, 0}
102  };
103 
104  /// \see Control Register 1 (CTL1): UG191, v3.7, June 24, 2009, Figure 6-2.
105  const Bitstream::Subfield Virtex5::sCTL1[] = {
106  {0, 0, 0, 0, 0, 0}
107  };
108 
109  /// \see Configuration Options Register 0 (COR0): UG191, v3.7, June 24, 2009, Table 6-10.
110  const Bitstream::Subfield Virtex5::sCOR0[] = {
111  {0x00000007, 0, "GWE_cycle", "GWE_CYCLE", 5,
112  // bitgen: 6, 1, 2, 3, 4, 5, Done, Keep
113  // config: 000:"1", 001:"2", 010:"3", 011:"4", 100:"5", 101:"6", 110:"GTS tracks DONE
114  // pin. BitGen option -g GTS_cycle:Done", 111:"Keep"
115  VALUES{"1", "2", "3", "4", "5", "6", "Done", "Keep", 0}},
116  {0x00000038, 3, "GTS_cycle", "GTS_CYCLE", 4,
117  // bitgen: 5, 1, 2, 3, 4, 6, Done, Keep
118  // config: 000:"1", 001:"2", 010:"3", 011:"4", 100:"5", 101:"6", 110:"GTS tracks DONE
119  // pin. BitGen option -g GTS_cycle:Done", 001[sic]:"Keep" but assuming 111:"Keep"
120  VALUES{"1", "2", "3", "4", "5", "6", "Done", "Keep", 0}},
121  {0x000001c0, 6, "LCK_cycle", "LOCK_CYCLE", 0,
122  // bitgen: NoWait, 0, 1, 2, 3, 4, 5, 6
123  // config: 000:"0", 001:"1", 010:"2", 011:"3", 100:"4", 101:"5", 110:"6", 111:"KEEP"
124  VALUES{"0", "1", "2", "3", "4", "5", "6", "NoWait", 0}},
125  {0x00000E00, 9, "Match_cycle", "MATCH_CYCLE", 0,
126  // bitgen: Auto, NoWait, 0, 1, 2, 3, 4, 5, 6
127  // config: 000:"0", 001:"1", 010:"2", 011:"3", 100:"4", 101:"5", 110:"6", 111:"KEEP"
128  VALUES{"0", "1", "2", "3", "4", "5", "6", "NoWait", 0}},
129  {0x00007000, 12, "DONE_cycle", "DONE_CYCLE", 3,
130  // bitgen: 4, 1, 2, 3, 5, 6
131  // config: 000:"1", 001:"2", 010:"3", 011:"4", 100:"5", 101:"6", 110:"7", 111:"KEEP"
132  VALUES{"1", "2", "3", "4", "5", "6", "7", "KEEP", 0}},
133  {0x00018000, 15, "StartupClk", "SSCLKSRC", 0,
134  // bitgen: Cclk, UserClk, JtagClk
135  // config: 00:"CCLK", 01:"UserClk", 1x:"JTAGClk"
136  VALUES{"Cclk", "UserClk", "JtagClk", "JtagClk", 0}},
137  {0x007e0000, 17, "ConfigRate", "OSCFSEL", 0,
138  // bitgen: 2, 6, 9, 13, 17, 20, 24, 27, 31, 35, 38, 42, 46, 49, 53, 56, 60
139  // config: values undefined
140  VALUES{
141  "[UNKNOWN 0]", "[UNKNOWN 1]", "[UNKNOWN 2]", "[UNKNOWN 3]",
142  "[UNKNOWN 4]", "[UNKNOWN 5]", "[UNKNOWN 6]", "[UNKNOWN 7]",
143  "[UNKNOWN 8]", "[UNKNOWN 9]", "[UNKNOWN 10]", "[UNKNOWN 11]",
144  "[UNKNOWN 12]", "[UNKNOWN 13]", "[UNKNOWN 14]", "[UNKNOWN 15]",
145  "[UNKNOWN 16]", "[UNKNOWN 17]", "[UNKNOWN 18]", "[UNKNOWN 19]",
146  "[UNKNOWN 20]", "[UNKNOWN 21]", "[UNKNOWN 22]", "[UNKNOWN 23]",
147  "[UNKNOWN 24]", "[UNKNOWN 25]", "[UNKNOWN 26]", "[UNKNOWN 27]",
148  "[UNKNOWN 28]", "[UNKNOWN 29]", "[UNKNOWN 30]", "[UNKNOWN 31]",
149  0}},
150  {0x00800000, 23, "Capture", "SINGLE", 0,
151  // bitgen: n/a -- this comes from the CAPTURE site ONESHOT setting
152  // config: 0:"Readback is not single-shot", 1:"Readback is single-shot"
153  VALUES{"Continuous", "OneShot", 0}},
154  {0x01000000, 24, "DriveDone", "DRIVE_DONE", 0,
155  // bitgen: No, Yes
156  // config: 0:"DONE pin is open drain", 1:"DONE is actively driven high"
157  VALUES{"No", "Yes", 0}},
158  {0x02000000, 25, "DonePipe", "DONE_PIPE", 0,
159  // bitgen: No, Yes
160  // config: 0:"No pipeline stage for DONEIN", 1:"Add pipeline stage for DONEIN"
161  VALUES{"No", "Yes", 0}},
162  {0x08000000, 27, "DONE_status", "PWRDWN_STAT", 0,
163  // bitgen: n/a?
164  // config: 0:"DONE pin", 1:"Powerdown pin"
165  VALUES{"DonePin", "PowerdownPin", 0}},
166  {0x10000000, 28, "CRC", "CRC_BYPASS", 0,
167  // bitgen: Enable, Disable
168  // config: 0:"CRC enabled", 1:"CRC disabled"
169  VALUES{"Enable", "Disable", 0}},
170  {0, 0, 0, 0, 0, 0}
171  };
172 
173  /// \see Configuration Options Register 1 (COR1): UG191, v3.7, June 24, 2009, Table 6-11.
174  const Bitstream::Subfield Virtex5::sCOR1[] = {
175  {0x00000003, 0, "BPI_page_size", "BPI_PAGE_SIZE", 0,
176  // bitgen: 1, 4, 8
177  // config: 00:"1 byte/word", 01:"4 bytes/words", 10:"8 bytes/words", 11:"Reserved"
178  VALUES{"1", "4", "8", "Reserved", 0}},
179  {0x0000000C, 2, "BPI_1st_read_cycle", "BPI_1ST_READ_CYCLES", 0,
180  // bitgen: 1, 2, 3, 4
181  // config: 00:"1", 01:"2", 10:"3", 11:"4"
182  VALUES{"1", "4", "8", "Reserved", 0}},
183  {0x00000100, 8, "ContinuousReadbackCRC", "RBCRC_EN", 0,
184  // bitgen: n/a?
185  // config: Continuous readback CRC enable
186  VALUES{"Disabled", "Enabled", 0}},
187  {0x00000200, 9, "InitAsCRCErrorPin", "RBCRC_NO_PIN", 0,
188  // bitgen: n/a?
189  // config: Disables INIT_B as read back CRC error status output pin
190  VALUES{"Disabled", "Enabled", 0}},
191  {0x00020000, 17, "PersistDeassertAtDesynch", "PERSIST_DEASSERT_AT_DESYNCH", 0,
192  // bitgen: n/a?
193  // config: Enables deassertion of PERSIST with the DESYNCH command
194  VALUES{"Disabled", "Enabled", 0}},
195  {0, 0, 0, 0, 0, 0}
196  };
197 
198  /// \see WBSTAR Register Description: UG191, v3.7, June 24, 2009, Table 6-12.
199  const Bitstream::Subfield Virtex5::sWBSTAR[] = {
200  {0x18000000, 27, "NextRevisionSelect", "RS[1:0]", 0,
201  // config: RS[1:0] pin value on next warm boot
202  VALUES{"00", "01", "10", "11", 0}},
203  {0x04000000, 26, "RevisionSelectTristate", "RS_TS_B", 0,
204  // config: 0:"Disabled", 1:"Enabled"
205  VALUES{"Disabled", "Enabled", 0}},
206  {0, 0, 0, 0, 0, 0}
207  };
208 
209  /// \see TIMER Register Description: UG191, v3.7, June 24, 2009, Table 6-13.
210  const Bitstream::Subfield Virtex5::sTIMER[] = {
211  {0x01000000, 24, "TimerForConfig", "TIMER_CFG_MON", 0,
212  // config: 0:"Disabled", 1:"Enabled"
213  VALUES{"Disabled", "Enabled", 0}},
214  {0x02000000, 25, "TimerForUser", "TIMER_USR_MON", 0,
215  // config: 0:"Disabled", 1:"Enabled"
216  VALUES{"Disabled", "Enabled", 0}},
217  {0, 0, 0, 0, 0, 0}
218  };
219 
220  /// \see BOOTSTS Register Description: UG191, v3.7, June 24, 2009, Table 6-14.
221  const Bitstream::Subfield Virtex5::sBOOTSTS[] = {
222  {0x00000001, 0, "RegisterStatus0", "VALID_0", 0,
223  // config: Status valid
224  VALUES{"Valid", "Invalid", 0}},
225  {0x00000002, 1, "FallbackStatus0", "FALLBACK_0", 0,
226  // config: 0:"Normal configuration", 1:"Fallback to default reconfiguration, RS[1:0]
227  // actively drives 2'b00"
228  VALUES{"Normal", "Fallback", 0}},
229  {0x00000004, 2, "InternalTrigger0", "IPROG_0", 0,
230  // config: Internal PROG triggered configuration
231  VALUES{"External", "Internal", 0}},
232  {0x00000008, 3, "WatchdogTimeout0", "WTO_ERROR_0", 0,
233  // config: Watchdog time-out error
234  VALUES{"Valid", "Invalid", 0}},
235  {0x00000010, 4, "ID_error0", "ID_ERROR_0", 0,
236  // config: ID error
237  VALUES{"NoError", "Error", 0}},
238  {0x00000020, 5, "CRC_error0", "CRC_ERROR_0", 0,
239  // config: CRC error
240  VALUES{"NoError", "Error", 0}},
241  {0x00000040, 6, "BPI_wraparound_error0", "WRAP_ERROR_0", 0,
242  // config: BPI address counter wraparound error
243  VALUES{"NoError", "Error", 0}},
244  {0x00000080, 7, "ReadbackCRC_error0", "RBCRC_ERROR_0", 0,
245  // config: RBCRC error cause [sic] reconfiguration
246  VALUES{"NoError", "Error", 0}},
247  {0x00000100, 8, "RegisterStatus1", "VALID_1", 0,
248  // config: Status valid
249  VALUES{"Valid", "Invalid", 0}},
250  {0x00000200, 9, "FallbackStatus1", "FALLBACK_1", 0,
251  // config: 0:"Normal configuration", 1:"Fallback to default reconfiguration, RS[1:0]
252  // actively drives 2'b00"
253  VALUES{"Normal", "Fallback", 0}},
254  {0x00000400, 10, "InternalTrigger1", "IPROG_1", 0,
255  // config: Internal PROG triggered configuration
256  VALUES{"External", "Internal", 0}},
257  {0x00000800, 11, "WatchdogTimeout1", "WTO_ERROR_1", 0,
258  // config: Watchdog time-out error
259  VALUES{"Valid", "Invalid", 0}},
260  {0x00001000, 12, "ID_error1", "ID_ERROR_1", 0,
261  // config: ID error
262  VALUES{"NoError", "Error", 0}},
263  {0x00002000, 13, "CRC_error1", "CRC_ERROR_1", 0,
264  // config: CRC error
265  VALUES{"NoError", "Error", 0}},
266  {0x00004000, 14, "BPI_wraparound_error1", "WRAP_ERROR_1", 0,
267  // config: BPI address counter wraparound error
268  VALUES{"NoError", "Error", 0}},
269  {0x00008000, 15, "ReadbackCRC_error1", "RBCRC_ERROR_1", 0,
270  // config: RBCRC error cause [sic] reconfiguration
271  VALUES{"NoError", "Error", 0}},
272  {0, 0, 0, 0, 0, 0}
273  };
274 
275  /// \see Status Register Description: UG191, v3.7, June 24, 2009, Table 6-9.
276  const Bitstream::Subfield Virtex5::sSTAT[] = {
277  {0x00000001, 0, "CRC_error", "CRC_ERROR", 0,
278  // bitgen: n/a
279  // config: 0:"No CRC error", 1:"CRC error"
280  VALUES{"No", "Yes", 0}},
281  {0x00000002, 1, "DecryptorSecuritySet", "PART_SECURED", 0,
282  // bitgen: n/a
283  // config: 0:"Decryptor security not set", 1:"Decryptor security set"
284  VALUES{"No", "Yes", 0}},
285  {0x00000004, 2, "DCM_locked", "DCM_LOCK", 0,
286  // bitgen: n/a
287  // config: 0:"DCMs not locked", 1:"DCMs are locked"
288  VALUES{"No", "Yes", 0}},
289  {0x00000008, 3, "DCI_matched", "DCI_MATCH", 0,
290  // bitgen: n/a
291  // config: 0:"DCI not matched", 1:"DCI matched
292  VALUES{"No", "Yes", 0}},
293  {0x00000010, 4, "StartupFinished", "EOS", 0,
294  // bitgen: n/a
295  // config: 0:"Startup sequence has not finished", 1:"Startup sequence has finished"
296  VALUES{"No", "Yes", 0}},
297  {0x00000020, 5, "GTS_CFG_B", "GTS_CFG_B", 0,
298  // bitgen: n/a
299  // config: 0:"All I/Os are placed in high-Z state", 1:"All I/Os behave as configured"
300  VALUES{"IoDisabled", "IoEnabled", 0}},
301  {0x00000040, 6, "GWE", "GWE", 0,
302  // bitgen: n/a
303  // config: 0:"FFs and block RAM are write disabled", 1:"FFs and block RAM are write
304  // enabled"
305  VALUES{"WriteDisabled", "WriteEnabled", 0}},
306  {0x00000080, 7, "GHIGH_B", "GHIGH_B", 0,
307  // bitgen: n/a
308  // config: 0:"GHIGH_B asserted", 1:"GHIGH_B deasserted"
309  VALUES{"InterconnectDisabled", "InterconnectEnabled", 0}},
310  {0x00000700, 8, "Mode", "MODE", 0,
311  // bitgen: n/a
312  // config: Status of the MODE pins (M2:M0)
313  VALUES{"MasterSerial", "MasterSPI", "MasterBPI-Up", "MasterBPI-Down",
314  "MasterSelectMap", "JTAG", "SlaveSelectMap", "SlaveSerial", 0}},
315  {0x00000800, 11, "INIT_complete", "INIT_COMPLETE", 0,
316  // bitgen: n/a
317  // config: 0:"Initializations has not finished", 1:"Initialization finished"
318  VALUES{"No", "Yes", 0}},
319  {0x00001000, 12, "INIT_B", "INIT_B", 0,
320  // bitgen: n/a
321  // config: Value on INIT_B pin
322  VALUES{"Deasserted", "Asserted", 0}},
323  {0x00002000, 13, "DONE_released", "RELEASE_DONE", 0,
324  // bitgen: n/a
325  // config: 0:"DONE signal not released", 1:"DONE signal released"
326  VALUES{"DrivenLow", "Released", 0}},
327  {0x00004000, 14, "DONE", "DONE", 0,
328  // bitgen: n/a
329  // config: Value on DONE pin
330  VALUES{"NotDone", "Done", 0}},
331  {0x00008000, 15, "ID_error", "ID_ERROR", 0,
332  // bitgen: n/a
333  // config: 0:"No IE_ERROR", 1:"ID_ERROR"
334  VALUES{"NoError", "Error", 0}},
335  {0x00010000, 16, "Decrypt_error", "DEC_ERROR", 0,
336  // bitgen: n/a
337  // config: 0:"No DEC_ERROR", 1:"DEC_ERROR"
338  VALUES{"NoError", "Error", 0}},
339  {0x001c0000, 18, "StartupState", "STARTUP_STATE", 0,
340  // bitgen: n/a
341  // config: 000:"0", 001:"1", 010:"3", 011:"2", 100:"7", 101:"6", 110:"4", 111:"5"
342  VALUES{"0", "1", "3", "2", "7", "6", "4", "5", 0}},
343  {0x01c00000, 22, "FlashTypeSelect", "FS", 0,
344  // bitgen: n/a
345  // config: SPI Flash type select
346  VALUES{0}},
347  {0x06000000, 25, "BusWidth", "BUS_WIDTH", 0,
348  // bitgen: n/a
349  // config: 00:"x1", 01:"x8", 10:"x16", 11:"x32"
350  VALUES{"1", "8", "16", "32", 0}},
351  {0, 0, 0, 0, 0, 0}
352  };
353 
354  /// \brief Return the masked value for a subfield of the specified register.
355  uint32_t Virtex5::makeSubfield(ERegister inRegister, const std::string& inSubfield,
356  const std::string& inSetting) {
357  const Subfield* subfields;
358  switch(inRegister) {
359  case eRegisterCOR0: subfields = sCOR0; break;
360  case eRegisterCOR1: subfields = sCOR1; break;
361  case eRegisterSTAT: subfields = sSTAT; break;
362  case eRegisterCTL0: subfields = sCTL0; break;
363  case eRegisterCTL1: subfields = sCTL1; break;
364  case eRegisterMASK: subfields = sMASK0; break;
365  case eRegisterWBSTAR: subfields = sWBSTAR; break;
366  case eRegisterTIMER: subfields = sTIMER; break;
367  case eRegisterBOOTSTS: subfields = sBOOTSTS; break;
368  default: return 0;
369  }
370  for(uint32_t field = 0; subfields[field].mMask != 0; field++) {
371  const Subfield& subfield = subfields[field];
372  if(inSubfield != subfield.mBitgenName && inSubfield != subfield.mConfigGuideName)
373  continue;
374  const char** ptr = subfield.mValues;
375  for(uint32_t i = 0; *ptr != 0; i++, ptr++) {
376  if(inSetting == *ptr) return (i << subfield.mShift) & subfield.mMask;
377  }
378  }
379  return 0;
380  }
381 
382 //#define GENERATE_STATIC_DEVICE_INFO
383 #ifndef GENERATE_STATIC_DEVICE_INFO
384 
385  extern DeviceInfo xc5vfx30t;
386  extern DeviceInfo xc5vfx70t;
387  extern DeviceInfo xc5vfx100t;
388  extern DeviceInfo xc5vfx130t;
389  extern DeviceInfo xc5vfx200t;
390  extern DeviceInfo xc5vlx30;
391  extern DeviceInfo xc5vlx50;
392  extern DeviceInfo xc5vlx85;
393  extern DeviceInfo xc5vlx110;
394  extern DeviceInfo xc5vlx155;
395  extern DeviceInfo xc5vlx220;
396  extern DeviceInfo xc5vlx330;
397  extern DeviceInfo xc5vlx20t;
398  extern DeviceInfo xc5vlx30t;
399  extern DeviceInfo xc5vlx50t;
400  extern DeviceInfo xc5vlx85t;
401  extern DeviceInfo xc5vlx110t;
402  extern DeviceInfo xc5vlx155t;
403  extern DeviceInfo xc5vlx220t;
404  extern DeviceInfo xc5vlx330t;
405  extern DeviceInfo xc5vsx35t;
406  extern DeviceInfo xc5vsx50t;
407  extern DeviceInfo xc5vsx95t;
408  extern DeviceInfo xc5vsx240t;
409  extern DeviceInfo xc5vtx150t;
410  extern DeviceInfo xc5vtx240t;
411 
412  void Virtex5::initializeDeviceInfo(const std::string& inDeviceName) {
413  using namespace torc::common;
414  switch(mDevice) {
415  case eXC5VFX30T: setDeviceInfo(xc5vfx30t); break;
416  case eXC5VFX70T: setDeviceInfo(xc5vfx70t); break;
417  case eXC5VFX100T: setDeviceInfo(xc5vfx100t); break;
418  case eXC5VFX130T: setDeviceInfo(xc5vfx130t); break;
419  case eXC5VFX200T: setDeviceInfo(xc5vfx200t); break;
420  case eXC5VLX30: setDeviceInfo(xc5vlx30); break;
421  case eXC5VLX50: setDeviceInfo(xc5vlx50); break;
422  case eXC5VLX85: setDeviceInfo(xc5vlx85); break;
423  case eXC5VLX110: setDeviceInfo(xc5vlx110); break;
424  case eXC5VLX155: setDeviceInfo(xc5vlx155); break;
425  case eXC5VLX220: setDeviceInfo(xc5vlx220); break;
426  case eXC5VLX330: setDeviceInfo(xc5vlx330); break;
427  case eXC5VLX20T: setDeviceInfo(xc5vlx20t); break;
428  case eXC5VLX30T: setDeviceInfo(xc5vlx30t); break;
429  case eXC5VLX50T: setDeviceInfo(xc5vlx50t); break;
430  case eXC5VLX85T: setDeviceInfo(xc5vlx85t); break;
431  case eXC5VLX110T: setDeviceInfo(xc5vlx110t); break;
432  case eXC5VLX155T: setDeviceInfo(xc5vlx155t); break;
433  case eXC5VLX220T: setDeviceInfo(xc5vlx220t); break;
434  case eXC5VLX330T: setDeviceInfo(xc5vlx330t); break;
435  case eXC5VSX35T: setDeviceInfo(xc5vsx35t); break;
436  case eXC5VSX50T: setDeviceInfo(xc5vsx50t); break;
437  case eXC5VSX95T: setDeviceInfo(xc5vsx95t); break;
438  case eXC5VSX240T: setDeviceInfo(xc5vsx240t); break;
439  case eXC5VTX150T: setDeviceInfo(xc5vtx150t); break;
440  case eXC5VTX240T: setDeviceInfo(xc5vtx240t); break;
441  default: break;
442  }
443  }
444 
445 #else
446 
447  void Virtex5::initializeDeviceInfo(const std::string& inDeviceName) {
448 
454 
455  // look up the device tile map
456  torc::architecture::DDB ddb(inDeviceName);
457  const torc::architecture::Tiles& tiles = ddb.getTiles();
458  uint32_t tileCount = tiles.getTileCount();
459  uint16_t rowCount = tiles.getRowCount();
460  uint16_t colCount = tiles.getColCount();
461  ColumnTypeVector columnTypes;
462 
463  // set up the tile index and name mappings, and the index to column def mapping
464  typedef std::map<TileTypeIndex, std::string> TileTypeIndexToName;
465  typedef std::map<std::string, TileTypeIndex> TileTypeNameToIndex;
466  TileTypeIndexToName tileTypeIndexToName;
467  TileTypeNameToIndex tileTypeNameToIndex;
468  TileTypeCount tileTypeCount = tiles.getTileTypeCount();
469  for(TileTypeIndex tileTypeIndex(0); tileTypeIndex < tileTypeCount; tileTypeIndex++) {
470  const std::string tileTypeName = tiles.getTileTypeName(tileTypeIndex);
471  tileTypeIndexToName[tileTypeIndex] = tileTypeName;
472  tileTypeNameToIndex[tileTypeName] = tileTypeIndex;
473  TileTypeNameToColumnType::iterator ttwp = mTileTypeNameToColumnType.find(tileTypeName);
474  TileTypeNameToColumnType::iterator ttwe = mTileTypeNameToColumnType.end();
475  if(ttwp != ttwe) mTileTypeIndexToColumnType[tileTypeIndex] = EColumnType(ttwp->second);
476  }
477 
478  // identify every column that contains known frames
479  columnTypes.resize(colCount);
480  uint32_t frameRowCount = 0;
481  for(uint32_t blockType = 0; blockType < eFarBlockTypeCount; blockType++) {
482  for(TileCol col; col < colCount; col++) {
483  columnTypes[col] = eColumnTypeEmpty;
484  TileTypeIndexToColumnType::iterator ttwe = mTileTypeIndexToColumnType.end();
485  TileTypeIndexToColumnType::iterator ttwp = ttwe;
486  for(TileRow row; row < rowCount; row++) {
487  // look up the tile info
488  const torc::architecture::TileInfo& tileInfo
489  = tiles.getTileInfo(tiles.getTileIndex(row, col));
490  TileTypeIndex tileTypeIndex = tileInfo.getTypeIndex();
491  // determine whether the tile type widths are defined
492  ttwp = mTileTypeIndexToColumnType.find(tileTypeIndex);
493  if(ttwp != ttwe) {
494  uint32_t width = mColumnDefs[ttwp->second][blockType];
495  frameRowCount += width;
496  //std::cout << " " << tiles.getTileTypeName(tileInfo.getTypeIndex())
497  // << ": " << width << " (" << frameCount << ")" << std::endl;
498  columnTypes[col] = static_cast<EColumnType>(ttwp->second);
499  break;
500  }
501  }
502  }
503  //std::cout << std::endl;
504  //if(blockType == 2) break;
505  }
506 
508  boost::filesystem::path generatedMap = workingPath / (inDeviceName + ".map.csv");
509  std::fstream tilemapStream(generatedMap.string().c_str(), std::ios::out);
510  for(TileRow row; row < rowCount; row++) {
511  for(TileCol col; col < colCount; col++) {
512  const torc::architecture::TileInfo& tileInfo
513  = tiles.getTileInfo(tiles.getTileIndex(row, col));
514  TileTypeIndex tileTypeIndex = tileInfo.getTypeIndex();
515  tilemapStream << tiles.getTileTypeName(tileTypeIndex);
516  if(col + 1 < colCount) tilemapStream << ",";
517  }
518  tilemapStream << std::endl;
519  }
520  tilemapStream.close();
521 
522  // update bitstream device information
523  setDeviceInfo(DeviceInfo(tileCount, rowCount, colCount, columnTypes));
524  }
525 
526 #endif
527 
529 
530  bool debug = false;
531  mFrameRowCount = 0;
532  uint32_t frameCount = 0;
533  uint32_t farRowCount = (mDeviceInfo.getRowCount() / 22) >> 1;
534  // the xc5vlx20t has 3 total FAR rows, 1 in the bottom half, and 2 in the top half
535  bool shortBottomHalf = (farRowCount * 22 << 1) + 1 < mDeviceInfo.getRowCount();
536  if(shortBottomHalf) farRowCount++;
537 
538  // map XDL tiles to top/bottom halves and frame rows
539  uint32_t bottomRowCount = farRowCount - (shortBottomHalf ? 1 : 0);
540  uint32_t topRowCount = farRowCount;
541  // top half rows
542  uint32_t xdlRow = 0;
543  uint32_t xdlBaseRow = xdlRow;
544  for(uint32_t frameRow = topRowCount - 1; ; frameRow--) {
545  for(int i = 0; i < 22; i++, xdlRow++) {
546 //std::cout << "mapping XDL row " << xdlRow << " to top frame row " << frameRow << " (base " << xdlBaseRow << ")" << std::endl;
548  = FrameRowDesignator(eFarTop, frameRow, xdlBaseRow);
549  }
550  xdlBaseRow += 22;
551  if(frameRow == 0) break;
552  }
553  // bottom half rows
554  for(uint32_t frameRow = 0; frameRow < bottomRowCount; frameRow++) {
555  for(int i = 0; i < 22; i++, xdlRow++) {
556 //std::cout << "mapping XDL row " << xdlRow << " to bottom frame row " << frameRow << " (base " << xdlBaseRow << ")" << std::endl;
558  = FrameRowDesignator(eFarBottom, frameRow, xdlBaseRow);
559  }
560  xdlBaseRow += 22;
561  }
562 
563  // generate the columns and mappings
564  uint32_t frameIndex = 0;
565  for(uint32_t i = 0; i < Virtex5::eFarBlockTypeCount; i++) {
567  uint32_t blockFrameIndexBounds = 0;
568  //Set first frame index to 0
569  uint32_t bitIndex = 0;
570  uint32_t xdlIndex = 0;
571  mBitColumnIndexes[i].push_back(bitIndex);
572  mXdlColumnIndexes[i].push_back(xdlIndex);
573  bool blockUsed = false;
574  for(uint32_t half = 0; half < 2; half++) {
575  for(uint32_t farRow = 0; farRow < farRowCount; farRow++) {
576  // fix short bottom half on xc5vlx20t
577  if(shortBottomHalf && half == 0 && (farRow + 1 == farRowCount)) continue;
578  // count the number of frame rows
579  if(i == 0) mFrameRowCount++;
580  // build the columns
581  uint32_t farMajor = 0;
583  uint16_t finalColumn = mDeviceInfo.getColCount()-1;
584  uint32_t xdlColumnCount = 0;
585  uint32_t bitColumnCount = 0;
586  for(ColumnIndex col; col < mDeviceInfo.getColCount(); col++) {
587  uint32_t width = mColumnDefs[mDeviceInfo.getColumnTypes()[col]][i];
588  //Allocate the frame maps
589  for(uint32_t farMinor = 0; farMinor < width; farMinor++) {
590  Virtex5::FrameAddress far(Virtex5::EFarTopBottom(half), blockType,
591  farRow, farMajor, farMinor);
592  mFrameIndexToAddress[frameIndex] = far;
593  mFrameAddressToIndex[far] = frameIndex;
594  frameIndex++;
595  blockFrameIndexBounds++;
596  }
597  if(width > 0) {
598  farMajor++;
599  blockUsed = true;
600  }
601  frameCount += width;
602 
603  //Extract frame indexes for 1 row
604  if(farRow == 0 && half == 0) {
605  //Indexes for Bitstream Columns, only stores non-empty tile types
608  mBitColumnToXdlColumn[bitColumnCount] = xdlColumnCount;
609  bitColumnCount++;
610  bitIndex += width;
611  mBitColumnIndexes[i].push_back(bitIndex);
612  if(col == finalColumn) {
613  bitIndex += getRowPadFrames();
614  mBitColumnIndexes[i].push_back(bitIndex);
615  }
616  }
617  //Indexes for XDL Columns, stores interconnect and tile indexes for
618  //non-empty tiles
619  xdlIndex += width;
620  mXdlColumnIndexes[i].push_back(xdlIndex);
621  xdlColumnCount++;
622  if(col == finalColumn) {
623  xdlIndex += getRowPadFrames();
624  mXdlColumnIndexes[i].push_back(xdlIndex);
625  }
626  }
627  }
628  // account for two pad frames after each frame row
629  if(blockUsed) {
630  frameIndex += getRowPadFrames();
631  blockFrameIndexBounds += getRowPadFrames();
632  }
633  if(debug) std::cout << "Last frame index: [" << i << ", " << frameIndex
634  << "]" << std::endl;
635  }
636  }
637  //stores frame index bounds for each block type
638  mBlockFrameIndexBounds[i] = blockFrameIndexBounds;
639  if(debug) std::cout << "***Block frame index bounds: " << mBlockFrameIndexBounds[i]
640  << std::endl;
641  }
642  //Test to check proper indexing
643  if(debug) {
644  for(uint32_t i = 0; i < Virtex5::eFarBlockTypeCount; i++) {
645  for(uint32_t j = 0; j < mBitColumnIndexes[i].size(); j++)
646  std::cout << "Bit Value at index: (" << i << ", " << j << ") : "
647  << mBitColumnIndexes[i][j] << std::endl;
648  for(uint32_t k = 0; k < mXdlColumnIndexes[i].size(); k++)
649  std::cout << "Xdl Value at index: (" << i << ", " << k << ") : "
650  << mXdlColumnIndexes[i][k] << std::endl;
651  }
652  }
653  }
654 
656  // 0000005f: DUMMY
657  // 00000063: DUMMY
658  // 00000067: DUMMY
659  // 0000006b: DUMMY
660  // 0000006f: DUMMY
661  // 00000073: DUMMY
662  // 00000077: DUMMY
663  // 0000007b: DUMMY
664  // 0000007f: BUS WIDTH SYNC
665  // 00000083: BUS WIDTH DETECT
666  // 00000087: DUMMY
667  // 0000008b: DUMMY
668  // 0000008f: SYNC
669  // 00000093: NOP x 1
670  // 00000097: TYPE1 WRITE WBSTAR: 00000000 (RevisionSelectTristate:Disabled,
671  // NextRevisionSelect:00)
672  // 0000009f: TYPE1 WRITE CMD NULL
673  // 000000a7: NOP x 1
674  // 000000ab: TYPE1 WRITE CMD RCRC
675  // 000000b3: NOP x 2
676  // 000000bb: TYPE1 WRITE TIMER: 00000000 (TimerForUser:Disabled, TimerForConfig:Disabled)
677  // 000000c3: TYPE1 WRITE [UNKNOWN REG 19]: 00000000
678  // 000000cb: TYPE1 WRITE COR0: 00003fe5 (DONE_status:DonePin, DonePipe:No, DriveDone:No,
679  // Capture:Continuous, ConfigRate:[UNKNOWN 0], StartupClk:Cclk, DONE_cycle:4,
680  // Match_cycle:NoWait, GTS_cycle:5, GWE_cycle:6)
681  // 000000d3: TYPE1 WRITE COR1: 00000000 (PersistDeassertAtDesynch:Disabled,
682  // ActionReadbackCRC:Continue, InitAsCRCErrorPin:Disabled,
683  // ContinuousReadbackCRC:Disabled, BPI_1st_read_cycle:1, BPI_page_size:1)
684  // 000000db: TYPE1 WRITE IDCODE: 02ad6093
685  // 000000e3: TYPE1 WRITE CMD SWITCH
686  // 000000eb: NOP x 1
687  // 000000ef: TYPE1 WRITE MASK: 00400000 (ICAP_sel:Protected, OverTempPowerDown:Protected,
688  // GLUTMASK:Protected, Encrypt:Protected, Security:Protected,
689  // Persist:Protected, GTS_USER_B:Protected)
690  // 000000f7: TYPE1 WRITE CTL0: 00400000 (ICAP_sel:Top, OverTempPowerDown:Disable,
691  // GLUTMASK:Masked, Encrypt:No, Security:None, Persist:No,
692  // GTS_USER_B:IoDisabled)
693  // 000000ff: TYPE1 WRITE MASK: 00000000 ()
694  // 00000107: TYPE1 WRITE CTL1: 00000000 ()
695  // 0000010f: NOP x 8
696 
697  // declare the packet vector and define a NOP packet
698  typedef VirtexFrame::word_t word_t;
699  VirtexPacketVector packets;
702  // dummy words
703  packets.insert(packets.end(), 8, dummy);
704  // bus width detect
705  packets.push_back(VirtexPacket(eSynchronizationBusWidthSync));
706  packets.push_back(VirtexPacket(eSynchronizationBusWidthDetect));
707  packets.push_back(dummy);
708  packets.push_back(dummy);
709  // sync
710  packets.push_back(VirtexPacket(eSynchronizationSync));
711  packets.push_back(nop);
712  // warm boot register
713  packets.push_back(VirtexPacket::makeType1Write(eRegisterWBSTAR, 0));
714  // NULL command
716  packets.push_back(nop);
717  // reset CRC command
719  packets.push_back(nop);
720  packets.push_back(nop);
721  // watchdog timer
722  packets.push_back(VirtexPacket::makeType1Write(eRegisterTIMER, 0));
723  // undocumented register 19
724  packets.push_back(VirtexPacket::makeType1Write(19, 0));
725  // configuration options register 0
726  packets.push_back(VirtexPacket::makeType1Write(eRegisterCOR0,
727  makeSubfield(eRegisterCOR0, "DONE_status", "DonePin") |
728  makeSubfield(eRegisterCOR0, "DonePipe", "No") |
729  makeSubfield(eRegisterCOR0, "DriveDone", "No") |
730  makeSubfield(eRegisterCOR0, "Capture", "Continuous") |
731  makeSubfield(eRegisterCOR0, "ConfigRate", "[UNKNOWN 0]") |
732  makeSubfield(eRegisterCOR0, "StartupClk", "Cclk") |
733  makeSubfield(eRegisterCOR0, "DONE_cycle", "4") |
734  makeSubfield(eRegisterCOR0, "Match_cycle", "NoWait") |
735  makeSubfield(eRegisterCOR0, "GTS_cycle", "5") |
736  makeSubfield(eRegisterCOR0, "GWE_cycle", "6") |
737  0));
738  // configuration options register 1
739  packets.push_back(VirtexPacket::makeType1Write(eRegisterCOR1,
740  makeSubfield(eRegisterCOR1, "PersistDeassertAtDesynch", "Disabled") |
741  makeSubfield(eRegisterCOR1, "ActionReadbackCRC", "Continue") |
742  makeSubfield(eRegisterCOR1, "InitAsCRCErrorPin", "Disabled") |
743  makeSubfield(eRegisterCOR1, "ContinuousReadbackCRC", "Disabled") |
744  makeSubfield(eRegisterCOR1, "BPI_1st_read_cycle", "1") |
745  makeSubfield(eRegisterCOR1, "BPI_page_size", "1") |
746  0));
747  // write the ID code
748  packets.push_back(VirtexPacket::makeType1Write(eRegisterIDCODE, 0x00000000));
749  // clock and rate switch command
751  packets.push_back(nop);
752  // control register 0 mask
753  packets.push_back(VirtexPacket::makeType1Write(eRegisterMASK,
754  makeSubfield(eRegisterMASK, "ICAP_sel", "Protected") |
755  makeSubfield(eRegisterMASK, "OverTempPowerDown", "Protected") |
756  makeSubfield(eRegisterMASK, "GLUTMASK", "Protected") |
757  makeSubfield(eRegisterMASK, "FARSRC", "Protected") |
758  makeSubfield(eRegisterMASK, "Encrypt", "Protected") |
759  makeSubfield(eRegisterMASK, "Security", "Protected") |
760  makeSubfield(eRegisterMASK, "Persist", "Protected") |
761  makeSubfield(eRegisterMASK, "GTS_USER_B", "Protected") |
762  0x00400000 /* this bit is not defined in the configuration guide */ |
763  0));
764  // control register 0
765  packets.push_back(VirtexPacket::makeType1Write(eRegisterCTL0,
766  makeSubfield(eRegisterCTL0, "ICAP_sel", "Top") |
767  makeSubfield(eRegisterCTL0, "OverTempPowerDown", "Disable") |
768  makeSubfield(eRegisterCTL0, "GLUTMASK", "Dynamic") |
769  makeSubfield(eRegisterCTL0, "FARSRC", "FAR") |
770  makeSubfield(eRegisterCTL0, "Encrypt", "No") |
771  makeSubfield(eRegisterCTL0, "Security", "None") |
772  makeSubfield(eRegisterCTL0, "Persist", "No") |
773  makeSubfield(eRegisterCTL0, "GTS_USER_B", "IoDisabled") |
774  0x00400000 /* this bit is not defined in the configuration guide */ |
775  0));
776  // control register 1 mask
777  packets.push_back(VirtexPacket::makeType1Write(eRegisterMASK, 0));
778  // control register 1
779  packets.push_back(VirtexPacket::makeType1Write(eRegisterCTL1, 0));
780  // more NOPs
781  packets.insert(packets.end(), 8, nop);
782  // return the packet vector
783  return packets;
784  }
785 
787  // 003b57cb: TYPE1 WRITE CRC: 7db34bdb
788  // 003b57d3: TYPE1 WRITE CMD GRESTORE
789  // 003b57db: NOP x 1
790  // 003b57df: TYPE1 WRITE CMD DGHIGH/LFRM
791  // 003b57e7: NOP x 100
792  // 003b5977: TYPE1 WRITE CMD GRESTORE
793  // 003b597f: NOP x 30
794  // 003b59f7: TYPE1 WRITE CMD START
795  // 003b59ff: NOP x 1
796  // 003b5a03: TYPE1 WRITE FAR: 00ef8000
797  // 003b5a0b: TYPE1 WRITE MASK: 00400000 (ICAP_sel:Protected, OverTempPowerDown:Protected,
798  // GLUTMASK:Protected, Encrypt:Protected, Security:Protected,
799  // Persist:Protected, GTS_USER_B:Protected)
800  // 003b5a13: TYPE1 WRITE CTL0: 00400000 (ICAP_sel:Top, OverTempPowerDown:Disable,
801  // GLUTMASK:Masked, Encrypt:No, Security:None, Persist:No,
802  // GTS_USER_B:IoDisabled)
803  // 003b5a1b: TYPE1 WRITE CRC: 0c90449e
804  // 003b5a23: TYPE1 WRITE CMD DESYNCH
805  // 003b5a2b: NOP x 61
806 
807  // declare the packet vector and define a NOP packet
808  typedef VirtexFrame::word_t word_t;
809  VirtexPacketVector packets;
811  // write a placeholder CRC value
812  packets.push_back(VirtexPacket::makeType1Write(eRegisterCRC, 0));
813  // restore command
815  packets.push_back(nop);
816  // last frame command
818  packets.insert(packets.end(), 100, nop);
819  // restore command
821  packets.insert(packets.end(), 30, nop);
822  // start command
824  packets.push_back(nop);
825  // frame address register
826  packets.push_back(VirtexPacket::makeType1Write(eRegisterFAR,
827  eFarMaskBlockType | eFarMaskRow)); // is this what the configuration controller wants?
828  // control register 0 mask
829  packets.push_back(VirtexPacket::makeType1Write(eRegisterMASK,
830  makeSubfield(eRegisterMASK, "ICAP_sel", "Protected") |
831  makeSubfield(eRegisterMASK, "OverTempPowerDown", "Protected") |
832  makeSubfield(eRegisterMASK, "GLUTMASK", "Protected") |
833  makeSubfield(eRegisterMASK, "Encrypt", "Protected") |
834  makeSubfield(eRegisterMASK, "Security", "Protected") |
835  makeSubfield(eRegisterMASK, "Persist", "Protected") |
836  makeSubfield(eRegisterMASK, "GTS_USER_B", "Protected") |
837  0x00400000 /* this bit is not defined in the configuration guide */ |
838  0));
839  // control register 0
840  packets.push_back(VirtexPacket::makeType1Write(eRegisterCTL0,
841  makeSubfield(eRegisterCTL0, "ICAP_sel", "Top") |
842  makeSubfield(eRegisterCTL0, "OverTempPowerDown", "Disable") |
843  makeSubfield(eRegisterCTL0, "GLUTMASK", "Masked") |
844  makeSubfield(eRegisterCTL0, "Encrypt", "No") |
845  makeSubfield(eRegisterCTL0, "Security", "None") |
846  makeSubfield(eRegisterCTL0, "Persist", "No") |
847  makeSubfield(eRegisterCTL0, "GTS_USER_B", "IoDisabled") |
848  0x00400000 /* this bit is not defined in the configuration guide */ |
849  0));
850  // write the CRC value
851  packets.push_back(VirtexPacket::makeType1Write(eRegisterCRC, 0x00000000));
852  // desynch command
854  packets.insert(packets.end(), 61, nop);
855  // return the packet vector
856  return packets;
857  }
858 
860  // Packets marked S pertain to shutdown bitstreams only
861  // 0000005f: DUMMY
862  // 00000063: DUMMY
863  // 00000067: DUMMY
864  // 0000006b: DUMMY
865  // 0000006f: DUMMY
866  // 00000073: DUMMY
867  // 00000077: DUMMY
868  // 0000007b: DUMMY
869  // 0000007f: BUS WIDTH SYNC
870  // 00000083: BUS WIDTH DETECT
871  // 00000087: DUMMY
872  // 0000008b: DUMMY
873  // 0000008f: SYNC
874  // 00000093: NOP x 1
875  // 00000097: TYPE1 WRITE CMD RCRC
876  // 0000009f: NOP x 2
877  // 000000a7: TYPE1 WRITE IDCODE: 02ad6093
878  // S 000000af: TYPE1 WRITE COR0: 00003fe5 (CRC:Enable, DONE_status:DonePin, DonePipe:No,
879  // DriveDone:No, Capture:Continuous, ConfigRate:[UNKNOWN 0],
880  // StartupClk:Cclk, DONE_cycle:4, Match_cycle:NoWait, LCK_cycle:NoWait,
881  // GTS_cycle:5, GWE_cycle:6)
882  // S 000000b7: TYPE1 WRITE CMD SHUTDOWN
883  // S 000000bf: NOP x 1
884  // S 000000c3: TYPE1 WRITE CRC: e48ff1d0
885  // S 000000cb: NOP x 4
886  // S 000000db: TYPE1 WRITE CMD AGHIGH
887  // S 000000e3: NOP x 1
888 
889  // declare the packet vector and define a NOP packet
890  typedef VirtexFrame::word_t word_t;
891  VirtexPacketVector packets;
894  // dummy words
895  packets.insert(packets.end(), 8, dummy);
896  // bus width detect
897  packets.push_back(VirtexPacket(eSynchronizationBusWidthSync));
898  packets.push_back(VirtexPacket(eSynchronizationBusWidthDetect));
899  packets.push_back(dummy);
900  packets.push_back(dummy);
901  // sync
902  packets.push_back(VirtexPacket(eSynchronizationSync));
903  packets.push_back(nop);
904  // reset CRC command
906  packets.push_back(nop);
907  packets.push_back(nop);
908  // write the ID code
909  packets.push_back(VirtexPacket::makeType1Write(eRegisterIDCODE, 0x00000000));
910  // extra for shutdown bitstreams
911  if(inBitstreamType == eBitstreamTypePartialShutdown) {
912  // configuration options register 0
913  packets.push_back(VirtexPacket::makeType1Write(eRegisterCOR0,
914  makeSubfield(eRegisterCOR0, "CRC", "Enable") |
915  makeSubfield(eRegisterCOR0, "DONE_status", "DonePin") |
916  makeSubfield(eRegisterCOR0, "DonePipe", "No") |
917  makeSubfield(eRegisterCOR0, "DriveDone", "No") |
918  makeSubfield(eRegisterCOR0, "Capture", "Continuous") |
919  makeSubfield(eRegisterCOR0, "ConfigRate", "[UNKNOWN 0]") |
920  makeSubfield(eRegisterCOR0, "StartupClk", "Cclk") |
921  makeSubfield(eRegisterCOR0, "DONE_cycle", "4") |
922  makeSubfield(eRegisterCOR0, "Match_cycle", "NoWait") |
923  makeSubfield(eRegisterCOR0, "LCK_cycle", "NoWait") |
924  makeSubfield(eRegisterCOR0, "GTS_cycle", "5") |
925  makeSubfield(eRegisterCOR0, "GWE_cycle", "6") |
926  0));
927  // shutdown command
929  packets.push_back(nop);
930  // write the CRC value
931  packets.push_back(VirtexPacket::makeType1Write(eRegisterCRC, 0x00000000));
932  packets.insert(packets.end(), 4, nop);
933  // aghigh command
935  packets.push_back(nop);
936  }
937  // return the packet vector
938  return packets;
939  }
940 
942  // Packets marked S pertain to shutdown bitstreams only
943  // S 0000d8b7: TYPE1 WRITE CMD GRESTORE
944  // S 0000d8bf: NOP x 1
945  // 0000d8c3: TYPE1 WRITE MASK: 00001000 ()
946  // 0000d8cb: TYPE1 WRITE CTL1: 00000000 ()
947  // 0000d8d3: TYPE1 WRITE CMD DGHIGH/LFRM
948  // 0000d8db: NOP x 101
949  // S 0000da6f: TYPE1 WRITE CMD GRESTORE
950  // S 0000da77: NOP x 1
951  // S 0000da7b: TYPE1 WRITE CMD START
952  // S 0000da83: NOP x 1
953  // 0000da87: TYPE1 WRITE FAR: 00ef8000
954  // 0000da8f: TYPE1 WRITE CRC: 3b8df9dc
955  // 0000da97: TYPE1 WRITE CMD DESYNCH
956  // 0000da9f: NOP x 4
957 
958  // declare the packet vector and define a NOP packet
959  typedef VirtexFrame::word_t word_t;
960  VirtexPacketVector packets;
962  // extra for shutdown bitstreams
963  if(inBitstreamType == eBitstreamTypePartialShutdown) {
964  // restore command
966  packets.push_back(nop);
967  }
968  // control register 1 mask
969  packets.push_back(VirtexPacket::makeType1Write(eRegisterMASK,
970  0x00001000 /* this value is undocumented for CTL1 in the configuration guide */ |
971  0));
972  // control register 1
973  packets.push_back(VirtexPacket::makeType1Write(eRegisterCTL1,
974  0x00000000 /* this value is undocumented for CTL1 in the configuration guide */ |
975  0));
976  // last frame command
978  packets.insert(packets.end(), 101, nop);
979  // extra for shutdown bitstreams
980  if(inBitstreamType == eBitstreamTypePartialShutdown) {
981  // restore command
983  packets.push_back(nop);
984  // start command
986  packets.push_back(nop);
987  }
988  // frame address register
989  packets.push_back(VirtexPacket::makeType1Write(eRegisterFAR,
990  eFarMaskBlockType | eFarMaskRow)); // is this what the configuration controller wants?
991  // write the CRC value
992  packets.push_back(VirtexPacket::makeType1Write(eRegisterCRC, 0x00000000));
993  // desynch command
995  if(inBitstreamType == eBitstreamTypePartialShutdown) {
996  packets.insert(packets.end(), 4, nop);
997  } else {
998  packets.insert(packets.end(), 1, nop);
999  }
1000  // return the packet vector
1001  return packets;
1002  }
1003 
1005  boost::shared_array<uint32_t> frameWords;
1006  // walk the bitstream and extract all frames
1007  Virtex5::iterator p = begin();
1008  Virtex5::iterator e = end();
1009  while(p < e) {
1010  const VirtexPacket& packet = *p++;
1011  if(packet.isType2() && packet.isWrite())
1012  frameWords = packet.getWords();
1013  }
1014  uint32_t index = 0;
1015  for(uint32_t i = 0; i < Bitstream::eBlockTypeCount; i++) {
1016  // all frames of block type are extracted
1017  for(uint32_t j = 0; j < mBlockFrameIndexBounds[i]; j++) {
1019  (new VirtexFrame(getFrameLength(), &frameWords[index])));
1020  index += getFrameLength();
1021  }
1022  }
1023  }
1024 
1026  /// \todo If the packet size differs from the frame data size, we need to replace the
1027  /// entire packet.
1028  uint32_t frameLength = getFrameLength();
1029  typedef boost::shared_array<uint32_t> WordSharedArray;
1030  // walk the bitstream and find the (full) FDRI write packet
1031  Virtex5::iterator p = begin();
1032  Virtex5::iterator e = end();
1033  while(p < e) {
1034  const VirtexPacket& packet = *p++;
1035  if(packet.isType2() && packet.isWrite()) {
1036  WordSharedArray words = packet.getWords();
1037  uint32_t* ptr = words.get();
1038  for(uint32_t block = 0; block < 8; block++) {
1039  for(uint32_t frame = 0; frame < mBlockFrameIndexBounds[block]; frame++) {
1040  const VirtexFrameBlocks::word_t* words
1041  = mFrameBlocks.mBlock[block][frame]->getWords();
1042  for(uint32_t index = 0; index < frameLength; index++) *ptr++ = *words++;
1043  }
1044  }
1045  }
1046  }
1047  }
1048 
1049  /*
1050  void Virtex5::initializePartialFrameBlocks (void) {
1051  boost::shared_array<uint32_t> frameWords;
1052  //Walk the bitstream and extract all FAR and FDRI
1053  Virtex5::iterator p = begin();
1054  Virtex5::iterator e = end();
1055  Virtex5::FrameAddress far;
1056  uint32_t address;
1057  while(p < e) {
1058  const VirtexPacket& packet = *p++;
1059  if(packet.isType1() && packet.isWrite() && packet.getAddress() == eRegisterFAR) {
1060  address = packet[1];
1061  far.assign (address);
1062  //std::cout << "Far: " << far << std::endl;
1063  }
1064  if(packet.isType1() && packet.isWrite() && packet.getAddress() == eRegisterFDRI) {
1065  frameWords = packet.getWords();
1066  //uint32_t numFrames = packet.getWordCount() % getFrameLength();
1067  //mFrameBlocks.mBlock[far.mBlockType].push_back(VirtexFrameSet
1068  // (getFrameLength(), numFrames, frameWords, far));
1069  }
1070  }
1071  }
1072  */
1073 
1075  uint32_t inBitCol, uint32_t inBlockCount) {
1076  return getXdlFrames(inFrameRow + (inTopBottom == eFarBottom ? (mFrameRowCount >> 1) : 0),
1077  mBitColumnToXdlColumn[inBitCol], inBlockCount);
1078  }
1079 
1081  uint32_t& outBeginBit, uint32_t& outEndBit, uint32_t inBlockCount) {
1082  return getXdlFrames(inBitRow, mBitColumnToXdlColumn[inBitCol], outBeginBit, outEndBit,
1083  inBlockCount);
1084  }
1085 
1087  uint32_t inBlockCount) {
1088  return getXdlFrames(inFrameRow, mBitColumnToXdlColumn[inBitCol], inBlockCount);
1089  }
1090 
1092  uint32_t& outBeginBit, uint32_t& outEndBit, uint32_t inBlockCount) {
1093 
1094  // look up the frame row designator for this XDL row
1095  FrameRowDesignator designator = mXdlRowToFrameRowDesignator[inXdlRow];
1096 
1097  // by default we have no bit position information
1098  outBeginBit = outEndBit = 0;
1099  // look up the absolute frame row
1100  uint32_t absoluteFrameRow = designator.mFrameRow;
1101  if(designator.mTopBottom == eFarBottom) absoluteFrameRow += (mFrameRowCount >> 1);
1102 
1103  // look up the relative XDL row
1104  uint32_t relativeXdlRow = inXdlRow - designator.mXdlBaseRow;
1105  //std::cout << "inXdlRow: " << inXdlRow << std::endl;
1106  //std::cout << "inXdlCol: " << inXdlCol << std::endl;
1107  //std::cout << " designator.mTopBottom: " << designator.mTopBottom << std::endl;
1108  //std::cout << " designator.mFrameRow: " << designator.mFrameRow << std::endl;
1109  //std::cout << " designator.mXdlBaseRow: " << designator.mXdlBaseRow << std::endl;
1110  //std::cout << " absoluteFrameRow: " << absoluteFrameRow << std::endl;
1111  //std::cout << " relativeXdlRow: " << relativeXdlRow << std::endl;
1112 
1113  // provide bit information for the columns that we know
1114  uint32_t index = relativeXdlRow;
1115  //std::cout << " index: " << index << std::endl;
1116  //std::cout << " mDeviceInfo.getColumnTypes()[inXdlCol]: "
1117  // << mDeviceInfo.getColumnTypes()[inXdlCol] << std::endl;
1118  switch(mDeviceInfo.getColumnTypes()[inXdlCol]) {
1119  case eColumnTypeClb:
1120  case eColumnTypeInt:
1121  if(index == 0 || index == 11) break; // these tiles have no bits
1122  index--; // tile 0 has no bits
1123  outBeginBit = index * 64; // regular tiles are 64 bits long
1124  outEndBit = outBeginBit + 64;
1125  if(index > 11) {
1126  outBeginBit -= 32; // the clock word is 32 bits long
1127  outEndBit -= 32; // the clock word is 32 bits long
1128  }
1129  break;
1130  case eColumnTypeBram:
1131  if(index != 5 && index != 10 && index != 16 && index != 21) break;
1132  index -= 5;
1133  outBeginBit = index * 64; // regular tiles are 64 bits long
1134  outEndBit = outBeginBit + 320;
1135  if(index > 10) {
1136  outBeginBit -= 32; // the clock word is 32 bits long
1137  outEndBit -= 32; // the clock word is 32 bits long
1138  }
1139  break;
1140  default:
1141  break;
1142  }
1143 
1144  // invoke the function that really does the work
1145  return getXdlFrames(absoluteFrameRow, inXdlCol);
1146  }
1147 
1149  uint32_t inBlockCount) {
1150  if(inFrameRow > getFrameRowCount()) return VirtexFrameBlocks();
1151 
1152  // index and extract frames
1153  int32_t xdlColumnIndex[inBlockCount];
1154  int32_t xdlColumnBound[inBlockCount];
1155  for(uint32_t i = 0; i < inBlockCount; i++) {
1156  // adjust for the frame row
1157  uint32_t indexOffset = inFrameRow * mXdlColumnIndexes[i].back();
1158  // column Index of given frame index
1159  xdlColumnIndex[i] = mXdlColumnIndexes[i][inXdlCol] + indexOffset;
1160  // frame bounds for given column type
1161  xdlColumnBound[i] = mColumnDefs[mDeviceInfo.getColumnTypes()[inXdlCol]][i];
1162  //std::cout << " block: " << i << ", start: " << xdlColumnIndex[i] << ", width: "
1163  // << xdlColumnBound[i] << " ==== XDL column: " << inXdlCol << ", bit column: "
1164  // << mXdlColumnToBitColumn[inXdlCol] << std::endl;
1165  }
1166  // extract the tile frames for the specified FAR
1167  VirtexFrameBlocks frameBlocks;
1168  for(uint32_t i = 0; i < inBlockCount; i++) {
1169  int startIndex = xdlColumnIndex[i];
1170  for(int j = 0; j < xdlColumnBound[i]; j++)
1171  frameBlocks.mBlock[i].push_back(mFrameBlocks.mBlock[i][startIndex+j]);
1172  }
1173  return frameBlocks;
1174  }
1175 
1177  // INT columns "belong" with their corresponding primary column in the bitstream, so if the
1178  // caller hands us an INT column, we look for the next primary column to the right
1179  // if the caller passes in a primary column, we return it as is
1180  const ColumnTypeVector& columns = mDeviceInfo.getColumnTypes();
1181  if(columns[inXdlCol] != eColumnTypeInt) return inXdlCol;
1182  // otherwise loop and increment until we find a primary column
1183  uint32_t col = inXdlCol + 1;
1184  ColumnTypeVector::const_iterator p = columns.begin() + col;
1185  ColumnTypeVector::const_iterator e = columns.end();
1186  while(p < e) {
1187  if(*p != eColumnTypeEmpty) return col;
1188  col++; p++;
1189  }
1190  // we shouldn't get here, but if we do, the best thing is to return the original column
1191  return inXdlCol;
1192  }
1193 
1194 } // namespace bitstream
1195 } // namespace torc
ColumnDefVector mColumnDefs
Column type widths.
static const Subfield sMASK0[]
Control Mask Register (MASK) subfields.
Definition: Virtex5.hpp:134
FrameAddressToIndex mFrameAddressToIndex
Map of frame addressee to frame indexes.
Definition: Virtex5.hpp:361
DeviceInfo xc5vsx50t
virtual void initializeFrameMaps(void)
Initialize the maps between frame indexes and frame addresses.
Definition: Virtex5.cpp:528
static uint32_t makeSubfield(ERegister inRegister, const std::string &inSubfield, const std::string &inSetting)
Return the masked value for a subfield of the specified register.
Definition: Virtex5.cpp:355
DeviceInfo xc5vlx30t
Encapsulation of a tile row in an unsigned 16-bit integer.
TileTypeNameToColumnType mTileTypeNameToColumnType
#define VALUES
Definition: Virtex5.cpp:52
IndexVector mBitColumnIndexes[Virtex5::eFarBlockTypeCount]
Vector to store frame indexes of XDL columns.
Definition: Virtex5.hpp:363
DeviceInfo xc5vsx95t
Encapsulation of a tile column in an unsigned 16-bit integer.
DeviceInfo xc5vlx220
Device database, including complete wiring and logic support.
Definition: DDB.hpp:42
TileTypeCount getTileTypeCount(void) const
Returns the tile type count for this device.
Definition: Tiles.hpp:151
TileRow getRowCount(void) const
Returns the row count for this device.
Definition: Tiles.hpp:153
Header for the DirectoryTree class.
DeviceInfo xc5vfx30t
DeviceInfo xc5vlx155
DeviceInfo xc5vtx240t
DeviceInfo xc5vlx85t
VirtexFrameBlocks mFrameBlocks
Input Frame blocks.
static const char * sRegisterName[eRegisterCount]
Configuration register names.
Definition: Virtex5.hpp:120
EFarTopBottom
Frame Address Register top and bottom constants.
Definition: Virtex5.hpp:82
uint16_t getRowCount(void) const
Returns the row count.
Definition: DeviceInfo.hpp:112
Frame< uint32_t > VirtexFrame
Virtex frame type.
Definition: Frame.hpp:104
const TileInfo & getTileInfo(TileIndex inTileIndex) const
Returns the TileInfo object for the specified tile.
Definition: Tiles.hpp:137
static const Subfield sCOR0[]
Configuration Options Register 0 (COR) subfields.
Definition: Virtex5.hpp:124
static const Subfield sTIMER[]
Watchdog Timer Register (TIMER) subfields.
Definition: Virtex5.hpp:138
TileTypeIndexToColumnType mTileTypeIndexToColumnType
Static device information class for Xilinx bitstreams. This class facilitates the creation of frame ...
Definition: DeviceInfo.hpp:75
Header for the Virtex5 class.
DeviceInfo xc5vlx50t
FrameIndexToAddress mFrameIndexToAddress
Map of frame indexes to frame addresses.
Definition: Virtex5.hpp:359
EFarBlockType
Frame Address Register block type constants.
Definition: Virtex5.hpp:85
static const Subfield sCOR1[]
Configuration Options Register 1 (COR) subfields.
Definition: Virtex5.hpp:126
uint16_t getColCount(void) const
Returns the column count.
Definition: DeviceInfo.hpp:114
IndexVector mXdlColumnIndexes[Virtex5::eFarBlockTypeCount]
Vector to store frame indexes of Bitstream columns.
Definition: Virtex5.hpp:365
static const Subfield sSTAT[]
Status Register (STAT) subfields.
Definition: Virtex5.hpp:128
DeviceInfo xc5vsx35t
DeviceInfo xc5vfx130t
ERegister
Configuration register enumeration.
Definition: Virtex5.hpp:56
TileCount getTileCount(void) const
Returns the tile count for this device.
Definition: Tiles.hpp:149
EDevice mDevice
Bitstream device enumeration.
Frame row designator: top/bottom flag and row index.
Definition: Virtex5.hpp:331
std::string string
virtual VirtexPacketVector generateFullBitstreamPrefix(void)
Return a packet vector with the full bitstream prefix.
Definition: Virtex5.cpp:655
DeviceInfo xc5vlx330t
static const Subfield sCTL1[]
Control Register 1 (CTL) subfields.
Definition: Virtex5.hpp:132
boost::uint32_t uint32_t
Imported type name.
DeviceInfo xc5vsx240t
DeviceInfo xc5vlx155t
virtual uint32_t getFrameRowCount(void) const
Return the number of frame rows for the current device.
Definition: Virtex5.hpp:259
static const char * sPacketTypeName[ePacketTypeCount]
Packet type names.
Definition: Virtex5.hpp:116
std::map< uint32_t, FrameRowDesignator > mXdlRowToFrameRowDesignator
Map of XDL tile rows to frame designators.
Definition: Virtex5.hpp:373
VirtexFrame::word_t word_t
FrameSet word type.
Definition: FrameSet.hpp:85
DeviceInfo xc5vlx20t
static const char * sOpcodeName[eOpcodeCount]
Packet opcode names.
Definition: Virtex5.hpp:118
DeviceInfo mDeviceInfo
Device information.
DeviceInfo xc5vlx30
Tile map, tile type, and wire information for the family and device.
Definition: Tiles.hpp:36
DEPRECATED void updateFullFrameBlocks(void)
Transfers frame block data into the full bitstream frame packet.
Definition: Virtex5.cpp:1025
FrameSet< FRAME_TYPE > mBlock[Bitstream::eBlockTypeCount]
FrameSets for each of the eight block types.
Definition: FrameSet.hpp:88
DeviceInfo xc5vfx70t
DeviceInfo xc5vlx220t
Encapsulation of a tile count in an unsigned 32-bit integer.
static const char * sCommandName[eCommandCount]
Configuration command names.
Definition: Virtex5.hpp:122
Encapsulation of a tile within a device tile map.
Definition: TileInfo.hpp:33
static const Subfield sBOOTSTS[]
Boot History Status Register (BOOTSTS) subfields.
Definition: Virtex5.hpp:140
EBitstreamType
The bitstream type to generate. Use eBitstreamFull to fully reconfigure a device, eBitstreamTypePartialActive to partially reconfigure it while it continues to run, or eBitstreamTypePartialShutdown to partially recongifure it after shutting it down.
const char * getTileTypeName(TileTypeIndex inTileTypeIndex) const
Returns the tile type name for the given tile type index.
Definition: Tiles.hpp:164
uint32_t mBlockFrameIndexBounds[Virtex5::eFarBlockTypeCount]
Array to hold frame index boundaries for blocks.
Definition: Virtex5.hpp:367
const ColumnTypeVector & getColumnTypes(void) const
Returns the column type vector.
Definition: DeviceInfo.hpp:116
boost::filesystem::path path
const TileTypeIndex & getTypeIndex(void) const
Returns the tile type index for this tile.
Definition: TileInfo.hpp:92
DeviceInfo xc5vfx200t
virtual VirtexPacketVector generatePartialBitstreamPrefix(EBitstreamType inBitstreamType)
Return a packet vector with the partial bitstream prefix.
Definition: Virtex5.cpp:859
DeviceInfo xc5vlx85
VirtexFrameBlocks getXdlFrames(uint32_t inXdlRow, uint32_t inXdlCol, uint32_t &outBeginBit, uint32_t &outEndBit, uint32_t inBlockCount=eBlockTypeCount)
Returns frames for specified XDL tile coordinates. inXldRow The XDL row coordinate. inXdlCol The XDL column coordinate. outBeginBit The bit index of the beginning of the requested tile. outEndBit The bit index of the end of the requested tile. inBlockCount The highest block type requested (8 for Xilinx architectures).
Definition: Virtex5.cpp:1091
boost::shared_ptr< VirtexFrame > FrameSharedPtr
Shared pointer encapsulation of a Frame.
Definition: FrameSet.hpp:44
std::vector< VirtexPacket > VirtexPacketVector
Vector of Virtex packets.
EFarTopBottom mTopBottom
Top/bottom flag.
Definition: Virtex5.hpp:333
uint32_t mFrameRowCount
Number of frame rows.
Definition: Virtex5.hpp:371
static VirtexPacket makeType1Write(uint32_t inAddress, uint32_t inWord)
Construct a type 1 write packet.
static const Subfield sWBSTAR[]
Warm Boot Start Address Register (WBSTAR) subfields.
Definition: Virtex5.hpp:136
static const boost::filesystem::path & getWorkingPath(void)
Returns the absolute path to the working directory.
Encapsulation of a tile type count in an unsigned 16-bit integer.
DEPRECATED void initializeFullFrameBlocks(void)
Loads full bitstream frames into block data structure.
Definition: Virtex5.cpp:1004
const WordSharedArray getWords(void) const
brief Returns the raw packet words, including the header word.
DeviceInfo xc5vlx330
TileCol getColCount(void) const
Returns the column count for this device.
Definition: Tiles.hpp:155
boost::uint32_t uint32_t
Imported type name.
Definition: Virtex5.hpp:51
Encapsulation of a tile type index in an unsigned 16-bit integer.
EColumnType
Major column types.
Definition: Virtex5.hpp:97
VirtexFrameBlocks getBitstreamFrames(EFarTopBottom inTopBottom, uint32_t inFrameRow, uint32_t inBitCol, uint32_t inBlockCount=eBlockTypeCount)
Returns frames for specified bitstream tile column. inTopBottom The top or bottom half of the device...
Definition: Virtex5.cpp:1074
DeviceInfo xc5vfx100t
boost::uint16_t uint16_t
Imported type name.
DeviceInfo xc5vtx150t
Header for the DDB class.
DeviceInfo xc5vlx110t
FrameBlocks< VirtexFrame > VirtexFrameBlocks
Virtex frame blocks type.
Definition: FrameSet.hpp:91
std::map< uint32_t, uint32_t > mBitColumnToXdlColumn
Map of bitstream column indexes to XDL column indexes.
Definition: Virtex5.hpp:369
virtual VirtexPacketVector generatePartialBitstreamSuffix(EBitstreamType inBitstreamType)
Return a packet vector with the partial bitstream suffix.
Definition: Virtex5.cpp:941
Template base for encapsulated integers, to enforce strong typing.
void setDeviceInfo(const DeviceInfo &rhs)
Assign static device information for the current bitstream.
Bitstream packet for Virtex class architectures.
static uint32_t makeHeader(EPacketType inType, EOpcode inOpcode, uint32_t inAddress, uint32_t inCount)
Construct a packet header.
const char ** mValues
The allowable subfield values.
virtual VirtexPacketVector generateFullBitstreamSuffix(void)
Return a packet vector with the full bitstream suffix.
Definition: Virtex5.cpp:786
DeviceInfo xc5vlx110
uint32_t getPrimaryXdlColumn(uint32_t inXdlCol)
Returns the primary column corresponding to the given column. If immediately to the left of a BRAM...
Definition: Virtex5.cpp:1176
DeviceInfo xc5vlx50
TileIndex getTileIndex(TileRow inRow, TileCol inCol) const
Returns the tile index for the given [row,column] pair.
Definition: Tiles.hpp:161
virtual uint32_t getFrameLength(void) const
Return the frame length for the current device.
Definition: Virtex5.hpp:261
virtual uint32_t getRowPadFrames(void) const
Return the number of pad frames after each row.
Definition: Virtex5.hpp:263
WORD_TYPE word_t
Frame word type.
Definition: Frame.hpp:48
static const Subfield sCTL0[]
Control Register 0 (CTL) subfields.
Definition: Virtex5.hpp:130
virtual void initializeDeviceInfo(const std::string &inDeviceName)
Initialize the device information.
Definition: Virtex5.cpp:412
Device database types for Xilinx architectures.