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Spartan6.cpp
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15 
16 /// \file
17 /// \brief Source for the Spartan6 class.
18 
20 #include <iostream>
21 
22 namespace torc {
23 namespace bitstream {
24 
25  const char* Spartan6::sPacketTypeName[ePacketTypeCount] = {
26  "[UNKNOWN TYPE 0]", "TYPE1", "TYPE2", "[UNKNOWN TYPE 3]", "[UNKNOWN TYPE 4]",
27  "[UNKNOWN TYPE 5]", "[UNKNOWN TYPE 6]", "[UNKNOWN TYPE 7]"
28  };
29 
30  const char* Spartan6::sOpcodeName[eOpcodeCount] = {
31  "NOP", "READ", "WRITE", "RESERVED"
32  };
33 
34  const char* Spartan6::sRegisterName[eRegisterCount] = {
35  "CRC", "FARMAJ", "FARMIN", "FDRI", "FDRO", "CMD", "CTL", "MASK", "STAT", "LOUT", "COR1",
36  "COR2", "PWRDN_REG", "FLR", "IDCODE", "CWDT", "HC_OPT_REG", "[UNUSED REGISTER 17]", "CSBO",
37  "GENERAL1", "GENERAL2", "GENERAL3", "GENERAL4", "GENERAL5", "MODE_REG", "PU_GWE", "PU_GTS",
38  "MFWR", "CCLK_FREQ", "SEU_OPT", "EXP_SIGN", "RDBK_SIGN", "BOOSTS", "EYE_MASK", "CBC_REG"
39  };
40 
41  const char* Spartan6::sCommandName[eCommandCount] = {
42  "NULL", "WCFG", "MFW", "LFRM", "RCFG", "START", "[UNKNOWN COMMAND 6]", "RCRC", "AGHIGH",
43  "[UNKNOWN COMMAND 9]", "GRESTORE", "SHUTDOWN", "[UNKNOWN COMMAND 12]", "DESYNC", "IPROG"
44  };
45 
46 #define VALUES (const char*[])
47 
48  /// \see Configuration Options Register Description: UG380, v2.2, July 30, 2010, Table 5-36
49  const Bitstream::Subfield Spartan6::sCOR1[] = {
50  {0x0003, 0, "StartupClk", "SSCLKSRC", 0,
51  // bitgen: Cclk, UserClk, JtagClk
52  // config: 00:"CCLK", 01:"UserClk", 1x:"TCK"
53  VALUES{"Cclk", "UserClk", "JtagClk", "TCK", 0}},
54  {0x0004, 2, "DriveDone", "DRIVE_DONE", 0,
55  // bitgen: No, Yes
56  // config: 0:"DONE pin is open drain", 1:"DONE is actively driven high"
57  VALUES{"No", "Yes", 0}},
58  {0x0008, 3, "DonePipe", "DONE_PIPE", 0,
59  // bitgen: No, Yes
60  // config: 0:"No pipeline stage for DONEIN", 1:"Add pipeline stage for DONEIN"
61  VALUES{"No", "Yes", 0}},
62  {0x0010, 4, "CRC_Bypass", "CRC_BYPASS", 0,
63  // bitgen: n/a?
64  // config: Does not check against updated CRC
65  VALUES{"0", "1", 0}},
66  {0x1000, 15, "Drive_Awake", "DRIVE_AWAKE", 0,
67  // bitgen: n/a?
68  // config: 0:"Does not drive the awake pin, 1:"Actively drives the awake pin"
69  VALUES{"0", "1", 0}},
70  {0, 0, 0, 0, 0, 0}
71  };
72 
73 
74  /// \see Configuration Options Register Description: UG380, v2.2, July 30, 2010, Table 5-36
75  const Bitstream::Subfield Spartan6::sCOR2[] = {
76  {0x0007, 0, "GWE_cycle", "GWE_CYCLE", 6,
77  // bitgen: 6, 1, 2, 3, 4, 5, Done, Keep
78  // config: 001:"2", 010:"3", 011:"4", 100:"5", 101:"6"
79  VALUES{"[UNDEFINED 0]", "2", "3", "4", "5", "6", "[UNDEFINED 6]", "[UNDEFINED 7]", 0}},
80  {0x0038, 3, "GTS_cycle", "GTS_CYCLE", 5,
81  // bitgen: 5, 1, 2, 3, 4, 6, Done, Keep
82  // config: 001:"2", 010:"3", 011:"4", 100:"5", 101:"6"
83  VALUES{"[UNDEFINED 0]", "2", "3", "4", "5", "6", "[UNDEFINED 6]", "[UNDEFINED 7]", 0}},
84  {0x01c0, 6, "LCK_cycle", "LOCK_CYCLE", 7,
85  // bitgen: NoWait, 0, 1, 2, 3, 4, 5, 6
86  // config: 000:"1", 001:"2", 010:"3", 011:"4", 100:"5", 101:"6", 111:"NO_WAIT"
87  VALUES{"1", "2", "3", "4", "5", "6", "[UNDEFINED 6]", "NoWait", 0}},
88  {0x0E00, 9, "DONE_cycle", "DONE_CYCLE", 4,
89  // bitgen: 4, 1, 2, 3, 5, 6
90  // config: 001:"2", 010:"3", 011:"4", 100:"5", 101:"6"
91  VALUES{"[UNDEFINED 0]", "2", "3", "4", "5", "6", "[UNDEFINED 6]", "[UNDEFINED 7]", 0}},
92  {0x8000, 15, "Reset_on_err", "RESET_ON_ERROR", 0,
93  // bitgen: No, Yes
94  // config: 0:"Disable reset on error", 1:"Enable reset on error"
95  VALUES{"Disable", "Enable", 0}},
96  {0, 0, 0, 0, 0, 0}
97  };
98 
99  /// \see Status Register Description: UG380, v2.2, July 30, 2010, Table 5-35
100  /// \note The "bitgen" names attempt to mimic the general bitgen convention.
101  const Bitstream::Subfield Spartan6::sSTAT[] = {
102  {0x0001, 0, "CRC_error", "CRC_ERROR", 0,
103  // bitgen: n/a
104  // config: 0:"No CRC error", 1:"CRC error"
105  VALUES{"No", "Yes", 0}},
106  {0x0002, 1, "ID_error", "ID_ERROR", 0,
107  // bitgen: n/a
108  // config: IDCODE not validated while trying to write FDRI
109  VALUES{"No", "Yes", 0}},
110  {0x0004, 2, "DCM_locked", "DCM_LOCK", 0,
111  // bitgen: n/a
112  // config: 0:"DCMs not locked", 1:"DCMs are locked"
113  VALUES{"No", "Yes", 0}},
114  {0x0008, 3, "GTS_CFG", "GTS_CFG_B", 0,
115  // bitgen: n/a
116  // config: 0:"All I/Os are placed in high-Z state", 1:"All I/Os behave as configured"
117  VALUES{"No", "Yes", 0}},
118  {0x0010, 4, "GWE", "GWE", 0,
119  // bitgen: n/a
120  // config: Status of Global Write Enable
121  VALUES{"No", "Yes", 0}},
122  {0x0020, 5, "GWHIGH", "GWHIGH_B", 0,
123  // bitgen: n/a
124  // config: 0:"GHIGH_B asserted", 1:"GHIGH_B deasserted"
125  VALUES{"No", "Yes", 0}},
126  {0x0040, 6, "DEC_ERROR", "DEC_ERROR", 0,
127  // bitgen: n/a
128  // config: 0:"No DEC Error", 1:"DEC Error"
129  VALUES{"No", "Yes", 0}},
130  {0x0080, 7, "PART_SECURED", "PART_SECURED", 0,
131  // bitgen: n/a
132  // config: 0:"Decryption security not set", 1:"Decyrption security set"
133  VALUES{"No", "Yes", 0}},
134  {0x0100, 8, "HSWAPEN", "HSWAPEN", 0,
135  // bitgen: n/a
136  // config: HSWAPEN Status
137  VALUES{"No", "Yes", 0}},
138  {0x0800, 9, "Mode", "MODE", 0,
139  // bitgen: n/a
140  // config: Status of the MODE pins (M1, M0, 0)
141  VALUES{"MasterSerial", "SlaveSelectMap32", "[UNDEFINED 2]", "MasterSelectMap",
142  "[UNDEFINED 3]", "JTAG", "SlaveSelectMap8", "[UNDEFINED 6]", "SlaveSerial", 0}},
143  {0x1000, 12, "INIT", "INIT_B", 0,
144  // bitgen: n/a
145  // config: Value on INIT pin
146  VALUES{"Deasserted", "Asserted", 0}},
147  {0x2000, 13, "Done", "DONE", 0,
148  // bitgen: n/a
149  // config: Value on DONE pin
150  VALUES{"Deasserted", "Asserted", 0}},
151  {0x4000, 14, "IN_PWRDN", "IN_PWRDN", 0,
152  // bitgen: n/a
153  // config: Suspend status
154  VALUES{"No", "Yes", 0}},
155  {0x4000, 15, "SWWD_Strikeout", "SWWD_strikeout", 0,
156  // bitgen: n/a
157  // config: Indicates error to configure for reasons of failure to find
158  // the sync word within the Configuration WatchDog timer
159  // (CWDT) count, invalid IDCODE, or CRC error. See the
160  // BOOTSTS register for the specific cause of failure. INIT
161  // is pulled Low and SWWD_strikeout goes High.
162  VALUES{"No", "Yes", 0}},
163  {0, 0, 0, 0, 0, 0}
164  };
165 
166  /// \see Control Register Description: UG380, v2.2, July 30, 2010, Table 5-34
167  const Bitstream::Subfield Spartan6::sCTL[] = {
168  {0x0002, 1, "CRC_EXTSTAT_DISABLE", "CRC_EXTSTAT_DISABLE", 0,
169  // bitgen: n/a?
170  // config: 0:"CRC indicator disabled", 1:"CRC Indicator enabled"
171  VALUES{"0", "1", 0}},
172  {0x0004, 2, "USE_EFUSE_KEY", "USE_EFUSE_KEY", 0,
173  // bitgen: n/a?
174  // config: 0:"Use battery backed ram", 1:"Use eFuse key"
175  VALUES{"0", "1", 0}},
176  {0x0008, 3, "Persist", "PERSIST", 0,
177  // bitgen: No, Yes
178  // config: 0:"No (default)", 1:"Yes"
179  VALUES{"No", "Yes", 0}},
180  {0x0030, 4, "Security", "SBITS", 0,
181  // bitgen: None, Level1, Level2
182  // config: 00:"Read/Write OK (default)", 01:"Readback disabled", 1x:"Readback disabled,
183  // writing disabled except CRC register."
184  VALUES{"None", "Level1", "Level2", "Level2", 0}},
185  {0x0040, 6, "DEC", "DEC", 0,
186  // bitgen: No, Yes
187  // config: 0:"No Decryption (default)", 1:"Yes Decryption Used"
188  VALUES{"No", "Yes", 0}},
189  {0, 0, 0, 0, 0, 0}
190  };
191 
192  /// \see Control Mask Register Description: Inferred from Table 5-34
193  const Bitstream::Subfield Spartan6::sMASK[] = {
194  {0x0001, 0, "RESERVED", "RESERVED", 0, VALUES{"Protected", "Writable", 0}},
195  {0x0002, 1, "CRC_EXTSTAT_DISABLE", "CRC_EXTSTAT_DISABLE", 0,
196  VALUES{"Protected", "Writable", 0}},
197  {0x0004, 2, "USE_EFUSE_KEY", "USE_EFUSE_KEY", 0, VALUES{"Protected", "Writable", 0}},
198  {0x0008, 3, "Persist", "PERSIST", 0, VALUES{"Protected", "Writable", 0}},
199  {0x0030, 4, "Security", "SBITS", 0,
200  VALUES{"Protected", "[UNKNOWN 1]", "[UNKNOWN 2]", "Writable", 0}},
201  {0x0040, 6, "DEC", "DEC", 0, VALUES{"Protected", "Writable", 0}},
202  {0, 0, 0, 0, 0, 0}
203  };
204 
205  /// \see Suspend Register Description: UG380, v2.2, July 30, 2010, Table 5-37
206  const Bitstream::Subfield Spartan6::sPWRDN_REG[] = {
207  {0x0001, 0, "KEEP_SCLK", "KEEP_SCLK", 1,
208  // bitgen: n/a?
209  // config: 0:"Use MCCLK for startup sequence initiated by power-up", 1:"Use SSCLKSRC for
210  // startup sequence initiated by power-up"
211  VALUES{"0", "1", 0}},
212  {0x0004, 2, "EN_PWRDN", "EN_PWRDN", 0,
213  // bitgen: n/a?
214  // config: 0:"Suspend is disabled", 1:"Suspend is enabled"
215  VALUES{"0", "1", 0}},
216  {0x0010, 4, "EN_PGSR", "EN_PGSR", 0,
217  // bitgen: No, Yes
218  // config: 0:"No GSR pulse during return from suspend", 1:"Generate GSR pulse during
219  // return from suspend"
220  VALUES{"No", "Yes", 0}},
221  {0x0020, 5, "FILTER", "FILTER_B", 0,
222  // bitgen: n/a
223  // config: 0:"Suspend filter (300ns) on, 1:"Filter off"
224  VALUES{"0", "1", 0}},
225  {0x4000, 14, "EN_EYES", "EN_EYES", 0,
226  // bitgen: No, Yes
227  // config: 0:"Disable Multi-Pin Wake-up
228  VALUES{"Disable", "Enable", 0}},
229  {0, 0, 0, 0, 0, 0}
230  };
231 
232  /// \see HC_OPT_REG Register Description: UG380, v2.2, July 30, 2010, Table 5-40
233  const Bitstream::Subfield Spartan6::sHC_OPT_REG[] = {
234  {0x0040, 6, "INIT_SKIP", "INIT_SKIP", 0,
235  // bitgen: No, Yes
236  // config: 0:"Do not skip initialization", 1:"Skip initialization"
237  VALUES{"0", "1", 0}},
238  {0, 0, 0, 0, 0, 0}
239  };
240 
241  /// \see Mode Register Description: UG380, v2.2, July 30, 2010, Table 5-44
242  const Bitstream::Subfield Spartan6::sMODE_REG[] = {
243  {0x0080, 0, "BOOTVSEL", "BOOTVSEL", 0,
244  // bitgen: n/a?
245  // config: Read only
246  VALUES{"[READ ONLY]", 0}},
247  {0x0400, 8, "BOOTMODE", "BOOTMODE", 1,
248  // bitgen: n/a?
249  // config: x00: BOOTMODE<0>, x10: BOOTMODE<1>
250  VALUES{"0", "1", 0}},
251  {0x1000, 11, "BUSWIDTH", "BUSWIDTH", 0,
252  // bitgen: n/a?
253  // config: Buswidth setting to reboot
254  VALUES{"0", "1", "2", 0}},
255  {0x2000, 13, "NEW_MODE", "NEW_MODE", 0,
256  // bitgen: n/a
257  // config: 0:"Physical Mode", 1:"Bitstream mode"
258  VALUES{"No", "Yes", 0}},
259  {0, 0, 0, 0, 0, 0}
260  };
261 
262  /// \see BOOSTS Register Description: UG380, v2.2, July 30, 2010, Table 5-48
263  const Bitstream::Subfield Spartan6::sBOOSTS[] = {
264  {0x0001, 0, "VALID_0", "VALID_O", 0,
265  // bitgen: n/a?
266  // config: Status valid
267  VALUES{"0", "1", 0}},
268  {0x0002, 1, "FALLBACK_O", "FALLBACK_0", 0,
269  // bitgen: n/a?
270  // config: 0: Normal Configuration, 1: Fallback to golden bit stream address.
271  VALUES{"0", "1", 0}},
272  {0x0008, 3, "WTO_ERROR_0", "WTO_ERROR_0", 0,
273  // bitgen: n/a?
274  // config: Watch dog time-out error.
275  VALUES{"0", "1", 0}},
276  {0x0010, 4, "ID_ERROR_0", "ID_ERROR_0", 0,
277  // bitgen: n/a?
278  // config: IDCODE error.
279  VALUES{"0", "1", 0}},
280  {0x0020, 5, "CRC_ERROR_0", "CRC_ERROR_0", 0,
281  // bitgen: n/a?
282  // config: CRC error.
283  VALUES{"0", "1", 0}},
284  {0x0040, 6, "VALID_1", "VALID_1", 0,
285  // bitgen: n/a?
286  // config: Status valid
287  VALUES{"0", "1", 0}},
288  {0x0080, 7, "FALLBACK_1", "FALLBACK_1", 0,
289  // bitgen: n/a?
290  // config: 0: Normal Configuration, 1: Fallback to 00 address.
291  VALUES{"0", "1", 0}},
292  {0x0200, 9, "WTO_ERROR_1", "WTO_ERROR_1", 0,
293  // bitgen: n/a?
294  // config: Watch dog time-out error.
295  VALUES{"0", "1", 0}},
296  {0x0400, 10, "ID_ERROR_1", "ID_ERROR_1", 0,
297  // bitgen: n/a?
298  // config: IDCODE error.
299  VALUES{"0", "1", 0}},
300  {0x0800, 11, "CRC_ERROR_1", "CRC_ERROR_1", 0,
301  // bitgen: n/a?
302  // config: CRC error.
303  VALUES{"0", "1", 0}},
304  {0, 0, 0, 0, 0, 0}
305  };
306 
307  /// \see SEU_OPT Register Description: UG380, v2.2, July 30, 2010, Table 5-49
308  const Bitstream::Subfield Spartan6::sSEU_OPT[] = {
309  {0x0001, 0, "SEU_ENABLE", "SEU_ENABLE", 0,
310  // bitgen: n/a?
311  // config: SEU Detection Enable/Disable
312  VALUES{"DISABLE", "ENABLE", 0}},
313  {0x0002, 1, "GLUT_MASK", "GLUT_MASK", 1,
314  // bitgen: n/a?
315  // config: 0: Unmask, 1: Mask out LUTRAM/SRL
316  VALUES{"Unmask", "Mask LUTRAM/SRL", 0}},
317  {0x0008, 3, "SEU_RUN_ON_ERR", "SEU_RUN_ON_ERR", 0,
318  // bitgen: n/a?
319  // config: If SEU_ERR detected, keep running
320  VALUES{"Halt", "Run", 0}},
321  {0x0010, 4, "SEU_FREQ", "SEU_FREQ", 0,
322  // bitgen: n/a?
323  // config: BUS Clock frequency during SEU
324  VALUES{"1be", 0}},
325  {0, 0, 0, 0, 0, 0}
326  };
327 
328  /// \brief Return the masked value for a subfield of the specified register.
329  uint16_t Spartan6::makeSubfield(ERegister inRegister, const std::string& inSubfield,
330  const std::string& inSetting) {
331  const Subfield* subfields;
332  switch(inRegister) {
333  case eRegisterCOR1: subfields = sCOR1; break;
334  case eRegisterCOR2: subfields = sCOR2; break;
335  case eRegisterSTAT: subfields = sSTAT; break;
336  case eRegisterCTL: subfields = sCTL; break;
337  case eRegisterMASK: subfields = sMASK; break;
338  case eRegisterPWRDN_REG: subfields = sPWRDN_REG; break;
339  case eRegisterHC_OPT_REG: subfields = sHC_OPT_REG; break;
340  case eRegisterMODE_REG: subfields = sMODE_REG; break;
341  case eRegisterBOOSTS: subfields = sBOOSTS; break;
342  case eRegisterSEU_OPT: subfields = sSEU_OPT; break;
343  default: return 0;
344  }
345  for(uint16_t field = 0; subfields[field].mMask != 0; field++) {
346  const Subfield& subfield = subfields[field];
347  if(inSubfield != subfield.mBitgenName && inSubfield != subfield.mConfigGuideName)
348  continue;
349  const char** ptr = subfield.mValues;
350  for(uint32_t i = 0; *ptr != 0; i++, ptr++) {
351  if(inSetting == *ptr) return (i << subfield.mShift) & subfield.mMask;
352  }
353  }
354  return 0;
355  }
356 
357 
358 } // namespace bitstream
359 } // namespace torc
static const char * sCommandName[eCommandCount]
Configuration command names.
Definition: Spartan6.hpp:94
static const char * sOpcodeName[eOpcodeCount]
Packet opcode names.
Definition: Spartan6.hpp:90
static const Subfield sMASK[]
Control Mask Register (MASK) subfields.
Definition: Spartan6.hpp:104
static const Subfield sCOR2[]
Configuration Options Register 2 (COR2) subfields.
Definition: Spartan6.hpp:98
static const Subfield sCTL[]
Control Register 0 (CTL0) subfields.
Definition: Spartan6.hpp:102
static const Subfield sMODE_REG[]
Mode Register (Mode) subfields.
Definition: Spartan6.hpp:110
std::string string
Header for the Spartan6 class.
boost::uint32_t uint32_t
Imported type name.
static uint16_t makeSubfield(ERegister inRegister, const std::string &inSubfield, const std::string &inSetting)
Return the masked value for a subfield of the specified register.
Definition: Spartan6.cpp:329
static const char * sRegisterName[eRegisterCount]
Configuration register names.
Definition: Spartan6.hpp:92
#define VALUES
Definition: Spartan6.cpp:46
static const char * sPacketTypeName[ePacketTypeCount]
Packet type names.
Definition: Spartan6.hpp:88
static const Subfield sHC_OPT_REG[]
HC_OPT_REG Register (PWRDN_REG) subfields.
Definition: Spartan6.hpp:108
static const Subfield sSEU_OPT[]
SEU_OPT Register (SEU_OPT) subfields.
Definition: Spartan6.hpp:114
static const Subfield sCOR1[]
Configuration Options Register 1 (COR1) subfields.
Definition: Spartan6.hpp:96
ERegister
Configuration register enumeration.
Definition: Spartan6.hpp:43
static const Subfield sBOOSTS[]
BOOSTS Register (BOOSTS) subfields.
Definition: Spartan6.hpp:112
static const Subfield sSTAT[]
Status Register (STAT) subfields.
Definition: Spartan6.hpp:100
boost::uint16_t uint16_t
Imported type name.
static const Subfield sPWRDN_REG[]
Suspend Register (PWRDN_REG) subfields.
Definition: Spartan6.hpp:106
const char ** mValues
The allowable subfield values.