torc-master
 All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Friends Macros Pages
Virtex6.cpp
Go to the documentation of this file.
1 // Torc - Copyright 2011-2013 University of Southern California. All Rights Reserved.
2 // $HeadURL$
3 // $Id$
4 
5 // This program is free software: you can redistribute it and/or modify it under the terms of the
6 // GNU General Public License as published by the Free Software Foundation, either version 3 of the
7 // License, or (at your option) any later version.
8 //
9 // This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
10 // without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
11 // the GNU General Public License for more details.
12 //
13 // You should have received a copy of the GNU General Public License along with this program. If
14 // not, see <http://www.gnu.org/licenses/>.
15 
17 #include <iostream>
18 
19 
20 
21 /// \todo Warning: this will need to be moved elsewhere.
25 #include <fstream>
26 
27 
28 namespace torc {
29 namespace bitstream {
30 
31  const char* Virtex6::sPacketTypeName[ePacketTypeCount] = {
32  "[UNKNOWN TYPE 0]", "TYPE1", "TYPE2", "[UNKNOWN TYPE 3]", "[UNKNOWN TYPE 4]",
33  "[UNKNOWN TYPE 5]", "[UNKNOWN TYPE 6]", "[UNKNOWN TYPE 7]"
34  };
35 
36  const char* Virtex6::sOpcodeName[eOpcodeCount] = {
37  "NOP", "READ", "WRITE", "RESERVED"
38  };
39 
40  const char* Virtex6::sRegisterName[eRegisterCount] = {
41  "CRC", "FAR", "FDRI", "FDRO", "CMD", "CTL0", "MASK", "STAT", "LOUT", "COR0", "MFWR", "CBC",
42  "IDCODE", "AXSS", "COR1", "CSOB", "WBSTAR", "TIMER", "[UNKNOWN REG 18]",
43  "[UNKNOWN REG 19]", "[UNKNOWN REG 20]", "[UNKNOWN REG 21]", "BOOTSTS", "[UNKNOWN REG 23]",
44  "CTL1", "[UNKNOWN REG 25]", "DWC"
45  };
46 
47  const char* Virtex6::sCommandName[eCommandCount] = {
48  "NULL", "WCFG", "MFW", "DGHIGH/LFRM", "RCFG", "START", "RCAP", "RCRC", "AGHIGH", "SWITCH",
49  "GRESTORE", "SHUTDOWN", "GCAPTURE", "DESYNCH", "Reserved", "IPROG", "CRCC",
50  "LTIMER"
51  };
52 
53 #define VALUES (const char*[])
54 
55  /// \see Control Register 0 (CTL0): UG360, v3.2, November 1, 2010, Table 6-28.
56  const Bitstream::Subfield Virtex6::sCTL0[] = {
57  {0x00000001, 0, "GTS_USER_B", "GTS_USER_B", 0,
58  // bitgen: n/a?
59  // config: 0:"I/Os 3-stated", 1:"I/Os active"
60  VALUES{"IoDisabled", "IoActive", 0}},
61  {0x00000008, 3, "Persist", "PERSIST", 0,
62  // bitgen: No, Yes
63  // config: 0:"No (default)", 1:"Yes"
64  VALUES{"No", "Yes", 0}},
65  {0x00000030, 4, "Security", "SBITS", 0,
66  // bitgen: None, Level1, Level2
67  // config: 00:"Read/Write OK (default)", 01:"Readback disabled", 1x:"Both writes and
68  // read disabled."
69  VALUES{"None", "Level1", "Level2", "Level2", 0}},
70  {0x00000040, 6, "Encrypt", "DEC", 0,
71  // bitgen: No, Yes
72  // config: AES Decryptor enable bit
73  VALUES{"No", "Yes", 0}},
74  {0x00000080, 7, "FARSRC", "FARSRC", 0,
75  // bitgen: n/a
76  // config: 0: FAR, address of RBCRC, 1: EFAR, address of ECC error frame
77  VALUES{"FAR", "EFAR", 0}},
78  {0x00000100, 8, "GLUTMASK", "GLUTMASK", 0,
79  // bitgen: n/a
80  // config: 0:"Readback all 0s from SRL16 and Distributed RAM. Use with active device
81  // readback.", 1:"Readback dynamic values from SRL16 and Distributed RAM. Use with
82  // shutdown readback."
83  VALUES{"Masked", "Dynamic", 0}},
84  {0x00001000, 12, "OverTempPowerDown", "OverTempPowerDown", 0,
85  // bitgen: Disable, Enable
86  // config: Enables the System Monitor Over-Temperature power down.
87  VALUES{"Disable", "Enable", 0}},
88  {0x40000000, 30, "ICAP_sel", "ICAP_SEL", 0,
89  // bitgen: n/a
90  // config: 0:"Top ICAP Port Enabled (default)", 1:"Bottom ICAP Port Enabled"
91  VALUES{"Top", "Bottom", 0}},
92  {0x80000000, 31, "EFUSE_key", "EFUSE_KEY", 0,
93  // bitgen: n/a
94  // config: 0:"Battery-back RAM", 1:"eFUSE"
95  VALUES{"No", "Yes", 0}},
96  {0, 0, 0, 0, 0, 0}
97  };
98 
99  /// \see Control Register 0 (CTL0): UG360, v3.2, November 1, 2010, Table 6-28.
100  const Bitstream::Subfield Virtex6::sMASK0[] = {
101  {0x00000001, 0, "GTS_USER_B", "GTS_USER_B", 0, VALUES{"Protected", "Writable", 0}},
102  {0x00000008, 3, "Persist", "PERSIST", 0, VALUES{"Protected", "Writable", 0}},
103  {0x00000030, 4, "Security", "SBITS", 0,
104  VALUES{"Protected", "[UNKNOWN 1]", "[UNKNOWN 2]", "Writable", 0}},
105  {0x00000040, 6, "Encrypt", "DEC", 0, VALUES{"Protected", "Writable", 0}},
106  {0x00000080, 7, "FARSRC", "FARSRC", 0, VALUES{"Protected", "Writable", 0}},
107  {0x00000100, 8, "GLUTMASK", "GLUTMASK", 0, VALUES{"Protected", "Writable", 0}},
108  {0x00001000, 12, "OverTempPowerDown", "OverTempPowerDown", 0, VALUES{"Protected",
109  "Writable", 0}},
110  {0x40000000, 30, "ICAP_sel", "ICAP_SEL", 0, VALUES{"Protected", "Writable", 0}},
111  {0x80000000, 31, "EFUSE_key", "EFUSE_KEY", 0, VALUES{"Protected", "Writable", 0}},
112  {0, 0, 0, 0, 0, 0}
113  };
114 
115  /// \see Control Register 0 (CTL0): UG360, v3.2, November 1, 2010, Table 6-30.
116  const Bitstream::Subfield Virtex6::sCTL1[] = {
117  {0, 0, 0, 0, 0, 0}
118  };
119 
120  /// \see Control Register 0 (CTL0): UG360, v3.2, November 1, 2010, Table 6-35.
121  const Bitstream::Subfield Virtex6::sCOR0[] = {
122  {0x00000007, 0, "GWE_cycle", "GWE_CYCLE", 5,
123  // bitgen: 6, 1, 2, 3, 4, 5, Done, Keep
124  // config: 000:"1", 001:"2", 010:"3", 011:"4", 100:"5", 101:"6", 110:"GTS tracks DONE
125  // pin. BitGen option -g GTS_cycle:Done", 111:"Keep"
126  VALUES{"1", "2", "3", "4", "5", "6", "Done", "Keep", 0}},
127  {0x00000038, 3, "GTS_cycle", "GTS_CYCLE", 4,
128  // bitgen: 5, 1, 2, 3, 4, 6, Done, Keep
129  // config: 000:"1", 001:"2", 010:"3", 011:"4", 100:"5", 101:"6", 110:"GTS tracks DONE
130  // pin. BitGen option -g GTS_cycle:Done", 001[sic]:"Keep" but assuming 111:"Keep"
131  VALUES{"1", "2", "3", "4", "5", "6", "Done", "Keep", 0}},
132  {0x00000E00, 9, "Match_cycle", "MATCH_CYCLE", 0,
133  // bitgen: Auto, NoWait, 0, 1, 2, 3, 4, 5, 6
134  // config: 000:"0", 001:"1", 010:"2", 011:"3", 100:"4", 101:"5", 110:"6", 111:"KEEP"
135  VALUES{"0", "1", "2", "3", "4", "5", "6", "NoWait", 0}},
136  {0x00007000, 12, "DONE_cycle", "DONE_CYCLE", 3,
137  // bitgen: 4, 1, 2, 3, 5, 6
138  // config: 000:"1", 001:"2", 010:"3", 011:"4", 100:"5", 101:"6", 110:"7", 111:"KEEP"
139  VALUES{"1", "2", "3", "4", "5", "6", "7", "KEEP", 0}},
140  {0x00018000, 15, "StartupClk", "SSCLKSRC", 0,
141  // bitgen: Cclk, UserClk, JtagClk
142  // config: 00:"CCLK", 01:"UserClk", 1x:"JTAGClk"
143  VALUES{"Cclk", "UserClk", "JtagClk", "JtagClk", 0}},
144  {0x007e0000, 17, "ConfigRate", "OSCFSEL", 0,
145  // bitgen: 2, 6, 9, 13, 17, 20, 24, 27, 31, 35, 38, 42, 46, 49, 53, 56, 60
146  // config: values undefined
147  VALUES{
148  "[UNKNOWN 0]", "[UNKNOWN 1]", "[UNKNOWN 2]", "[UNKNOWN 3]",
149  "[UNKNOWN 4]", "[UNKNOWN 5]", "[UNKNOWN 6]", "[UNKNOWN 7]",
150  "[UNKNOWN 8]", "[UNKNOWN 9]", "[UNKNOWN 10]", "[UNKNOWN 11]",
151  "[UNKNOWN 12]", "[UNKNOWN 13]", "[UNKNOWN 14]", "[UNKNOWN 15]",
152  "[UNKNOWN 16]", "[UNKNOWN 17]", "[UNKNOWN 18]", "[UNKNOWN 19]",
153  "[UNKNOWN 20]", "[UNKNOWN 21]", "[UNKNOWN 22]", "[UNKNOWN 23]",
154  "[UNKNOWN 24]", "[UNKNOWN 25]", "[UNKNOWN 26]", "[UNKNOWN 27]",
155  "[UNKNOWN 28]", "[UNKNOWN 29]", "[UNKNOWN 30]", "[UNKNOWN 31]",
156  0}},
157  {0x00800000, 23, "Capture", "SINGLE", 0,
158  // bitgen: n/a -- this comes from the CAPTURE site ONESHOT setting
159  // config: 0:"Readback is not single-shot", 1:"Readback is single-shot"
160  VALUES{"Continuous", "OneShot", 0}},
161  {0x01000000, 24, "DriveDone", "DRIVE_DONE", 0,
162  // bitgen: No, Yes
163  // config: 0:"DONE pin is open drain", 1:"DONE is actively driven high"
164  VALUES{"No", "Yes", 0}},
165  {0x02000000, 25, "DonePipe", "DONE_PIPE", 0,
166  // bitgen: No, Yes
167  // config: 0:"No pipeline stage for DONEIN", 1:"Add pipeline stage for DONEIN"
168  VALUES{"No", "Yes", 0}},
169  {0x08000000, 27, "DONE_status", "PWRDWN_STAT", 0,
170  // bitgen: n/a?
171  // config: 0:"DONE pin", 1:"Powerdown pin"
172  VALUES{"DonePin", "PowerdownPin", 0}},
173  {0, 0, 0, 0, 0, 0}
174  };
175 
176  /// \see Configuration Options Register 1 (COR1): UG360, v3.2, November 1, 2010, Table 6-37.
177  const Bitstream::Subfield Virtex6::sCOR1[] = {
178  {0x00000003, 0, "BPI_page_size", "BPI_PAGE_SIZE", 0,
179  // bitgen: 1, 4, 8
180  // config: 00:"1 byte/word", 01:"4 bytes/words", 10:"8 bytes/words", 11:"Reserved"
181  VALUES{"1", "4", "8", "Reserved", 0}},
182  {0x0000000C, 2, "BPI_1st_read_cycle", "BPI_1ST_READ_CYCLES", 0,
183  // bitgen: 1, 2, 3, 4
184  // config: 00:"1", 01:"2", 10:"3", 11:"4"
185  VALUES{"1", "4", "8", "Reserved", 0}},
186  {0x00000100, 8, "ContinuousReadbackCRC", "RBCRC_EN", 0,
187  // bitgen: n/a?
188  // config: Continuous readback CRC enable
189  VALUES{"Disabled", "Enabled", 0}},
190  {0x00000200, 9, "InitAsCRCErrorPin", "RBCRC_NO_PIN", 0,
191  // bitgen: n/a?
192  // config: Disables INIT_B as read back CRC error status output pin
193  VALUES{"Disabled", "Enabled", 0}},
194  {0x00018000, 15, "ActionReadbackCRC", "RBCRC_ACTION", 0,
195  // bitgen: n/a?
196  // config: Action for readback CRC 00:"1", 01:"2", 10:"3", 11:"4"
197  VALUES{"Continue", "Halt", "CorrectAndHalt", "CorrectAndContinue", 0}},
198  {0x00020000, 17, "PersistDeassertAtDesynch", "PERSIST_DEASSERT_AT_DESYNCH", 0,
199  // bitgen: n/a?
200  // config: Enables deassertion of PERSIST with the DESYNCH command
201  VALUES{"Disabled", "Enabled", 0}},
202  {0, 0, 0, 0, 0, 0}
203  };
204 
205  /// \see WBSTAR Register Description: UG360, v3.2, November 1, 2010, Table 6-39.
206  const Bitstream::Subfield Virtex6::sWBSTAR[] = {
207  {0x18000000, 27, "NextRevisionSelect", "RS[1:0]", 0,
208  // config: RS[1:0] pin value on next warm boot
209  VALUES{"00", "01", "10", "11", 0}},
210  {0x04000000, 26, "RevisionSelectTristate", "RS_TS_B", 0,
211  // config: 0:"Disabled", 1:"Enabled"
212  VALUES{"Disabled", "Enabled", 0}},
213  {0, 0, 0, 0, 0, 0}
214  };
215 
216  /// \see TIMER Register Description: UG360, v3.2, November 1, 2010, Table 6-41.
217  const Bitstream::Subfield Virtex6::sTIMER[] = {
218  {0x01000000, 24, "TimerForConfig", "TIMER_CFG_MON", 0,
219  // config: 0:"Disabled", 1:"Enabled"
220  VALUES{"Disabled", "Enabled", 0}},
221  {0x02000000, 25, "TimerForUser", "TIMER_USR_MON", 0,
222  // config: 0:"Disabled", 1:"Enabled"
223  VALUES{"Disabled", "Enabled", 0}},
224  {0, 0, 0, 0, 0, 0}
225  };
226 
227  /// \see BOOTSTS Register Description: UG360, v3.2, November 1, 2010, Table 6-43.
228  const Bitstream::Subfield Virtex6::sBOOTSTS[] = {
229  {0x00000001, 0, "RegisterStatus0", "VALID_0", 0,
230  // config: Status valid
231  VALUES{"Valid", "Invalid", 0}},
232  {0x00000002, 1, "FallbackStatus0", "FALLBACK_0", 0,
233  // config: 0:"Normal configuration", 1:"Fallback to default reconfiguration, RS[1:0]
234  // actively drives 2'b00"
235  VALUES{"Normal", "Fallback", 0}},
236  {0x00000004, 2, "InternalTrigger0", "IPROG_0", 0,
237  // config: Internal PROG triggered configuration
238  VALUES{"External", "Internal", 0}},
239  {0x00000008, 3, "WatchdogTimeout0", "WTO_ERROR_0", 0,
240  // config: Watchdog time-out error
241  VALUES{"Valid", "Invalid", 0}},
242  {0x00000010, 4, "ID_error0", "ID_ERROR_0", 0,
243  // config: ID error
244  VALUES{"NoError", "Error", 0}},
245  {0x00000020, 5, "CRC_error0", "CRC_ERROR_0", 0,
246  // config: CRC error
247  VALUES{"NoError", "Error", 0}},
248  {0x00000040, 6, "BPI_wraparound_error0", "WRAP_ERROR_0", 0,
249  // config: BPI address counter wraparound error
250  VALUES{"NoError", "Error", 0}},
251  {0x00000100, 8, "RegisterStatus1", "VALID_1", 0,
252  // config: Status valid
253  VALUES{"Valid", "Invalid", 0}},
254  {0x00000200, 9, "FallbackStatus1", "FALLBACK_1", 0,
255  // config: 0:"Normal configuration", 1:"Fallback to default reconfiguration, RS[1:0]
256  // actively drives 2'b00"
257  VALUES{"Normal", "Fallback", 0}},
258  {0x00000400, 10, "InternalTrigger1", "IPROG_1", 0,
259  // config: Internal PROG triggered configuration
260  VALUES{"External", "Internal", 0}},
261  {0x00000800, 11, "WatchdogTimeout1", "WTO_ERROR_1", 0,
262  // config: Watchdog time-out error
263  VALUES{"Valid", "Invalid", 0}},
264  {0x00001000, 12, "ID_error1", "ID_ERROR_1", 0,
265  // config: ID error
266  VALUES{"NoError", "Error", 0}},
267  {0x00002000, 13, "CRC_error1", "CRC_ERROR_1", 0,
268  // config: CRC error
269  VALUES{"NoError", "Error", 0}},
270  {0x00004000, 14, "BPI_wraparound_error1", "WRAP_ERROR_1", 0,
271  // config: BPI address counter wraparound error
272  VALUES{"NoError", "Error", 0}},
273  {0, 0, 0, 0, 0, 0}
274  };
275 
276  /// \see Status Register Description: UG360, v3.2, November 1, 2010, Table 6-33.
277  const Bitstream::Subfield Virtex6::sSTAT[] = {
278  {0x00000001, 0, "CRC_error", "CRC_ERROR", 0,
279  // bitgen: n/a
280  // config: 0:"No CRC error", 1:"CRC error"
281  VALUES{"No", "Yes", 0}},
282  {0x00000002, 1, "DecryptorSecuritySet", "PART_SECURED", 0,
283  // bitgen: n/a
284  // config: 0:"Decryptor security not set", 1:"Decryptor security set"
285  VALUES{"No", "Yes", 0}},
286  {0x00000004, 2, "MMCM_locked", "MMCM_LOCK", 0,
287  // bitgen: n/a
288  // config: 0:"MMCMs not locked", 1:"MMCMs are locked"
289  VALUES{"No", "Yes", 0}},
290  {0x00000008, 3, "DCI_matched", "DCI_MATCH", 0,
291  // bitgen: n/a
292  // config: 0:"DCI not matched", 1:"DCI matched
293  VALUES{"No", "Yes", 0}},
294  {0x00000010, 4, "StartupFinished", "EOS", 0,
295  // bitgen: n/a
296  // config: 0:"Startup sequence has not finished", 1:"Startup sequence has finished"
297  VALUES{"No", "Yes", 0}},
298  {0x00000020, 5, "GTS_CFG_B", "GTS_CFG_B", 0,
299  // bitgen: n/a
300  // config: 0:"All I/Os are placed in high-Z state", 1:"All I/Os behave as configured"
301  VALUES{"IoDisabled", "IoEnabled", 0}},
302  {0x00000040, 6, "GWE", "GWE", 0,
303  // bitgen: n/a
304  // config: 0:"FFs and block RAM are write disabled", 1:"FFs and block RAM are write
305  // enabled"
306  VALUES{"WriteDisabled", "WriteEnabled", 0}},
307  {0x00000080, 7, "GHIGH_B", "GHIGH_B", 0,
308  // bitgen: n/a
309  // config: 0:"GHIGH_B asserted", 1:"GHIGH_B deasserted"
310  VALUES{"InterconnectDisabled", "InterconnectEnabled", 0}},
311  {0x00000700, 8, "Mode", "MODE", 0,
312  // bitgen: n/a
313  // config: Status of the MODE pins (M2:M0)
314  VALUES{"MasterSerial", "MasterSPI", "MasterBPI-Up", "MasterBPI-Down",
315  "MasterSelectMap", "JTAG", "SlaveSelectMap", "SlaveSerial", 0}},
316  {0x00000800, 11, "INIT_complete", "INIT_COMPLETE", 0,
317  // bitgen: n/a
318  // config: 0:"Initializations has not finished", 1:"Initialization finished"
319  VALUES{"No", "Yes", 0}},
320  {0x00001000, 12, "INIT_B", "INIT_B", 0,
321  // bitgen: n/a
322  // config: Value on INIT_B pin
323  VALUES{"Deasserted", "Asserted", 0}},
324  {0x00002000, 13, "DONE_released", "RELEASE_DONE", 0,
325  // bitgen: n/a
326  // config: 0:"DONE signal not released", 1:"DONE signal released"
327  VALUES{"DrivenLow", "Released", 0}},
328  {0x00004000, 14, "DONE", "DONE", 0,
329  // bitgen: n/a
330  // config: Value on DONE pin
331  VALUES{"NotDone", "Done", 0}},
332  {0x00008000, 15, "ID_error", "ID_ERROR", 0,
333  // bitgen: n/a
334  // config: 0:"No IE_ERROR", 1:"ID_ERROR"
335  VALUES{"NoError", "Error", 0}},
336  {0x00010000, 16, "Decrypt_error", "DEC_ERROR", 0,
337  // bitgen: n/a
338  // config: 0:"No DEC_ERROR", 1:"DEC_ERROR"
339  VALUES{"NoError", "Error", 0}},
340  {0x00020000, 17, "Decrypt_error", "SYSMON_OVER_TEMP", 0,
341  // bitgen: n/a
342  // config: 0:"No DEC_ERROR", 1:"DEC_ERROR"
343  VALUES{"NoError", "Error", 0}},
344  {0x001c0000, 18, "StartupState", "STARTUP_STATE", 0,
345  // bitgen: n/a
346  // config: 000:"0", 001:"1", 010:"3", 011:"2", 100:"7", 101:"6", 110:"4", 111:"5"
347  VALUES{"0", "1", "3", "2", "7", "6", "4", "5", 0}},
348  {0x01c00000, 22, "FlashTypeSelect", "FS", 0,
349  // bitgen: n/a
350  // config: SPI Flash type select
351  VALUES{0}},
352  {0x06000000, 25, "BusWidth", "BUS_WIDTH", 0,
353  // bitgen: n/a
354  // config: 00:"x1", 01:"x8", 10:"x16", 11:"x32"
355  VALUES{"1", "8", "16", "32", 0}},
356  {0x06000000, 28, "HswapenPin", "HSWAPEN_B", 0,
357  // bitgen: Pullup, Pulldown, Pullnone
358  // config: 0:"0", 1:"1"
359  VALUES{"0", "1", "16", "32", 0}},
360  {0, 0, 0, 0, 0, 0}
361  };
362 
363  /// \brief Return the masked value for a subfield of the specified register.
364  uint32_t Virtex6::makeSubfield(ERegister inRegister, const std::string& inSubfield,
365  const std::string& inSetting) {
366  const Subfield* subfields;
367  switch(inRegister) {
368  case eRegisterCOR0: subfields = sCOR0; break;
369  case eRegisterCOR1: subfields = sCOR1; break;
370  case eRegisterSTAT: subfields = sSTAT; break;
371  case eRegisterCTL0: subfields = sCTL0; break;
372  case eRegisterCTL1: subfields = sCTL1; break;
373  case eRegisterMASK: subfields = sMASK0; break;
374  case eRegisterWBSTAR: subfields = sWBSTAR; break;
375  case eRegisterTIMER: subfields = sTIMER; break;
376  case eRegisterBOOTSTS: subfields = sBOOTSTS; break;
377  default: return 0;
378  }
379  for(uint32_t field = 0; subfields[field].mMask != 0; field++) {
380  const Subfield& subfield = subfields[field];
381  if(inSubfield != subfield.mBitgenName && inSubfield != subfield.mConfigGuideName)
382  continue;
383  const char** ptr = subfield.mValues;
384  for(uint32_t i = 0; *ptr != 0; i++, ptr++) {
385  if(inSetting == *ptr) return (i << subfield.mShift) & subfield.mMask;
386  }
387  }
388  return 0;
389  }
390 
391 //#define GENERATE_STATIC_DEVICE_INFO
392 #ifndef GENERATE_STATIC_DEVICE_INFO
393 
394  extern DeviceInfo xc6vcx75t;
395  extern DeviceInfo xc6vcx130t;
396  extern DeviceInfo xc6vcx195t;
397  extern DeviceInfo xc6vcx240t;
398  extern DeviceInfo xc6vhx250t;
399  extern DeviceInfo xc6vhx255t;
400  extern DeviceInfo xc6vhx380t;
401  extern DeviceInfo xc6vhx565t;
402  extern DeviceInfo xc6vlx75t;
403  extern DeviceInfo xc6vlx130t;
404  extern DeviceInfo xc6vlx195t;
405  extern DeviceInfo xc6vlx240t;
406  extern DeviceInfo xc6vlx365t;
407  extern DeviceInfo xc6vlx550t;
408  extern DeviceInfo xc6vlx760;
409  extern DeviceInfo xc6vsx315t;
410  extern DeviceInfo xc6vsx475t;
411 
412  void Virtex6::initializeDeviceInfo(const std::string& inDeviceName) {
413  using namespace torc::common;
414  switch(mDevice) {
415  case eXC6VCX75T: setDeviceInfo(xc6vcx75t); break;
416  case eXC6VCX130T: setDeviceInfo(xc6vcx130t); break;
417  case eXC6VCX195T: setDeviceInfo(xc6vcx195t); break;
418  case eXC6VCX240T: setDeviceInfo(xc6vcx240t); break;
419  case eXC6VHX250T: setDeviceInfo(xc6vhx250t); break;
420  case eXC6VHX255T: setDeviceInfo(xc6vhx255t); break;
421  case eXC6VHX380T: setDeviceInfo(xc6vhx380t); break;
422  case eXC6VHX565T: setDeviceInfo(xc6vhx565t); break;
423  case eXC6VLX75T: setDeviceInfo(xc6vlx75t); break;
424  case eXC6VLX130T: setDeviceInfo(xc6vlx130t); break;
425  case eXC6VLX195T: setDeviceInfo(xc6vlx195t); break;
426  case eXC6VLX240T: setDeviceInfo(xc6vlx240t); break;
427  case eXC6VLX365T: setDeviceInfo(xc6vlx365t); break;
428  case eXC6VLX550T: setDeviceInfo(xc6vlx550t); break;
429  case eXC6VLX760: setDeviceInfo(xc6vlx760); break;
430  case eXC6VSX315T: setDeviceInfo(xc6vsx315t); break;
431  case eXC6VSX475T: setDeviceInfo(xc6vsx475t); break;
432  default: break;
433  }
434 
435  // update the top and bottom bitstream row counts as appropriate for the device
436  setRowCounts();
437  }
438 
439 #else
440 
441  void Virtex6::initializeDeviceInfo(const std::string& inDeviceName) {
442 
448 
449  // look up the device tile map
450  //mPrivateDeviceName = inDeviceName;
451  torc::architecture::DDB ddb(inDeviceName);
452  const torc::architecture::Tiles& tiles = ddb.getTiles();
453  uint32_t tileCount = tiles.getTileCount();
454  uint16_t rowCount = tiles.getRowCount();
455  uint16_t colCount = tiles.getColCount();
456  ColumnTypeVector columnTypes;
457 
458  // set up the tile index and name mappings, and the index to column def mapping
459  typedef std::map<TileTypeIndex, std::string> TileTypeIndexToName;
460  typedef std::map<std::string, TileTypeIndex> TileTypeNameToIndex;
461  TileTypeIndexToName tileTypeIndexToName;
462  TileTypeNameToIndex tileTypeNameToIndex;
463  TileTypeCount tileTypeCount = tiles.getTileTypeCount();
464  for(TileTypeIndex tileTypeIndex(0); tileTypeIndex < tileTypeCount; tileTypeIndex++) {
465  const std::string tileTypeName = tiles.getTileTypeName(tileTypeIndex);
466  tileTypeIndexToName[tileTypeIndex] = tileTypeName;
467  tileTypeNameToIndex[tileTypeName] = tileTypeIndex;
468  TileTypeNameToColumnType::iterator ttwp = mTileTypeNameToColumnType.find(tileTypeName);
469  TileTypeNameToColumnType::iterator ttwe = mTileTypeNameToColumnType.end();
470  if(ttwp != ttwe) mTileTypeIndexToColumnType[tileTypeIndex] = EColumnType(ttwp->second);
471 if(ttwp != ttwe) {
472  std::cout << "Mapping: " << tileTypeName << "(" << tileTypeIndex << ") = ColumnType " << ttwp->second << std::endl;
473 }
474  }
475 
476  // identify every column that contains known frames
477  columnTypes.resize(colCount);
478  mFrameRowCount = 0;
479  for(uint32_t blockType = 0; blockType < Virtex6::eFarBlockTypeCount; blockType++) {
480  for(TileCol col; col < colCount; col++) {
481 //std::cout << col << ": ";
482  columnTypes[col] = eColumnTypeEmpty;
483  TileTypeIndexToColumnType::iterator ttwe = mTileTypeIndexToColumnType.end();
484  TileTypeIndexToColumnType::iterator ttwp = ttwe;
485  for(TileRow row; row < rowCount; row++) {
486  // look up the tile info
487  const torc::architecture::TileInfo& tileInfo
488  = tiles.getTileInfo(tiles.getTileIndex(row, col));
489  TileTypeIndex tileTypeIndex = tileInfo.getTypeIndex();
490  // determine whether the tile type widths are defined
491  ttwp = mTileTypeIndexToColumnType.find(tileTypeIndex);
492  if(ttwp != ttwe) {
493  uint32_t width = mColumnDefs[ttwp->second][blockType];
494  mFrameRowCount += width;
495  //std::cout << " " << tiles.getTileTypeName(tileInfo.getTypeIndex())
496  // << ": " << width << " (" << mFrameRowCount << ")"
497  // << ">>>>>>>> " << tileInfo.getName() << " (" << tileInfo.getTypeIndex() << ") @" << row << "," << col << "" << std::endl;
498  columnTypes[col] = static_cast<EColumnType>(ttwp->second);
499  break;
500  }
501  }
502 //if(!found) std::cout << std::endl;
503  }
504  //std::cout << std::endl;
505  if(blockType == 2) break;
506  }
507 
509  boost::filesystem::path generatedMap = workingPath / (inDeviceName + ".map.csv");
510  std::fstream tilemapStream(generatedMap.string().c_str(), std::ios::out);
511  for(TileRow row; row < rowCount; row++) {
512  for(TileCol col; col < colCount; col++) {
513  const torc::architecture::TileInfo& tileInfo
514  = tiles.getTileInfo(tiles.getTileIndex(row, col));
515  TileTypeIndex tileTypeIndex = tileInfo.getTypeIndex();
516  tilemapStream << tiles.getTileTypeName(tileTypeIndex);
517  if(col + 1 < colCount) tilemapStream << ",";
518  }
519  tilemapStream << std::endl;
520  }
521  tilemapStream.close();
522 
523  // update bitstream device information
524  setDeviceInfo(DeviceInfo(tileCount, rowCount, colCount, columnTypes));
525  setRowCounts();
526  }
527 
528 #endif
529 
531  // The division between top and bottom rows can be determined by the locations of the
532  // CMT_BUFG_TOP and CMT_BUFG_BOTTOM tiles in the clock column. The number of clock regions
533  // above and including the CMT_BUFG_TOP tile determine the number of top rows in the
534  // bitstream. The number of clock regions below and including the CMT_BUFG_BOTTOM tile
535  // determine the number of bottom rows in the bitstream.
536  using namespace torc::common;
537  switch(mDevice) {
538  case eXC6VCX75T: mTopRowCount = 2; mBottomRowCount = 1; break;
539  case eXC6VCX130T: mTopRowCount = 2; mBottomRowCount = 3; break;
540  case eXC6VCX195T: mTopRowCount = 2; mBottomRowCount = 3; break;
541  case eXC6VCX240T: mTopRowCount = 3; mBottomRowCount = 3; break;
542  case eXC6VHX250T: mTopRowCount = 1; mBottomRowCount = 5; break;
543  case eXC6VHX255T: mTopRowCount = 4; mBottomRowCount = 2; break;
544  case eXC6VHX380T: mTopRowCount = 4; mBottomRowCount = 5; break;
545  case eXC6VHX565T: mTopRowCount = 4; mBottomRowCount = 5; break;
546  case eXC6VLX75T: mTopRowCount = 2; mBottomRowCount = 1; break;
547  case eXC6VLX130T: mTopRowCount = 2; mBottomRowCount = 3; break;
548  case eXC6VLX195T: mTopRowCount = 2; mBottomRowCount = 3; break;
549  case eXC6VLX240T: mTopRowCount = 3; mBottomRowCount = 3; break;
550  case eXC6VLX365T: mTopRowCount = 3; mBottomRowCount = 3; break;
551  case eXC6VLX550T: mTopRowCount = 4; mBottomRowCount = 5; break;
552  case eXC6VLX760: mTopRowCount = 4; mBottomRowCount = 5; break;
553  case eXC6VSX315T: mTopRowCount = 3; mBottomRowCount = 3; break;
554  case eXC6VSX475T: mTopRowCount = 4; mBottomRowCount = 5; break;
555  default: break;
556  }
557  }
558 
560 
561  bool debug = 0;
562  uint32_t farRowCount = ((mDeviceInfo.getRowCount() - 1) / 42) >> 1;
563  (void) farRowCount;
564  // the xc6vcx75t has 3 total FAR rows, 2 in the top half, and 1 in the bottom half
565  // the xc6vcx130t has 5 total FAR rows, 2 in the top half, and 3 in the bottom half
566  // the xc6vhx250t has 6 total FAR rows, 1 in the top half, and 5 in the bottom half
567  // similar exceptions exist in other devices, ...
568  uint32_t bottomRowCount = mBottomRowCount;
569  uint32_t topRowCount = mTopRowCount;
570  uint32_t frameIndex = 0;
571  for(uint32_t i = 0; i < Virtex6::eFarBlockTypeCount; i++) {
573  uint32_t blockFrameIndexBounds = 0;
574  //Set first frame index to 0
575  uint32_t bitIndex = 0;
576  uint32_t xdlIndex = 0;
577  mBitColumnIndexes[i].push_back(bitIndex);
578  mXdlColumnIndexes[i].push_back(xdlIndex);
579  bool blockUsed = false;
580  for(uint32_t half = 0; half < 2; half++) {
581  uint32_t rowCount = (half == eFarBottom ? bottomRowCount : topRowCount);
582  for(uint32_t farRow = 0; farRow < rowCount; farRow++) {
583  // build the columns
584  uint32_t farMajor = 0;
586  uint16_t finalColumn = mDeviceInfo.getColCount()-1;
587  uint32_t xdlColumnCount = 0;
588  uint32_t bitColumnCount = 0;
589  for(ColumnIndex col; col < mDeviceInfo.getColCount();
590  col++) {
591  uint32_t width = mColumnDefs[mDeviceInfo.getColumnTypes()[col]][i];
592  //Allocate the frame maps
593  for(uint32_t farMinor = 0; farMinor < width; farMinor++) {
594  Virtex6::FrameAddress far(Virtex6::EFarTopBottom(half), blockType,
595  farRow, farMajor, farMinor);
596  mFrameIndexToAddress[frameIndex] = far;
597  mFrameAddressToIndex[far] = frameIndex;
598  frameIndex++;
599  blockFrameIndexBounds++;
600  }
601  if(width > 0) {
602  farMajor++;
603  blockUsed = true;
604  }
605 
606  //Extract frame indexes for 1 row
607  if(farRow == 0 && half == 0) {
608  //Indexes for Bitstream Columns, only stores non-empty tile types
610  mXdlColumnToBitColumn[xdlColumnCount] = bitColumnCount;
611  bitColumnCount++;
612  bitIndex += width;
613  mBitColumnIndexes[i].push_back(bitIndex);
614  if(col == finalColumn) {
615  bitIndex += getRowPadFrames();
616  mBitColumnIndexes[i].push_back(bitIndex);
617  }
618  }
619  //Indexes for XDL Columns, stores interconnect and tile indexes for
620  //non-empty tiles
621  xdlIndex += width;
622  mXdlColumnIndexes[i].push_back(xdlIndex);
623  xdlColumnCount++;
624  if(col == finalColumn)
625  {
626  xdlIndex += getRowPadFrames();
627  mXdlColumnIndexes[i].push_back(xdlIndex);
628  }
629  }
630  }
631  // account for two pad frames after each frame row
632  if(blockUsed) {
633  frameIndex += getRowPadFrames();
634  blockFrameIndexBounds += getRowPadFrames();
635  }
636  if(debug) std::cout << "Last frame index: [" << i << ", " << frameIndex
637  << "]" << std::endl;
638  }
639  }
640  //stores frame index bounds for each block type
641  mBlockFrameIndexBounds[i] = blockFrameIndexBounds;
642  if(debug) std::cout << "***Block frame index bounds: " << mBlockFrameIndexBounds[i] << std::endl;
643  }
644  //Test to check proper indexing
645  if(debug) {
646  for(uint32_t i = 0; i < Virtex6::eFarBlockTypeCount; i++) {
647  for(uint32_t j = 0; j < mBitColumnIndexes[i].size(); j++)
648  std::cout << "Bit Value at index: (" << i << ", " << j << ") : " << mBitColumnIndexes[i][j] << std::endl;
649  for(uint32_t k = 0; k < mXdlColumnIndexes[i].size(); k++)
650  std::cout << "Xdl Value at index: (" << i << ", " << k << ") : " << mXdlColumnIndexes[i][k] << std::endl;
651  }
652  }
653  }
654 
656  // 0000005f: DUMMY
657  // 00000063: DUMMY
658  // 00000067: DUMMY
659  // 0000006b: DUMMY
660  // 0000006f: DUMMY
661  // 00000073: DUMMY
662  // 00000077: DUMMY
663  // 0000007b: DUMMY
664  // 0000007f: BUS WIDTH SYNC
665  // 00000083: BUS WIDTH DETECT
666  // 00000087: DUMMY
667  // 0000008b: DUMMY
668  // 0000008f: SYNC
669  // 00000093: NOP x 1
670  // 00000097: TYPE1 WRITE WBSTAR: 00000000 (RevisionSelectTristate:Disabled,
671  // NextRevisionSelect:00)
672  // 0000009f: TYPE1 WRITE CMD NULL
673  // 000000a7: NOP x 1
674  // 000000ab: TYPE1 WRITE CMD RCRC
675  // 000000b3: NOP x 2
676  // 000000bb: TYPE1 WRITE TIMER: 00000000 (TimerForUser:Disabled, TimerForConfig:Disabled)
677  // 000000c3: TYPE1 WRITE [UNKNOWN REG 19]: 00000000
678  // 000000cb: TYPE1 WRITE COR0: 00003fe5 (DONE_status:DonePin, DonePipe:No, DriveDone:No,
679  // Capture:Continuous, ConfigRate:[UNKNOWN 0], StartupClk:Cclk, DONE_cycle:4,
680  // Match_cycle:NoWait, GTS_cycle:5, GWE_cycle:6)
681  // 000000d3: TYPE1 WRITE COR1: 00000000 (PersistDeassertAtDesynch:Disabled,
682  // ActionReadbackCRC:Continue, InitAsCRCErrorPin:Disabled,
683  // ContinuousReadbackCRC:Disabled, BPI_1st_read_cycle:1, BPI_page_size:1)
684  // 000000db: TYPE1 WRITE IDCODE: 04250093
685  // 000000e3: TYPE1 WRITE CMD SWITCH
686  // 000000eb: NOP x 1
687  // 000000ef: TYPE1 WRITE MASK: 00000001 (EFUSE_key:Protected, ICAP_sel:Protected,
688  // OverTempPowerDown:Protected, GLUTMASK:Protected, FARSRC:Protected,
689  // Encrypt:Protected, Security:Protected, Persist:Protected,
690  // GTS_USER_B:Writable)
691  // 000000f7: TYPE1 WRITE CTL0: 00000101 (EFUSE_key:No, ICAP_sel:Top,
692  // OverTempPowerDown:Disable, GLUTMASK:Dynamic, FARSRC:FAR, Encrypt:No,
693  // Security:None, Persist:No, GTS_USER_B:IoActive)
694  // 000000ff: TYPE1 WRITE MASK: 00000000 ()
695  // 00000107: TYPE1 WRITE CTL1: 00000000 ()
696  // 0000010f: NOP x 8
697 
698  // declare the packet vector and define a NOP packet
699  typedef VirtexFrame::word_t word_t;
700  VirtexPacketVector packets;
703  // dummy words
704  packets.insert(packets.end(), 8, dummy);
705  // bus width detect
706  packets.push_back(VirtexPacket(eSynchronizationBusWidthSync));
707  packets.push_back(VirtexPacket(eSynchronizationBusWidthDetect));
708  packets.push_back(dummy);
709  packets.push_back(dummy);
710  // sync
711  packets.push_back(VirtexPacket(eSynchronizationSync));
712  packets.push_back(nop);
713  // warm boot register
714  packets.push_back(VirtexPacket::makeType1Write(eRegisterWBSTAR, 0));
715  // NULL command
717  packets.push_back(nop);
718  // reset CRC command
720  packets.push_back(nop);
721  packets.push_back(nop);
722  // watchdog timer
723  packets.push_back(VirtexPacket::makeType1Write(eRegisterTIMER, 0));
724  // undocumented register 19
725  packets.push_back(VirtexPacket::makeType1Write(19, 0));
726  // configuration options register 0
727  packets.push_back(VirtexPacket::makeType1Write(eRegisterCOR0,
728  makeSubfield(eRegisterCOR0, "DONE_status", "DonePin") |
729  makeSubfield(eRegisterCOR0, "DonePipe", "No") |
730  makeSubfield(eRegisterCOR0, "DriveDone", "No") |
731  makeSubfield(eRegisterCOR0, "Capture", "Continuous") |
732  makeSubfield(eRegisterCOR0, "ConfigRate", "[UNKNOWN 0]") |
733  makeSubfield(eRegisterCOR0, "StartupClk", "Cclk") |
734  makeSubfield(eRegisterCOR0, "DONE_cycle", "4") |
735  makeSubfield(eRegisterCOR0, "Match_cycle", "NoWait") |
736  makeSubfield(eRegisterCOR0, "GTS_cycle", "5") |
737  makeSubfield(eRegisterCOR0, "GWE_cycle", "6") |
738  0));
739  // configuration options register 1
740  packets.push_back(VirtexPacket::makeType1Write(eRegisterCOR1,
741  makeSubfield(eRegisterCOR1, "PersistDeassertAtDesynch", "Disabled") |
742  makeSubfield(eRegisterCOR1, "ActionReadbackCRC", "Continue") |
743  makeSubfield(eRegisterCOR1, "InitAsCRCErrorPin", "Disabled") |
744  makeSubfield(eRegisterCOR1, "ContinuousReadbackCRC", "Disabled") |
745  makeSubfield(eRegisterCOR1, "BPI_1st_read_cycle", "1") |
746  makeSubfield(eRegisterCOR1, "BPI_page_size", "1") |
747  0));
748  // write the ID code
749  packets.push_back(VirtexPacket::makeType1Write(eRegisterIDCODE, 0x00000000));
750  // clock and rate switch command
752  packets.push_back(nop);
753  // control register 0 mask
754  packets.push_back(VirtexPacket::makeType1Write(eRegisterMASK,
755  makeSubfield(eRegisterMASK, "EFUSE_key", "Protected") |
756  makeSubfield(eRegisterMASK, "ICAP_sel", "Protected") |
757  makeSubfield(eRegisterMASK, "OverTempPowerDown", "Protected") |
758  makeSubfield(eRegisterMASK, "GLUTMASK", "Protected") |
759  makeSubfield(eRegisterMASK, "FARSRC", "Protected") |
760  makeSubfield(eRegisterMASK, "Encrypt", "Protected") |
761  makeSubfield(eRegisterMASK, "Security", "Protected") |
762  makeSubfield(eRegisterMASK, "Persist", "Protected") |
763  makeSubfield(eRegisterMASK, "GTS_USER_B", "Writable") |
764  0));
765  // control register 0
766  packets.push_back(VirtexPacket::makeType1Write(eRegisterCTL0,
767  makeSubfield(eRegisterCTL0, "EFUSE_key", "NO") |
768  makeSubfield(eRegisterCTL0, "ICAP_sel", "Top") |
769  makeSubfield(eRegisterCTL0, "OverTempPowerDown", "Disable") |
770  makeSubfield(eRegisterCTL0, "GLUTMASK", "Dynamic") |
771  makeSubfield(eRegisterCTL0, "FARSRC", "FAR") |
772  makeSubfield(eRegisterCTL0, "Encrypt", "No") |
773  makeSubfield(eRegisterCTL0, "Security", "None") |
774  makeSubfield(eRegisterCTL0, "Persist", "No") |
775  makeSubfield(eRegisterCTL0, "GTS_USER_B", "IoActive") |
776  0));
777  // control register 1 mask
778  packets.push_back(VirtexPacket::makeType1Write(eRegisterMASK, 0));
779  // control register 1
780  packets.push_back(VirtexPacket::makeType1Write(eRegisterCTL1, 0));
781  // more NOPs
782  packets.insert(packets.end(), 8, nop);
783  // return the packet vector
784  return packets;
785  }
786 
788  // 008cd86b: TYPE1 WRITE CRC: 03aeb518
789  // 008cd873: NOP x 2
790  // 008cd87b: TYPE1 WRITE CMD GRESTORE
791  // 008cd883: NOP x 1
792  // 008cd887: TYPE1 WRITE CMD DGHIGH/LFRM
793  // 008cd88f: NOP x 100
794  // 008cda1f: TYPE1 WRITE CMD START
795  // 008cda27: NOP x 1
796  // 008cda2b: TYPE1 WRITE FAR: 00ef8000
797  // 008cda33: TYPE1 WRITE MASK: 00000101 (EFUSE_key:Protected, ICAP_sel:Protected,
798  // OverTempPowerDown:Protected, GLUTMASK:Writable, FARSRC:Protected,
799  // Encrypt:Protected, Security:Protected, Persist:Protected,
800  // GTS_USER_B:Writable)
801  // 008cda3b: TYPE1 WRITE CTL0: 00000101 (EFUSE_key:No, ICAP_sel:Top,
802  // OverTempPowerDown:Disable, GLUTMASK:Dynamic, FARSRC:FAR, Encrypt:No,
803  // Security:None, Persist:No, GTS_USER_B:IoActive)
804  // 008cda43: TYPE1 WRITE CRC: a82bb072
805  // 008cda4b: NOP x 2
806  // 008cda53: TYPE1 WRITE CMD DESYNCH
807  // 008cda5b: NOP x 400
808 
809  // declare the packet vector and define a NOP packet
810  typedef VirtexFrame::word_t word_t;
811  VirtexPacketVector packets;
813  // write a placeholder CRC value
814  packets.push_back(VirtexPacket::makeType1Write(eRegisterCRC, 0));
815  packets.push_back(nop);
816  packets.push_back(nop);
817  // restore command
819  packets.push_back(nop);
820  // last frame command
822  packets.insert(packets.end(), 100, nop);
823  // start command
825  packets.push_back(nop);
826  // frame address register
827  packets.push_back(VirtexPacket::makeType1Write(eRegisterFAR,
828  eFarMaskBlockType | eFarMaskRow)); // is this what the configuration controller wants?
829  // control register 0 mask
830  packets.push_back(VirtexPacket::makeType1Write(eRegisterMASK,
831  makeSubfield(eRegisterMASK, "EFUSE_key", "Protected") |
832  makeSubfield(eRegisterMASK, "ICAP_sel", "Protected") |
833  makeSubfield(eRegisterMASK, "OverTempPowerDown", "Protected") |
834  makeSubfield(eRegisterMASK, "GLUTMASK", "Protected") |
835  makeSubfield(eRegisterMASK, "FARSRC", "Protected") |
836  makeSubfield(eRegisterMASK, "Encrypt", "Protected") |
837  makeSubfield(eRegisterMASK, "Security", "Protected") |
838  makeSubfield(eRegisterMASK, "Persist", "Protected") |
839  makeSubfield(eRegisterMASK, "GTS_USER_B", "Writable") |
840  0));
841  // control register 0
842  packets.push_back(VirtexPacket::makeType1Write(eRegisterCTL0,
843  makeSubfield(eRegisterCTL0, "EFUSE_key", "NO") |
844  makeSubfield(eRegisterCTL0, "ICAP_sel", "Top") |
845  makeSubfield(eRegisterCTL0, "OverTempPowerDown", "Disable") |
846  makeSubfield(eRegisterCTL0, "GLUTMASK", "Dynamic") |
847  makeSubfield(eRegisterCTL0, "FARSRC", "FAR") |
848  makeSubfield(eRegisterCTL0, "Encrypt", "No") |
849  makeSubfield(eRegisterCTL0, "Security", "None") |
850  makeSubfield(eRegisterCTL0, "Persist", "No") |
851  makeSubfield(eRegisterCTL0, "GTS_USER_B", "IoActive") |
852  0));
853  // write the CRC value
854  packets.push_back(VirtexPacket::makeType1Write(eRegisterCRC, 0x00000000));
855  packets.push_back(nop);
856  packets.push_back(nop);
857  // desynch command
859  packets.insert(packets.end(), 400, nop);
860  // return the packet vector
861  return packets;
862  }
863 
865  // Packets marked S pertain to shutdown bitstreams only
866  // 0000005f: DUMMY
867  // 00000063: DUMMY
868  // 00000067: DUMMY
869  // 0000006b: DUMMY
870  // 0000006f: DUMMY
871  // 00000073: DUMMY
872  // 00000077: DUMMY
873  // 0000007b: DUMMY
874  // 0000007f: BUS WIDTH SYNC
875  // 00000083: BUS WIDTH DETECT
876  // 00000087: DUMMY
877  // 0000008b: DUMMY
878  // 0000008f: SYNC
879  // 00000093: NOP x 1
880  // 00000097: TYPE1 WRITE CMD RCRC
881  // 0000009f: NOP x 2
882  // 000000a7: TYPE1 WRITE IDCODE: 04250093
883  // S 000000af: TYPE1 WRITE COR0: 00003fe5 (DONE_status:DonePin, DonePipe:No,
884  // DriveDone:No, Capture:Continuous, ConfigRate:[UNKNOWN 0],
885  // StartupClk:Cclk, DONE_cycle:4, Match_cycle:NoWait, GTS_cycle:5,
886  // GWE_cycle:6)
887  // S 000000b7: TYPE1 WRITE CMD SHUTDOWN
888  // S 000000bf: NOP x 1
889  // S 000000c3: TYPE1 WRITE CRC: 8412163c
890  // S 000000cb: NOP x 4
891  // S 000000db: TYPE1 WRITE CMD AGHIGH
892  // S 000000e3: NOP x 1
893  // 000000e7: TYPE1 WRITE CMD NULL
894 
895  // declare the packet vector and define a NOP packet
896  typedef VirtexFrame::word_t word_t;
897  VirtexPacketVector packets;
900  // dummy words
901  packets.insert(packets.end(), 8, dummy);
902  // bus width detect
903  packets.push_back(VirtexPacket(eSynchronizationBusWidthSync));
904  packets.push_back(VirtexPacket(eSynchronizationBusWidthDetect));
905  packets.push_back(dummy);
906  packets.push_back(dummy);
907  // sync
908  packets.push_back(VirtexPacket(eSynchronizationSync));
909  packets.push_back(nop);
910  // reset CRC command
912  packets.push_back(nop);
913  packets.push_back(nop);
914  // write the ID code
915  packets.push_back(VirtexPacket::makeType1Write(eRegisterIDCODE, 0x00000000));
916  // extra for shutdown bitstreams
917  if(inBitstreamType == eBitstreamTypePartialShutdown) {
918  // configuration options register 0
919  packets.push_back(VirtexPacket::makeType1Write(eRegisterCOR0,
920  makeSubfield(eRegisterCOR0, "DONE_status", "DonePin") |
921  makeSubfield(eRegisterCOR0, "DonePipe", "No") |
922  makeSubfield(eRegisterCOR0, "DriveDone", "No") |
923  makeSubfield(eRegisterCOR0, "Capture", "Continuous") |
924  makeSubfield(eRegisterCOR0, "ConfigRate", "[UNKNOWN 0]") |
925  makeSubfield(eRegisterCOR0, "StartupClk", "Cclk") |
926  makeSubfield(eRegisterCOR0, "DONE_cycle", "4") |
927  makeSubfield(eRegisterCOR0, "Match_cycle", "NoWait") |
928  makeSubfield(eRegisterCOR0, "GTS_cycle", "5") |
929  makeSubfield(eRegisterCOR0, "GWE_cycle", "6") |
930  0));
931  // shutdown command
933  packets.push_back(nop);
934  // write the CRC value
935  packets.push_back(VirtexPacket::makeType1Write(eRegisterCRC, 0x00000000));
936  packets.insert(packets.end(), 4, nop);
937  // aghigh command
939  packets.push_back(nop);
940  }
941  // null command
943  // return the packet vector
944  return packets;
945  }
946 
948  // Packets marked S pertain to shutdown bitstreams only
949  // S 00000767: TYPE1 WRITE CMD GRESTORE
950  // S 0000076f: NOP x 1
951  // 00000773: TYPE1 WRITE MASK: 00001000 ()
952  // 0000077b: TYPE1 WRITE CTL1: 00000000 ()
953  // 00000783: TYPE1 WRITE CMD DGHIGH/LFRM
954  // 0000078b: NOP x 100
955  // S 0000091b: TYPE1 WRITE CMD GRESTORE
956  // S 00000923: NOP x 1
957  // S 00000927: TYPE1 WRITE CMD START
958  // S 0000092f: NOP x 1
959  // 00000933: TYPE1 WRITE FAR: 00ef8000
960  // 0000093b: TYPE1 WRITE CRC: 5a60db74
961  // 00000943: TYPE1 WRITE CMD DESYNCH
962  // 0000094b: NOP x 16
963 
964  // declare the packet vector and define a NOP packet
965  typedef VirtexFrame::word_t word_t;
966  VirtexPacketVector packets;
968  // extra for shutdown bitstreams
969  if(inBitstreamType == eBitstreamTypePartialShutdown) {
970  // restore command
972  packets.push_back(nop);
973  }
974  // control register 1 mask
975  packets.push_back(VirtexPacket::makeType1Write(eRegisterMASK,
976  0x00001000 /* this value is undocumented for CTL1 in the configuration guide */ |
977  0));
978  // control register 1
979  packets.push_back(VirtexPacket::makeType1Write(eRegisterCTL1,
980  0x00000000 /* this value is undocumented for CTL1 in the configuration guide */ |
981  0));
982  // last frame command
984  packets.insert(packets.end(), 100, nop);
985  // extra for shutdown bitstreams
986  if(inBitstreamType == eBitstreamTypePartialShutdown) {
987  // restore command
989  packets.push_back(nop);
990  // start command
992  packets.push_back(nop);
993  }
994  // frame address register
995  packets.push_back(VirtexPacket::makeType1Write(eRegisterFAR,
996  eFarMaskBlockType | eFarMaskRow)); // is this what the configuration controller wants?
997  // write the CRC value
998  packets.push_back(VirtexPacket::makeType1Write(eRegisterCRC, 0x00000000));
999  // desynch command
1001  packets.insert(packets.end(), 16, nop);
1002  // return the packet vector
1003  return packets;
1004  }
1005 
1007  boost::shared_array<uint32_t> frameWords;
1008  // walk the bitstream and extract all frames
1009  Virtex6::iterator p = begin();
1010  Virtex6::iterator e = end();
1011  while(p < e) {
1012  const VirtexPacket& packet = *p++;
1013  if(packet.isType2() && packet.isWrite())
1014  frameWords = packet.getWords();
1015  }
1016  uint32_t index = 0;
1017  for (uint32_t i = 0; i < Bitstream::eBlockTypeCount; i++) {
1018  // all frames of block type are extracted
1019  uint32_t padExtra = getRowPadFrames() * getFrameRowCount();
1020  for (uint32_t j = 0; j < mBlockFrameIndexBounds[i] + padExtra; j++) {
1022  (new VirtexFrame(getFrameLength(), &frameWords[index])));
1023  index += getFrameLength();
1024  }
1025  }
1026  }
1027 
1028  /*
1029  void Virtex6::initializePartialFrameBlocks (void) {
1030  boost::shared_array<uint32_t> frameWords;
1031  //Walk the bitstream and extract all FAR and FDRI
1032  Virtex6::iterator p = begin();
1033  Virtex6::iterator e = end();
1034  Virtex6::FrameAddress far;
1035  uint32_t address;
1036  while(p < e) {
1037  const VirtexPacket& packet = *p++;
1038  if(packet.isType1() && packet.isWrite() && packet.getAddress() == eRegisterFAR) {
1039  address = packet[1];
1040  far.assign (address);
1041  //std::cout << "Far: " << far << std::endl;
1042  }
1043  if(packet.isType1() && packet.isWrite() && packet.getAddress() == eRegisterFDRI) {
1044  frameWords = packet.getWords();
1045  //uint32_t numFrames = packet.getWordCount() % getFrameLength();
1046  //mFrameBlocks.mBlock[far.mBlockType].push_back(VirtexFrameSet
1047  // (getFrameLength(), numFrames, frameWords, far));
1048  }
1049  }
1050  }
1051  */
1052 
1054  uint32_t inFrameRow) {
1055  if(inFrameRow > getFrameRowCount()) return VirtexFrameBlocks();
1056 
1057  // index and extract frames
1058  int32_t bitColumnIndex[inBlockCount];
1059  int32_t bitColumnBound[inBlockCount];
1060  for(uint32_t i = 0; i < inBlockCount; i++) {
1061  // adjust for the frame row
1062  uint32_t lastIndex = mBitColumnIndexes[i].back();
1063  uint32_t indexOffset = inFrameRow * (lastIndex ? (lastIndex + getRowPadFrames()) : 0);
1064  // column Index of given frame index
1065  bitColumnIndex[i] = mBitColumnIndexes[i][inBitCol] + indexOffset;
1066  // frame bounds for given column type
1067  bitColumnBound[i] = mColumnDefs[mDeviceInfo.getColumnTypes()[inBitCol]][i];
1068  }
1069  // extract the tile frames for the specified FAR
1070  VirtexFrameBlocks frameBlocks;
1071  for(uint32_t i = 0; i < inBlockCount; i++) {
1072  int startIndex = bitColumnIndex[i];
1073  for(int j = 0; j < bitColumnBound[i]; j++)
1074  frameBlocks.mBlock[i].push_back(mFrameBlocks.mBlock[i][startIndex+j]);
1075  }
1076  return frameBlocks;
1077  }
1078 
1080  uint32_t inFrameRow) {
1081  if(inFrameRow > getFrameRowCount()) return VirtexFrameBlocks();
1082 
1083  // index and extract frames
1084  int32_t xdlColumnIndex[inBlockCount];
1085  int32_t xdlColumnBound[inBlockCount];
1086  for(uint32_t i = 0; i < inBlockCount; i++) {
1087  // adjust for the frame row
1088  uint32_t lastIndex = mXdlColumnIndexes[i].back();
1089  uint32_t indexOffset = inFrameRow * (lastIndex ? (lastIndex + getRowPadFrames()) : 0);
1090  // column Index of given frame index
1091  xdlColumnIndex[i] = mXdlColumnIndexes[i][inXdlCol] + indexOffset;
1092  // frame bounds for given column type
1093  xdlColumnBound[i] = mColumnDefs[mDeviceInfo.getColumnTypes()[inXdlCol]][i];
1094  //std::cout << " block: " << i << ", start: " << xdlColumnIndex[i] << ", width: "
1095  // << xdlColumnBound[i] << " ==== XDL column: " << inXdlCol << ", bit column: "
1096  // << mXdlColumnToBitColumn[inXdlCol] << std::endl;
1097  }
1098  // extract the tile frames for the specified FAR
1099  VirtexFrameBlocks frameBlocks;
1100  for(uint32_t i = 0; i < inBlockCount; i++) {
1101  int startIndex = xdlColumnIndex[i];
1102  for(int j = 0; j < xdlColumnBound[i]; j++)
1103  frameBlocks.mBlock[i].push_back(mFrameBlocks.mBlock[i][startIndex+j]);
1104  }
1105  return frameBlocks;
1106  }
1107 
1108 } // namespace bitstream
1109 } // namespace torc
ColumnDefVector mColumnDefs
Column type widths.
DeviceInfo xc6vhx250t
static const char * sOpcodeName[eOpcodeCount]
Packet opcode names.
Definition: Virtex6.hpp:114
virtual uint32_t getRowPadFrames(void) const
Return the number of pad frames after each row.
Definition: Virtex6.hpp:233
Encapsulation of a tile row in an unsigned 16-bit integer.
static const char * sPacketTypeName[ePacketTypeCount]
Packet type names.
Definition: Virtex6.hpp:112
TileTypeNameToColumnType mTileTypeNameToColumnType
DeviceInfo xc6vlx365t
Encapsulation of a tile column in an unsigned 16-bit integer.
Device database, including complete wiring and logic support.
Definition: DDB.hpp:42
IndexVector mBitColumnIndexes[Virtex6::eFarBlockTypeCount]
Vector to store frame indexes of XDL columns.
Definition: Virtex6.hpp:314
TileTypeCount getTileTypeCount(void) const
Returns the tile type count for this device.
Definition: Tiles.hpp:151
DeviceInfo xc6vlx195t
TileRow getRowCount(void) const
Returns the row count for this device.
Definition: Tiles.hpp:153
static const char * sRegisterName[eRegisterCount]
Configuration register names.
Definition: Virtex6.hpp:116
virtual VirtexPacketVector generateFullBitstreamPrefix(void)
Return a packet vector with the full bitstream prefix.
Definition: Virtex6.cpp:655
uint32_t mFrameRowCount
Number of frame rows.
Definition: Virtex6.hpp:322
static const Subfield sBOOTSTS[]
Boot History Status Register (BOOTSTS) subfields.
Definition: Virtex6.hpp:136
Header for the DirectoryTree class.
VirtexFrameBlocks mFrameBlocks
Input Frame blocks.
virtual VirtexPacketVector generatePartialBitstreamSuffix(EBitstreamType inBitstreamType)
Return a packet vector with the partial bitstream suffix.
Definition: Virtex6.cpp:947
IndexVector mXdlColumnIndexes[Virtex6::eFarBlockTypeCount]
Vector to store frame indexes of Bitstream columns.
Definition: Virtex6.hpp:316
uint16_t getRowCount(void) const
Returns the row count.
Definition: DeviceInfo.hpp:112
Frame< uint32_t > VirtexFrame
Virtex frame type.
Definition: Frame.hpp:104
const TileInfo & getTileInfo(TileIndex inTileIndex) const
Returns the TileInfo object for the specified tile.
Definition: Tiles.hpp:137
Header for the Virtex6 class.
FrameAddressToIndex mFrameAddressToIndex
Map of frame addressee to frame indexes.
Definition: Virtex6.hpp:312
TileTypeIndexToColumnType mTileTypeIndexToColumnType
Static device information class for Xilinx bitstreams. This class facilitates the creation of frame ...
Definition: DeviceInfo.hpp:75
VirtexFrameBlocks getBitstreamFrames(uint32_t inBlockCount, uint32_t inBitCol, uint32_t inFrameRow=0)
Returns frames for queried bitstream coordinates.
Definition: Virtex6.cpp:1053
uint16_t getColCount(void) const
Returns the column count.
Definition: DeviceInfo.hpp:114
DeviceInfo xc6vhx255t
static const Subfield sCOR0[]
Configuration Options Register 0 (COR) subfields.
Definition: Virtex6.hpp:120
virtual uint32_t getFrameRowCount(void) const
Return the number of frame rows for the current device.
Definition: Virtex6.hpp:229
DeviceInfo xc6vsx315t
FrameIndexToAddress mFrameIndexToAddress
Map of frame indexes to frame addresses.
Definition: Virtex6.hpp:310
static const Subfield sMASK0[]
Control Mask Register (MASK) subfields.
Definition: Virtex6.hpp:130
TileCount getTileCount(void) const
Returns the tile count for this device.
Definition: Tiles.hpp:149
EDevice mDevice
Bitstream device enumeration.
uint32_t mBlockFrameIndexBounds[Virtex6::eFarBlockTypeCount]
Array to hold frame index boundaries for blocks.
Definition: Virtex6.hpp:318
std::string string
static const Subfield sCOR1[]
Configuration Options Register 1 (COR) subfields.
Definition: Virtex6.hpp:122
uint32_t mShift
The subfield LSB position.
static const char * sCommandName[eCommandCount]
Configuration command names.
Definition: Virtex6.hpp:118
#define VALUES
Definition: Virtex6.cpp:53
const char * mConfigGuideName
The subfield name documented in the configuration guide.
boost::uint32_t uint32_t
Imported type name.
EColumnType
Major column types.
Definition: Virtex6.hpp:97
DeviceInfo xc6vcx75t
DeviceInfo xc6vlx75t
VirtexFrame::word_t word_t
FrameSet word type.
Definition: FrameSet.hpp:85
uint32_t mMask
The subfield bit mask.
DeviceInfo xc6vlx130t
DeviceInfo xc6vcx240t
static const Subfield sCTL1[]
Control Register 1 (CTL) subfields.
Definition: Virtex6.hpp:128
DeviceInfo xc6vlx240t
DeviceInfo mDeviceInfo
Device information.
Tile map, tile type, and wire information for the family and device.
Definition: Tiles.hpp:36
uint32_t mTopRowCount
The number of top bitstream rows.
Definition: Virtex6.hpp:138
ERegister
Configuration register enumeration.
Definition: Virtex6.hpp:56
DeviceInfo xc6vhx565t
FrameSet< FRAME_TYPE > mBlock[Bitstream::eBlockTypeCount]
FrameSets for each of the eight block types.
Definition: FrameSet.hpp:88
Encapsulation of a tile count in an unsigned 32-bit integer.
uint32_t mBottomRowCount
The number of bottom bitstream rows.
Definition: Virtex6.hpp:140
Encapsulation of a tile within a device tile map.
Definition: TileInfo.hpp:33
EBitstreamType
The bitstream type to generate. Use eBitstreamFull to fully reconfigure a device, eBitstreamTypePartialActive to partially reconfigure it while it continues to run, or eBitstreamTypePartialShutdown to partially recongifure it after shutting it down.
const char * getTileTypeName(TileTypeIndex inTileTypeIndex) const
Returns the tile type name for the given tile type index.
Definition: Tiles.hpp:164
const ColumnTypeVector & getColumnTypes(void) const
Returns the column type vector.
Definition: DeviceInfo.hpp:116
boost::filesystem::path path
const TileTypeIndex & getTypeIndex(void) const
Returns the tile type index for this tile.
Definition: TileInfo.hpp:92
void setRowCounts(void)
Set the number of top and bottom bitstream rows.
Definition: Virtex6.cpp:530
virtual VirtexPacketVector generatePartialBitstreamPrefix(EBitstreamType inBitstreamType)
Return a packet vector with the partial bitstream prefix.
Definition: Virtex6.cpp:864
DeviceInfo xc6vcx130t
static const Subfield sSTAT[]
Status Register (STAT) subfields.
Definition: Virtex6.hpp:124
boost::shared_ptr< VirtexFrame > FrameSharedPtr
Shared pointer encapsulation of a Frame.
Definition: FrameSet.hpp:44
std::vector< VirtexPacket > VirtexPacketVector
Vector of Virtex packets.
virtual uint32_t getFrameLength(void) const
Return the frame length for the current device.
Definition: Virtex6.hpp:231
EFarBlockType
Frame Address Register block type constants.
Definition: Virtex6.hpp:85
static VirtexPacket makeType1Write(uint32_t inAddress, uint32_t inWord)
Construct a type 1 write packet.
static uint32_t makeSubfield(ERegister inRegister, const std::string &inSubfield, const std::string &inSetting)
Return the masked value for a subfield of the specified register.
Definition: Virtex6.cpp:364
const char * mBitgenName
The subfield name documented in bitgen.
static const boost::filesystem::path & getWorkingPath(void)
Returns the absolute path to the working directory.
Encapsulation of a tile type count in an unsigned 16-bit integer.
const WordSharedArray getWords(void) const
brief Returns the raw packet words, including the header word.
EFarTopBottom
Frame Address Register top and bottom constants.
Definition: Virtex6.hpp:82
TileCol getColCount(void) const
Returns the column count for this device.
Definition: Tiles.hpp:155
Encapsulation of a tile type index in an unsigned 16-bit integer.
boost::uint16_t uint16_t
Imported type name.
Header for the DDB class.
FrameBlocks< VirtexFrame > VirtexFrameBlocks
Virtex frame blocks type.
Definition: FrameSet.hpp:91
DEPRECATED void initializeFullFrameBlocks(void)
Loads full bitstream frames into block data structure.
Definition: Virtex6.cpp:1006
virtual void initializeFrameMaps(void)
Initialize the maps between frame indexes and frame addresses. This is generally only useful for int...
Definition: Virtex6.cpp:559
Template base for encapsulated integers, to enforce strong typing.
DeviceInfo xc6vlx760
boost::uint32_t uint32_t
Imported type name.
Definition: Virtex6.hpp:51
DeviceInfo xc6vsx475t
void setDeviceInfo(const DeviceInfo &rhs)
Assign static device information for the current bitstream.
virtual void initializeDeviceInfo(const std::string &inDeviceName)
Initialize the device information.
Definition: Virtex6.cpp:412
Bitstream packet for Virtex class architectures.
static const Subfield sCTL0[]
Control Register 0 (CTL) subfields.
Definition: Virtex6.hpp:126
static uint32_t makeHeader(EPacketType inType, EOpcode inOpcode, uint32_t inAddress, uint32_t inCount)
Construct a packet header.
DeviceInfo xc6vcx195t
const char ** mValues
The allowable subfield values.
static const Subfield sWBSTAR[]
Warm Boot Start Address Register (WBSTAR) subfields.
Definition: Virtex6.hpp:132
std::map< uint32_t, uint32_t > mXdlColumnToBitColumn
Map of XDL column indexes to bitstream column indexes.
Definition: Virtex6.hpp:320
VirtexFrameBlocks getXdlFrames(uint32_t inBlockCount, uint32_t inXdlCol, uint32_t inFrameRow=0)
Returns frames for queried xdl coordinates.
Definition: Virtex6.cpp:1079
DeviceInfo xc6vlx550t
DeviceInfo xc6vhx380t
TileIndex getTileIndex(TileRow inRow, TileCol inCol) const
Returns the tile index for the given [row,column] pair.
Definition: Tiles.hpp:161
static const Subfield sTIMER[]
Watchdog Timer Register (TIMER) subfields.
Definition: Virtex6.hpp:134
virtual VirtexPacketVector generateFullBitstreamSuffix(void)
Return a packet vector with the full bitstream suffix.
Definition: Virtex6.cpp:787
WORD_TYPE word_t
Frame word type.
Definition: Frame.hpp:48
Device database types for Xilinx architectures.