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ioWriteVerilog.c
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1 /**CFile****************************************************************
2 
3  FileName [ioWriteVerilog.c]
4 
5  SystemName [ABC: Logic synthesis and verification system.]
6 
7  PackageName [Command processing package.]
8 
9  Synopsis [Procedures to output a special subset of Verilog.]
10 
11  Author [Alan Mishchenko]
12 
13  Affiliation [UC Berkeley]
14 
15  Date [Ver. 1.0. Started - June 20, 2005.]
16 
17  Revision [$Id: ioWriteVerilog.c,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
18 
19 ***********************************************************************/
20 
21 #include "ioAbc.h"
22 #include "base/main/main.h"
23 #include "map/mio/mio.h"
24 
25 ABC_NAMESPACE_IMPL_START
26 
27 
28 ////////////////////////////////////////////////////////////////////////
29 /// DECLARATIONS ///
30 ////////////////////////////////////////////////////////////////////////
31 
32 static void Io_WriteVerilogInt( FILE * pFile, Abc_Ntk_t * pNtk );
33 static void Io_WriteVerilogPis( FILE * pFile, Abc_Ntk_t * pNtk, int Start );
34 static void Io_WriteVerilogPos( FILE * pFile, Abc_Ntk_t * pNtk, int Start );
35 static void Io_WriteVerilogWires( FILE * pFile, Abc_Ntk_t * pNtk, int Start );
36 static void Io_WriteVerilogRegs( FILE * pFile, Abc_Ntk_t * pNtk, int Start );
37 static void Io_WriteVerilogLatches( FILE * pFile, Abc_Ntk_t * pNtk );
38 static void Io_WriteVerilogObjects( FILE * pFile, Abc_Ntk_t * pNtk );
39 static int Io_WriteVerilogWiresCount( Abc_Ntk_t * pNtk );
40 static char * Io_WriteVerilogGetName( char * pName );
41 
42 ////////////////////////////////////////////////////////////////////////
43 /// FUNCTION DEFINITIONS ///
44 ////////////////////////////////////////////////////////////////////////
45 
46 /**Function*************************************************************
47 
48  Synopsis [Write verilog.]
49 
50  Description []
51 
52  SideEffects []
53 
54  SeeAlso []
55 
56 ***********************************************************************/
57 void Io_WriteVerilog( Abc_Ntk_t * pNtk, char * pFileName )
58 {
59  Abc_Ntk_t * pNetlist;
60  FILE * pFile;
61  int i;
62  // can only write nodes represented using local AIGs
63  if ( !Abc_NtkIsAigNetlist(pNtk) && !Abc_NtkIsMappedNetlist(pNtk) )
64  {
65  printf( "Io_WriteVerilog(): Can produce Verilog for mapped or AIG netlists only.\n" );
66  return;
67  }
68  // start the output stream
69  pFile = fopen( pFileName, "w" );
70  if ( pFile == NULL )
71  {
72  fprintf( stdout, "Io_WriteVerilog(): Cannot open the output file \"%s\".\n", pFileName );
73  return;
74  }
75 
76  // write the equations for the network
77  fprintf( pFile, "// Benchmark \"%s\" written by ABC on %s\n", pNtk->pName, Extra_TimeStamp() );
78  fprintf( pFile, "\n" );
79 
80  // write modules
81  if ( pNtk->pDesign )
82  {
83  // write the network first
84  Io_WriteVerilogInt( pFile, pNtk );
85  // write other things
86  Vec_PtrForEachEntry( Abc_Ntk_t *, pNtk->pDesign->vModules, pNetlist, i )
87  {
88  assert( Abc_NtkIsNetlist(pNetlist) );
89  if ( pNetlist == pNtk )
90  continue;
91  fprintf( pFile, "\n" );
92  Io_WriteVerilogInt( pFile, pNetlist );
93  }
94  }
95  else
96  {
97  Io_WriteVerilogInt( pFile, pNtk );
98  }
99 
100  fprintf( pFile, "\n" );
101  fclose( pFile );
102 }
103 
104 /**Function*************************************************************
105 
106  Synopsis [Writes verilog.]
107 
108  Description []
109 
110  SideEffects []
111 
112  SeeAlso []
113 
114 ***********************************************************************/
115 void Io_WriteVerilogInt( FILE * pFile, Abc_Ntk_t * pNtk )
116 {
117  // write inputs and outputs
118 // fprintf( pFile, "module %s ( gclk,\n ", Abc_NtkName(pNtk) );
119  fprintf( pFile, "module %s ( ", Io_WriteVerilogGetName(Abc_NtkName(pNtk)) );
120  // add the clock signal if it does not exist
121  if ( Abc_NtkLatchNum(pNtk) > 0 && Nm_ManFindIdByName(pNtk->pManName, "clock", ABC_OBJ_PI) == -1 )
122  fprintf( pFile, "clock, " );
123  // write other primary inputs
124  fprintf( pFile, "\n " );
125  if ( Abc_NtkPiNum(pNtk) > 0 )
126  {
127  Io_WriteVerilogPis( pFile, pNtk, 3 );
128  fprintf( pFile, ",\n " );
129  }
130  if ( Abc_NtkPoNum(pNtk) > 0 )
131  Io_WriteVerilogPos( pFile, pNtk, 3 );
132  fprintf( pFile, " );\n" );
133  // add the clock signal if it does not exist
134  if ( Abc_NtkLatchNum(pNtk) > 0 && Nm_ManFindIdByName(pNtk->pManName, "clock", ABC_OBJ_PI) == -1 )
135  fprintf( pFile, " input clock;\n" );
136  // write inputs, outputs, registers, and wires
137  if ( Abc_NtkPiNum(pNtk) > 0 )
138  {
139 // fprintf( pFile, " input gclk," );
140  fprintf( pFile, " input " );
141  Io_WriteVerilogPis( pFile, pNtk, 10 );
142  fprintf( pFile, ";\n" );
143  }
144  if ( Abc_NtkPoNum(pNtk) > 0 )
145  {
146  fprintf( pFile, " output" );
147  Io_WriteVerilogPos( pFile, pNtk, 5 );
148  fprintf( pFile, ";\n" );
149  }
150  // if this is not a blackbox, write internal signals
151  if ( !Abc_NtkHasBlackbox(pNtk) )
152  {
153  if ( Abc_NtkLatchNum(pNtk) > 0 )
154  {
155  fprintf( pFile, " reg" );
156  Io_WriteVerilogRegs( pFile, pNtk, 4 );
157  fprintf( pFile, ";\n" );
158  }
159  if ( Io_WriteVerilogWiresCount(pNtk) > 0 )
160  {
161  fprintf( pFile, " wire" );
162  Io_WriteVerilogWires( pFile, pNtk, 4 );
163  fprintf( pFile, ";\n" );
164  }
165  // write nodes
166  Io_WriteVerilogObjects( pFile, pNtk );
167  // write registers
168  if ( Abc_NtkLatchNum(pNtk) > 0 )
169  Io_WriteVerilogLatches( pFile, pNtk );
170  }
171  // finalize the file
172  fprintf( pFile, "endmodule\n\n" );
173 }
174 
175 /**Function*************************************************************
176 
177  Synopsis [Writes the primary inputs.]
178 
179  Description []
180 
181  SideEffects []
182 
183  SeeAlso []
184 
185 ***********************************************************************/
186 void Io_WriteVerilogPis( FILE * pFile, Abc_Ntk_t * pNtk, int Start )
187 {
188  Abc_Obj_t * pTerm, * pNet;
189  int LineLength;
190  int AddedLength;
191  int NameCounter;
192  int i;
193 
194  LineLength = Start;
195  NameCounter = 0;
196  Abc_NtkForEachPi( pNtk, pTerm, i )
197  {
198  pNet = Abc_ObjFanout0(pTerm);
199  // get the line length after this name is written
200  AddedLength = strlen(Io_WriteVerilogGetName(Abc_ObjName(pNet))) + 2;
201  if ( NameCounter && LineLength + AddedLength + 3 > IO_WRITE_LINE_LENGTH )
202  { // write the line extender
203  fprintf( pFile, "\n " );
204  // reset the line length
205  LineLength = 3;
206  NameCounter = 0;
207  }
208  fprintf( pFile, " %s%s", Io_WriteVerilogGetName(Abc_ObjName(pNet)), (i==Abc_NtkPiNum(pNtk)-1)? "" : "," );
209  LineLength += AddedLength;
210  NameCounter++;
211  }
212 }
213 
214 /**Function*************************************************************
215 
216  Synopsis [Writes the primary outputs.]
217 
218  Description []
219 
220  SideEffects []
221 
222  SeeAlso []
223 
224 ***********************************************************************/
225 void Io_WriteVerilogPos( FILE * pFile, Abc_Ntk_t * pNtk, int Start )
226 {
227  Abc_Obj_t * pTerm, * pNet, * pSkip;
228  int LineLength;
229  int AddedLength;
230  int NameCounter;
231  int i;
232  int nskip;
233 
234  pSkip = 0;
235  nskip = 0;
236 
237  LineLength = Start;
238  NameCounter = 0;
239  Abc_NtkForEachPo( pNtk, pTerm, i )
240  {
241  pNet = Abc_ObjFanin0(pTerm);
242 
243  if ( Abc_ObjIsPi(Abc_ObjFanin0(pNet)) )
244  {
245  // Skip this output since it is a feedthrough -- the same
246  // name will appear as an input and an output which other
247  // tools reading verilog do not like.
248 
249  nskip++;
250  pSkip = pNet; // save an example of skipped net
251  continue;
252  }
253 
254  // get the line length after this name is written
255  AddedLength = strlen(Io_WriteVerilogGetName(Abc_ObjName(pNet))) + 2;
256  if ( NameCounter && LineLength + AddedLength + 3 > IO_WRITE_LINE_LENGTH )
257  { // write the line extender
258  fprintf( pFile, "\n " );
259  // reset the line length
260  LineLength = 3;
261  NameCounter = 0;
262  }
263  fprintf( pFile, " %s%s", Io_WriteVerilogGetName(Abc_ObjName(pNet)), (i==Abc_NtkPoNum(pNtk)-1)? "" : "," );
264  LineLength += AddedLength;
265  NameCounter++;
266  }
267 
268  if (nskip != 0)
269  {
270  assert (pSkip);
271  printf( "Io_WriteVerilogPos(): Omitted %d feedthrough nets from output list of module (e.g. %s).\n", nskip, Abc_ObjName(pSkip) );
272  return;
273  }
274 
275 }
276 
277 /**Function*************************************************************
278 
279  Synopsis [Writes the wires.]
280 
281  Description []
282 
283  SideEffects []
284 
285  SeeAlso []
286 
287 ***********************************************************************/
288 void Io_WriteVerilogWires( FILE * pFile, Abc_Ntk_t * pNtk, int Start )
289 {
290  Abc_Obj_t * pObj, * pNet, * pBox, * pTerm;
291  int LineLength;
292  int AddedLength;
293  int NameCounter;
294  int i, k, Counter, nNodes;
295 
296  // count the number of wires
297  nNodes = Io_WriteVerilogWiresCount( pNtk );
298 
299  // write the wires
300  Counter = 0;
301  LineLength = Start;
302  NameCounter = 0;
303  Abc_NtkForEachNode( pNtk, pObj, i )
304  {
305  if ( i == 0 )
306  continue;
307  pNet = Abc_ObjFanout0(pObj);
308  if ( Abc_ObjFanoutNum(pNet) > 0 && Abc_ObjIsCo(Abc_ObjFanout0(pNet)) )
309  continue;
310  Counter++;
311  // get the line length after this name is written
312  AddedLength = strlen(Io_WriteVerilogGetName(Abc_ObjName(pNet))) + 2;
313  if ( NameCounter && LineLength + AddedLength + 3 > IO_WRITE_LINE_LENGTH )
314  { // write the line extender
315  fprintf( pFile, "\n " );
316  // reset the line length
317  LineLength = 3;
318  NameCounter = 0;
319  }
320  fprintf( pFile, " %s%s", Io_WriteVerilogGetName(Abc_ObjName(pNet)), (Counter==nNodes)? "" : "," );
321  LineLength += AddedLength;
322  NameCounter++;
323  }
324  Abc_NtkForEachLatch( pNtk, pObj, i )
325  {
326  pNet = Abc_ObjFanin0(Abc_ObjFanin0(pObj));
327  Counter++;
328  // get the line length after this name is written
329  AddedLength = strlen(Io_WriteVerilogGetName(Abc_ObjName(pNet))) + 2;
330  if ( NameCounter && LineLength + AddedLength + 3 > IO_WRITE_LINE_LENGTH )
331  { // write the line extender
332  fprintf( pFile, "\n " );
333  // reset the line length
334  LineLength = 3;
335  NameCounter = 0;
336  }
337  fprintf( pFile, " %s%s", Io_WriteVerilogGetName(Abc_ObjName(pNet)), (Counter==nNodes)? "" : "," );
338  LineLength += AddedLength;
339  NameCounter++;
340  }
341  Abc_NtkForEachBox( pNtk, pBox, i )
342  {
343  if ( Abc_ObjIsLatch(pBox) )
344  continue;
345  Abc_ObjForEachFanin( pBox, pTerm, k )
346  {
347  pNet = Abc_ObjFanin0(pTerm);
348  Counter++;
349  // get the line length after this name is written
350  AddedLength = strlen(Io_WriteVerilogGetName(Abc_ObjName(pNet))) + 2;
351  if ( NameCounter && LineLength + AddedLength + 3 > IO_WRITE_LINE_LENGTH )
352  { // write the line extender
353  fprintf( pFile, "\n " );
354  // reset the line length
355  LineLength = 3;
356  NameCounter = 0;
357  }
358  fprintf( pFile, " %s%s", Io_WriteVerilogGetName(Abc_ObjName(pNet)), (Counter==nNodes)? "" : "," );
359  LineLength += AddedLength;
360  NameCounter++;
361  }
362  Abc_ObjForEachFanout( pBox, pTerm, k )
363  {
364  pNet = Abc_ObjFanout0(pTerm);
365  if ( Abc_ObjFanoutNum(pNet) > 0 && Abc_ObjIsCo(Abc_ObjFanout0(pNet)) )
366  continue;
367  Counter++;
368  // get the line length after this name is written
369  AddedLength = strlen(Io_WriteVerilogGetName(Abc_ObjName(pNet))) + 2;
370  if ( NameCounter && LineLength + AddedLength + 3 > IO_WRITE_LINE_LENGTH )
371  { // write the line extender
372  fprintf( pFile, "\n " );
373  // reset the line length
374  LineLength = 3;
375  NameCounter = 0;
376  }
377  fprintf( pFile, " %s%s", Io_WriteVerilogGetName(Abc_ObjName(pNet)), (Counter==nNodes)? "" : "," );
378  LineLength += AddedLength;
379  NameCounter++;
380  }
381  }
382  assert( Counter == nNodes );
383 }
384 
385 /**Function*************************************************************
386 
387  Synopsis [Writes the regs.]
388 
389  Description []
390 
391  SideEffects []
392 
393  SeeAlso []
394 
395 ***********************************************************************/
396 void Io_WriteVerilogRegs( FILE * pFile, Abc_Ntk_t * pNtk, int Start )
397 {
398  Abc_Obj_t * pLatch, * pNet;
399  int LineLength;
400  int AddedLength;
401  int NameCounter;
402  int i, Counter, nNodes;
403 
404  // count the number of latches
405  nNodes = Abc_NtkLatchNum(pNtk);
406 
407  // write the wires
408  Counter = 0;
409  LineLength = Start;
410  NameCounter = 0;
411  Abc_NtkForEachLatch( pNtk, pLatch, i )
412  {
413  pNet = Abc_ObjFanout0(Abc_ObjFanout0(pLatch));
414  Counter++;
415  // get the line length after this name is written
416  AddedLength = strlen(Io_WriteVerilogGetName(Abc_ObjName(pNet))) + 2;
417  if ( NameCounter && LineLength + AddedLength + 3 > IO_WRITE_LINE_LENGTH )
418  { // write the line extender
419  fprintf( pFile, "\n " );
420  // reset the line length
421  LineLength = 3;
422  NameCounter = 0;
423  }
424  fprintf( pFile, " %s%s", Io_WriteVerilogGetName(Abc_ObjName(pNet)), (Counter==nNodes)? "" : "," );
425  LineLength += AddedLength;
426  NameCounter++;
427  }
428 }
429 
430 /**Function*************************************************************
431 
432  Synopsis [Writes the latches.]
433 
434  Description []
435 
436  SideEffects []
437 
438  SeeAlso []
439 
440 ***********************************************************************/
441 void Io_WriteVerilogLatches( FILE * pFile, Abc_Ntk_t * pNtk )
442 {
443  Abc_Obj_t * pLatch;
444  int i;
445  if ( Abc_NtkLatchNum(pNtk) == 0 )
446  return;
447  // write the latches
448 // fprintf( pFile, " always @(posedge %s) begin\n", Io_WriteVerilogGetName(Abc_ObjFanout0(Abc_NtkPi(pNtk,0))) );
449 // fprintf( pFile, " always begin\n" );
450  fprintf( pFile, " always @ (posedge clock) begin\n" );
451  Abc_NtkForEachLatch( pNtk, pLatch, i )
452  {
453  fprintf( pFile, " %s", Io_WriteVerilogGetName(Abc_ObjName(Abc_ObjFanout0(Abc_ObjFanout0(pLatch)))) );
454  fprintf( pFile, " <= %s;\n", Io_WriteVerilogGetName(Abc_ObjName(Abc_ObjFanin0(Abc_ObjFanin0(pLatch)))) );
455  }
456  fprintf( pFile, " end\n" );
457  // check if there are initial values
458  Abc_NtkForEachLatch( pNtk, pLatch, i )
459  if ( Abc_LatchInit(pLatch) == ABC_INIT_ZERO || Abc_LatchInit(pLatch) == ABC_INIT_ONE )
460  break;
461  if ( i == Abc_NtkLatchNum(pNtk) )
462  return;
463  // write the initial values
464  fprintf( pFile, " initial begin\n" );
465  Abc_NtkForEachLatch( pNtk, pLatch, i )
466  {
467  if ( Abc_LatchInit(pLatch) == ABC_INIT_ZERO )
468  fprintf( pFile, " %s <= 1\'b0;\n", Io_WriteVerilogGetName(Abc_ObjName(Abc_ObjFanout0(Abc_ObjFanout0(pLatch)))) );
469  else if ( Abc_LatchInit(pLatch) == ABC_INIT_ONE )
470  fprintf( pFile, " %s <= 1\'b1;\n", Io_WriteVerilogGetName(Abc_ObjName(Abc_ObjFanout0(Abc_ObjFanout0(pLatch)))) );
471  }
472  fprintf( pFile, " end\n" );
473 }
474 
475 /**Function*************************************************************
476 
477  Synopsis [Writes the nodes and boxes.]
478 
479  Description []
480 
481  SideEffects []
482 
483  SeeAlso []
484 
485 ***********************************************************************/
486 void Io_WriteVerilogObjects( FILE * pFile, Abc_Ntk_t * pNtk )
487 {
488  Vec_Vec_t * vLevels;
489  Abc_Ntk_t * pNtkBox;
490  Abc_Obj_t * pObj, * pTerm, * pFanin;
491  Hop_Obj_t * pFunc;
492  int i, k, Counter, nDigits, Length;
493 
494  // write boxes
495  nDigits = Abc_Base10Log( Abc_NtkBoxNum(pNtk)-Abc_NtkLatchNum(pNtk) );
496  Counter = 0;
497  Abc_NtkForEachBox( pNtk, pObj, i )
498  {
499  if ( Abc_ObjIsLatch(pObj) )
500  continue;
501  pNtkBox = (Abc_Ntk_t *)pObj->pData;
502  fprintf( pFile, " %s box%0*d", pNtkBox->pName, nDigits, Counter++ );
503  fprintf( pFile, "(" );
504  Abc_NtkForEachPi( pNtkBox, pTerm, k )
505  {
506  fprintf( pFile, ".%s", Io_WriteVerilogGetName(Abc_ObjName(Abc_ObjFanout0(pTerm))) );
507  fprintf( pFile, "(%s), ", Io_WriteVerilogGetName(Abc_ObjName(Abc_ObjFanin0(Abc_ObjFanin(pObj,k)))) );
508  }
509  Abc_NtkForEachPo( pNtkBox, pTerm, k )
510  {
511  fprintf( pFile, ".%s", Io_WriteVerilogGetName(Abc_ObjName(Abc_ObjFanin0(pTerm))) );
512  fprintf( pFile, "(%s)%s", Io_WriteVerilogGetName(Abc_ObjName(Abc_ObjFanout0(Abc_ObjFanout(pObj,k)))), k==Abc_NtkPoNum(pNtkBox)-1? "":", " );
513  }
514  fprintf( pFile, ");\n" );
515  }
516  // write nodes
517  if ( Abc_NtkHasMapping(pNtk) )
518  {
519  Length = Mio_LibraryReadGateNameMax((Mio_Library_t *)pNtk->pManFunc);
520  nDigits = Abc_Base10Log( Abc_NtkNodeNum(pNtk) );
521  Counter = 0;
522  Abc_NtkForEachNode( pNtk, pObj, k )
523  {
524  Mio_Gate_t * pGate = (Mio_Gate_t *)pObj->pData;
525  Mio_Pin_t * pGatePin;
526  if ( Abc_ObjFaninNum(pObj) == 0 && (!strcmp(Mio_GateReadName(pGate), "_const0_") || !strcmp(Mio_GateReadName(pGate), "_const1_")) )
527  {
528  fprintf( pFile, " %-*s %s = 1\'b%d;\n", Length, "assign", Io_WriteVerilogGetName(Abc_ObjName( Abc_ObjFanout0(pObj) )), !strcmp(Mio_GateReadName(pGate), "_const1_") );
529  continue;
530  }
531  // write the node
532  fprintf( pFile, " %-*s g%0*d", Length, Mio_GateReadName(pGate), nDigits, Counter++ );
533  fprintf( pFile, "(" );
534  for ( pGatePin = Mio_GateReadPins(pGate), i = 0; pGatePin; pGatePin = Mio_PinReadNext(pGatePin), i++ )
535  {
536  fprintf( pFile, ".%s", Io_WriteVerilogGetName(Mio_PinReadName(pGatePin)) );
537  fprintf( pFile, "(%s), ", Io_WriteVerilogGetName(Abc_ObjName( Abc_ObjFanin(pObj,i) )) );
538  }
539  assert ( i == Abc_ObjFaninNum(pObj) );
540  fprintf( pFile, ".%s", Io_WriteVerilogGetName(Mio_GateReadOutName(pGate)) );
541  fprintf( pFile, "(%s)", Io_WriteVerilogGetName(Abc_ObjName( Abc_ObjFanout0(pObj) )) );
542  fprintf( pFile, ");\n" );
543  }
544  }
545  else
546  {
547  vLevels = Vec_VecAlloc( 10 );
548  Abc_NtkForEachNode( pNtk, pObj, i )
549  {
550  pFunc = (Hop_Obj_t *)pObj->pData;
551  fprintf( pFile, " assign %s = ", Io_WriteVerilogGetName(Abc_ObjName(Abc_ObjFanout0(pObj))) );
552  // set the input names
553  Abc_ObjForEachFanin( pObj, pFanin, k )
554  Hop_IthVar((Hop_Man_t *)pNtk->pManFunc, k)->pData = Extra_UtilStrsav(Io_WriteVerilogGetName(Abc_ObjName(pFanin)));
555  // write the formula
556  Hop_ObjPrintVerilog( pFile, pFunc, vLevels, 0 );
557  fprintf( pFile, ";\n" );
558  // clear the input names
559  Abc_ObjForEachFanin( pObj, pFanin, k )
560  ABC_FREE( Hop_IthVar((Hop_Man_t *)pNtk->pManFunc, k)->pData );
561  }
562  Vec_VecFree( vLevels );
563  }
564 }
565 
566 /**Function*************************************************************
567 
568  Synopsis [Counts the number of wires.]
569 
570  Description []
571 
572  SideEffects []
573 
574  SeeAlso []
575 
576 ***********************************************************************/
577 int Io_WriteVerilogWiresCount( Abc_Ntk_t * pNtk )
578 {
579  Abc_Obj_t * pObj, * pNet, * pBox;
580  int i, k, nWires;
581  nWires = Abc_NtkLatchNum(pNtk);
582  Abc_NtkForEachNode( pNtk, pObj, i )
583  {
584  if ( i == 0 )
585  continue;
586  pNet = Abc_ObjFanout0(pObj);
587  if ( Abc_ObjFanoutNum(pNet) > 0 && Abc_ObjIsCo(Abc_ObjFanout0(pNet)) )
588  continue;
589  nWires++;
590  }
591  Abc_NtkForEachBox( pNtk, pBox, i )
592  {
593  if ( Abc_ObjIsLatch(pBox) )
594  continue;
595  nWires += Abc_ObjFaninNum(pBox);
596  Abc_ObjForEachFanout( pBox, pObj, k )
597  {
598  pNet = Abc_ObjFanout0(pObj);
599  if ( Abc_ObjFanoutNum(pNet) > 0 && Abc_ObjIsCo(Abc_ObjFanout0(pNet)) )
600  continue;
601  nWires++;
602  }
603  }
604  return nWires;
605 }
606 
607 /**Function*************************************************************
608 
609  Synopsis [Prepares the name for writing the Verilog file.]
610 
611  Description []
612 
613  SideEffects []
614 
615  SeeAlso []
616 
617 ***********************************************************************/
618 char * Io_WriteVerilogGetName( char * pName )
619 {
620  static char Buffer[500];
621  int Length, i;
622  Length = strlen(pName);
623  // consider the case of a signal having name "0" or "1"
624  if ( !(Length == 1 && (pName[0] == '0' || pName[0] == '1')) )
625  {
626  for ( i = 0; i < Length; i++ )
627  if ( !((pName[i] >= 'a' && pName[i] <= 'z') ||
628  (pName[i] >= 'A' && pName[i] <= 'Z') ||
629  (pName[i] >= '0' && pName[i] <= '9') || pName[i] == '_') )
630  break;
631  if ( i == Length )
632  return pName;
633  }
634  // create Verilog style name
635  Buffer[0] = '\\';
636  for ( i = 0; i < Length; i++ )
637  Buffer[i+1] = pName[i];
638  Buffer[Length+1] = ' ';
639  Buffer[Length+2] = 0;
640  return Buffer;
641 }
642 
643 ////////////////////////////////////////////////////////////////////////
644 /// END OF FILE ///
645 ////////////////////////////////////////////////////////////////////////
646 
647 
648 ABC_NAMESPACE_IMPL_END
649 
Nm_ManFindIdByName
int Nm_ManFindIdByName(Nm_Man_t *p, char *pName, int Type)
Definition: nmApi.c:219
Abc_LatchInit
static int Abc_LatchInit(Abc_Obj_t *pLatch)
Definition: abc.h:425
Io_WriteVerilogPis
static void Io_WriteVerilogPis(FILE *pFile, Abc_Ntk_t *pNtk, int Start)
Definition: ioWriteVerilog.c:186
Io_WriteVerilogWiresCount
static int Io_WriteVerilogWiresCount(Abc_Ntk_t *pNtk)
Definition: ioWriteVerilog.c:577
Vec_VecAlloc
static Vec_Vec_t * Vec_VecAlloc(int nCap)
FUNCTION DEFINITIONS ///.
Definition: vecVec.h:145
Abc_Ntk_t_::pManName
Nm_Man_t * pManName
Definition: abc.h:160
Vec_Vec_t
typedefABC_NAMESPACE_HEADER_START struct Vec_Vec_t_ Vec_Vec_t
INCLUDES ///.
Definition: vecVec.h:42
Abc_NtkIsNetlist
static int Abc_NtkIsNetlist(Abc_Ntk_t *pNtk)
Definition: abc.h:249
Mio_GateReadPins
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Definition: mioApi.c:147
Abc_ObjIsLatch
static int Abc_ObjIsLatch(Abc_Obj_t *pObj)
Definition: abc.h:356
Abc_Ntk_t_
Definition: abc.h:153
Abc_ObjFanoutNum
static int Abc_ObjFanoutNum(Abc_Obj_t *pObj)
Definition: abc.h:365
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static int Abc_NtkBoxNum(Abc_Ntk_t *pNtk)
Definition: abc.h:289
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static void Io_WriteVerilogPos(FILE *pFile, Abc_Ntk_t *pNtk, int Start)
Definition: ioWriteVerilog.c:225
Abc_ObjFaninNum
static int Abc_ObjFaninNum(Abc_Obj_t *pObj)
Definition: abc.h:364
Abc_NtkHasMapping
static int Abc_NtkHasMapping(Abc_Ntk_t *pNtk)
Definition: abc.h:256
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Definition: mioApi.c:144
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static int Abc_NtkLatchNum(Abc_Ntk_t *pNtk)
Definition: abc.h:294
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char * Mio_PinReadName(Mio_Pin_t *pPin)
Definition: mioApi.c:170
Abc_ObjIsPi
static int Abc_ObjIsPi(Abc_Obj_t *pObj)
Definition: abc.h:347
Io_WriteVerilogLatches
static void Io_WriteVerilogLatches(FILE *pFile, Abc_Ntk_t *pNtk)
Definition: ioWriteVerilog.c:441
Io_WriteVerilogObjects
static void Io_WriteVerilogObjects(FILE *pFile, Abc_Ntk_t *pNtk)
Definition: ioWriteVerilog.c:486
Mio_PinStruct_t_
Definition: mioInt.h:103
Mio_PinReadNext
Mio_Pin_t * Mio_PinReadNext(Mio_Pin_t *pPin)
Definition: mioApi.c:179
Vec_VecFree
static void Vec_VecFree(Vec_Vec_t *p)
Definition: vecVec.h:347
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static void Io_WriteVerilogWires(FILE *pFile, Abc_Ntk_t *pNtk, int Start)
Definition: ioWriteVerilog.c:288
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static Abc_Obj_t * Abc_ObjFanin0(Abc_Obj_t *pObj)
Definition: abc.h:373
Hop_Obj_t_
Definition: hop.h:65
Abc_ObjIsCo
static int Abc_ObjIsCo(Abc_Obj_t *pObj)
Definition: abc.h:352
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void Io_WriteVerilog(Abc_Ntk_t *pNtk, char *pFileName)
FUNCTION DEFINITIONS ///.
Definition: ioWriteVerilog.c:57
Extra_UtilStrsav
char * Extra_UtilStrsav(const char *s)
Definition: extraUtilUtil.c:169
strcmp
int strcmp()
Abc_Obj_t_
Definition: abc.h:128
Abc_Ntk_t_::pManFunc
void * pManFunc
Definition: abc.h:191
Abc_NtkNodeNum
static int Abc_NtkNodeNum(Abc_Ntk_t *pNtk)
Definition: abc.h:293
Abc_NtkHasBlackbox
static int Abc_NtkHasBlackbox(Abc_Ntk_t *pNtk)
Definition: abc.h:258
IO_WRITE_LINE_LENGTH
#define IO_WRITE_LINE_LENGTH
MACRO DEFINITIONS ///.
Definition: ioAbc.h:71
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static ABC_NAMESPACE_IMPL_START void Io_WriteVerilogInt(FILE *pFile, Abc_Ntk_t *pNtk)
DECLARATIONS ///.
Definition: ioWriteVerilog.c:115
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static int Abc_NtkIsAigNetlist(Abc_Ntk_t *pNtk)
Definition: abc.h:261
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static int Abc_Base10Log(unsigned n)
Definition: abc_global.h:252
ABC_NAMESPACE_IMPL_END
#define ABC_NAMESPACE_IMPL_END
Definition: abc_global.h:108
if
if(last==0)
Definition: sparse_int.h:34
Mio_LibraryStruct_t_
STRUCTURE DEFINITIONS ///.
Definition: mioInt.h:61
Counter
static int Counter
Definition: extraBddMisc.c:1877
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#define Abc_NtkForEachLatch(pNtk, pObj, i)
Definition: abc.h:497
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Definition: mioInt.h:79
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void * pData
Definition: hop.h:68
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static void Io_WriteVerilogRegs(FILE *pFile, Abc_Ntk_t *pNtk, int Start)
Definition: ioWriteVerilog.c:396
Abc_NtkForEachBox
#define Abc_NtkForEachBox(pNtk, pObj, i)
Definition: abc.h:495
Abc_NtkForEachNode
#define Abc_NtkForEachNode(pNtk, pNode, i)
Definition: abc.h:461
ABC_NAMESPACE_IMPL_START
#define ABC_NAMESPACE_IMPL_START
Definition: abc_global.h:107
Abc_NtkIsMappedNetlist
static int Abc_NtkIsMappedNetlist(Abc_Ntk_t *pNtk)
Definition: abc.h:262
ABC_OBJ_PI
Definition: abc.h:89
Abc_ObjForEachFanout
#define Abc_ObjForEachFanout(pObj, pFanout, i)
Definition: abc.h:526
Abc_NtkName
static char * Abc_NtkName(Abc_Ntk_t *pNtk)
Definition: abc.h:270
Abc_NtkPoNum
static int Abc_NtkPoNum(Abc_Ntk_t *pNtk)
Definition: abc.h:286
Abc_ObjForEachFanin
#define Abc_ObjForEachFanin(pObj, pFanin, i)
Definition: abc.h:524
ABC_FREE
#define ABC_FREE(obj)
Definition: abc_global.h:232
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static int Abc_NtkPiNum(Abc_Ntk_t *pNtk)
Definition: abc.h:285
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ABC_DLL char * Abc_ObjName(Abc_Obj_t *pNode)
DECLARATIONS ///.
Definition: abcNames.c:48
Extra_TimeStamp
char * Extra_TimeStamp()
Definition: extraUtilFile.c:446
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static char * Io_WriteVerilogGetName(char *pName)
Definition: ioWriteVerilog.c:618
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Vec_Ptr_t * vModules
Definition: abc.h:223
assert
#define assert(ex)
Definition: util_old.h:213
strlen
int strlen()
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int Mio_LibraryReadGateNameMax(Mio_Library_t *pLib)
Definition: mioApi.c:75
Abc_Obj_t_::pData
void * pData
Definition: abc.h:145
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#define Abc_NtkForEachPo(pNtk, pPo, i)
Definition: abc.h:517
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static Abc_Obj_t * Abc_ObjFanout(Abc_Obj_t *pObj, int i)
Definition: abc.h:370
Abc_ObjFanin
static Abc_Obj_t * Abc_ObjFanin(Abc_Obj_t *pObj, int i)
Definition: abc.h:372
Vec_PtrForEachEntry
#define Vec_PtrForEachEntry(Type, vVec, pEntry, i)
MACRO DEFINITIONS ///.
Definition: vecPtr.h:55
Abc_Ntk_t_::pDesign
Abc_Des_t * pDesign
Definition: abc.h:180
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Definition: mioApi.c:143
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typedefABC_NAMESPACE_HEADER_START struct Hop_Man_t_ Hop_Man_t
INCLUDES ///.
Definition: hop.h:49
Abc_Ntk_t_::pName
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Definition: abc.h:158
Hop_IthVar
Hop_Obj_t * Hop_IthVar(Hop_Man_t *p, int i)
FUNCTION DEFINITIONS ///.
Definition: hopOper.c:63
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static Abc_Obj_t * Abc_ObjFanout0(Abc_Obj_t *pObj)
Definition: abc.h:371
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#define Abc_NtkForEachPi(pNtk, pPi, i)
Definition: abc.h:513
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Definition: hopUtil.c:369