cgtInt.h File Reference

#include "aig/saig/saig.h"
#include "sat/bsat/satSolver.h"
#include "sat/cnf/cnf.h"
#include "cgt.h"

Go to the source code of this file.

Data Structures
struct	Cgt_Man_t_

Typedefs
typedef typedefABC_NAMESPACE_HEADER_START struct Cgt_Man_t_	Cgt_Man_t
	INCLUDES ///. More...

Functions
void	Cgt_ManDetectCandidates (Aig_Man_t *pAig, Vec_Int_t *vUseful, Aig_Obj_t *pObj, int nLevelMax, Vec_Ptr_t *vCands)
	MACRO DEFINITIONS ///. More...
Aig_Man_t *	Cgt_ManDeriveAigForGating (Cgt_Man_t *p)
Aig_Man_t *	Cgt_ManDupPartition (Aig_Man_t *pAig, int nVarsMin, int nFlopsMin, int iStart, Aig_Man_t *pCare, Vec_Vec_t *vSuppsInv, int *pnOutputs)
Aig_Man_t *	Cgt_ManDeriveGatedAig (Aig_Man_t *pAig, Vec_Vec_t *vGates, int fReduce, int *pnUsedNodes)
Vec_Vec_t *	Cgt_ManDecideSimple (Aig_Man_t *pAig, Vec_Vec_t *vGatesAll, int nOdcMax, int fVerbose)
Vec_Vec_t *	Cgt_ManDecideArea (Aig_Man_t *pAig, Vec_Vec_t *vGatesAll, int nOdcMax, int fVerbose)
Cgt_Man_t *	Cgt_ManCreate (Aig_Man_t *pAig, Aig_Man_t *pCare, Cgt_Par_t *pPars)
	DECLARATIONS ///. More...
void	Cgt_ManClean (Cgt_Man_t *p)
void	Cgt_ManStop (Cgt_Man_t *p)
int	Cgt_CheckImplication (Cgt_Man_t *p, Aig_Obj_t *pGate, Aig_Obj_t *pFlop)
	DECLARATIONS ///. More...

Typedef Documentation

typedef typedefABC_NAMESPACE_HEADER_START struct Cgt_Man_t_ Cgt_Man_t

INCLUDES ///.

CFile****************************************************************

FileName [cgtInt.h]

SystemName [ABC: Logic synthesis and verification system.]

PackageName [Clock gating package.]

Synopsis [Internal declarations.]

Author [Alan Mishchenko]

Affiliation [UC Berkeley]

Date [Ver. 1.0. Started - June 20, 2005.]

Revision [

Id:

cgtInt.h,v 1.00 2005/06/20 00:00:00 alanmi Exp

]PARAMETERS ///BASIC TYPES ///

Definition at line 47 of file cgtInt.h.

Function Documentation

int Cgt_CheckImplication	(	Cgt_Man_t *	p,
		Aig_Obj_t *	pGate,
		Aig_Obj_t *	pMiter
	)

DECLARATIONS ///.

CFile****************************************************************

FileName [cgtSat.c]

SystemName [ABC: Logic synthesis and verification system.]

PackageName [Clock gating package.]

Synopsis [Checking implications using SAT.]

Author [Alan Mishchenko]

Affiliation [UC Berkeley]

Date [Ver. 1.0. Started - June 20, 2005.]

Revision [

Id:

cgtSat.c,v 1.00 2005/06/20 00:00:00 alanmi Exp

]FUNCTION DEFINITIONS /// Function*************************************************************

Synopsis [Runs equivalence test for the two nodes.]

Description [Both nodes should be regular and different from each other.]

SideEffects []

SeeAlso []

Definition at line 46 of file cgtSat.c.

{
    int nBTLimit = p->pPars->nConfMax;
    int pLits[2], RetValue;
    abctime clk;
    p->nCalls++;

    // sanity checks
    assert( p->pSat && p->pCnf );
    assert( !Aig_IsComplement(pMiter) );
    assert( Aig_Regular(pGate) != pMiter );

    // solve under assumptions
    // G => !M -- true     G & M -- false
    pLits[0] = toLitCond( p->pCnf->pVarNums[Aig_Regular(pGate)->Id], Aig_IsComplement(pGate) );
    pLits[1] = toLitCond( p->pCnf->pVarNums[pMiter->Id], 0 );

clk = Abc_Clock();
    RetValue = sat_solver_solve( p->pSat, pLits, pLits + 2, (ABC_INT64_T)nBTLimit, (ABC_INT64_T)0, (ABC_INT64_T)0, (ABC_INT64_T)0 );
p->timeSat += Abc_Clock() - clk;
    if ( RetValue == l_False )
    {
p->timeSatUnsat += Abc_Clock() - clk;
        pLits[0] = lit_neg( pLits[0] );
        pLits[1] = lit_neg( pLits[1] );
        RetValue = sat_solver_addclause( p->pSat, pLits, pLits + 2 );
        assert( RetValue );
        sat_solver_compress( p->pSat );
        p->nCallsUnsat++;
        return 1;
    }
    else if ( RetValue == l_True )
    {
p->timeSatSat += Abc_Clock() - clk;
        p->nCallsSat++;
        return 0;
    }
    else // if ( RetValue1 == l_Undef )
    {
p->timeSatUndec += Abc_Clock() - clk;
        p->nCallsUndec++;
        return -1;
    }
    return -2;
}

void Cgt_ManClean

(

Cgt_Man_t *

p

)

Function*************************************************************

Synopsis [Creates the manager.]

Description []

SideEffects []

SeeAlso []

Definition at line 86 of file cgtMan.c.

{
    if ( p->pPart )
    {
        Aig_ManStop( p->pPart );
        p->pPart = NULL;
    }
    if ( p->pCnf )
    {
        Cnf_DataFree( p->pCnf );
        p->pCnf = NULL;
    }
    if ( p->pSat )
    {
        sat_solver_delete( p->pSat );
        p->pSat = NULL;
    }
    if ( p->vPatts )
    {
        Vec_PtrFree( p->vPatts );
        p->vPatts = NULL;
    }
}

Cgt_Man_t* Cgt_ManCreate	(	Aig_Man_t *	pAig,
		Aig_Man_t *	pCare,
		Cgt_Par_t *	pPars
	)

DECLARATIONS ///.

CFile****************************************************************

FileName [cgtMan.c]

SystemName [ABC: Logic synthesis and verification system.]

PackageName [Clock gating package.]

Synopsis [Manipulation of clock gating manager.]

Author [Alan Mishchenko]

Affiliation [UC Berkeley]

Date [Ver. 1.0. Started - June 20, 2005.]

Revision [

Id:

cgtMan.c,v 1.00 2005/06/20 00:00:00 alanmi Exp

]FUNCTION DEFINITIONS /// Function*************************************************************

Synopsis [Creates the manager.]

Description []

SideEffects []

SeeAlso []

Definition at line 45 of file cgtMan.c.

{
    Cgt_Man_t * p;
    // prepare the sequential AIG
    assert( Saig_ManRegNum(pAig) > 0 );
    Aig_ManFanoutStart( pAig );
    Aig_ManSetCioIds( pAig );
    // create interpolation manager
    p = ABC_ALLOC( Cgt_Man_t, 1 ); 
    memset( p, 0, sizeof(Cgt_Man_t) );
    p->pPars      = pPars;
    p->pAig       = pAig;
    p->vGatesAll  = Vec_VecStart( Saig_ManRegNum(pAig) );
    p->vFanout    = Vec_PtrAlloc( 1000 );
    p->vVisited   = Vec_PtrAlloc( 1000 );
    p->nPattWords = 16;
    if ( pCare == NULL )
        return p;
    // check out the constraints
    if ( Aig_ManCiNum(pCare) != Aig_ManCiNum(pAig) )
    {
        printf( "The PI count of care (%d) and AIG (%d) differ. Careset is not used.\n", 
            Aig_ManCiNum(pCare), Aig_ManCiNum(pAig) );
        return p;
    }
    p->pCare = pCare;
    p->vSuppsInv = (Vec_Vec_t *)Aig_ManSupportsInverse( p->pCare );
    return p;
}

Vec_Vec_t* Cgt_ManDecideArea	(	Aig_Man_t *	pAig,
		Vec_Vec_t *	vGatesAll,
		int	nOdcMax,
		int	fVerbose
	)

Function*************************************************************

Synopsis [Computes the set of complete clock gates.]

Description []

SideEffects []

SeeAlso []

Definition at line 255 of file cgtDecide.c.

{
    Vec_Vec_t * vGates;
    Vec_Ptr_t * vCompletes, * vOne;
    Aig_Obj_t * pGate;
    int i, k, Counter = 0;
    abctime clk = Abc_Clock();
    // derive and label complete gates
    vCompletes = Cgt_ManCompleteGates( pAig, vGatesAll, nOdcMax, fVerbose );
    // label complete gates
    Vec_PtrForEachEntry( Aig_Obj_t *, vCompletes, pGate, i )
        Aig_Regular(pGate)->fMarkA = 1;
    // select only complete gates
    vGates = Vec_VecStart( Saig_ManRegNum(pAig) );
    Vec_VecForEachEntry( Aig_Obj_t *, vGatesAll, pGate, i, k )
        if ( Aig_Regular(pGate)->fMarkA )
            Vec_VecPush( vGates, i, pGate );
    // unlabel complete gates
    Vec_PtrForEachEntry( Aig_Obj_t *, vCompletes, pGate, i )
        Aig_Regular(pGate)->fMarkA = 0;
    // count the number of gated flops
    Vec_VecForEachLevel( vGates, vOne, i )
    {
        Counter += (int)(Vec_PtrSize(vOne) > 0);
//        printf( "%d ", Vec_PtrSize(vOne) );
    }
//    printf( "\n" );
    if ( fVerbose )
    {
        printf( "Gating signals = %6d. Gated flops = %6d. (Total flops = %6d.)\n", 
            Vec_VecSizeSize(vGatesAll), Counter, Saig_ManRegNum(pAig) );
        printf( "Complete gates = %6d. Gated transitions = %5.2f %%. ", 
            Vec_PtrSize(vCompletes), Cgt_ManComputeCoverage(pAig, vGates) );
        ABC_PRT( "Time", Abc_Clock() - clk );
    }
    Vec_PtrFree( vCompletes );
    return vGates;
}

Vec_Vec_t* Cgt_ManDecideSimple	(	Aig_Man_t *	pAig,
		Vec_Vec_t *	vGatesAll,
		int	nOdcMax,
		int	fVerbose
	)

Function*************************************************************

Synopsis [Chooses what clock-gate to use for this register.]

Description [Currently uses the naive approach: For each register, choose the clock gate, which covers most of the transitions.]

SideEffects []

SeeAlso []

Definition at line 184 of file cgtDecide.c.

{
    int nFrames = 32;
    int nWords  =  1;
    Ssw_Sml_t * pSml;
    Vec_Vec_t * vGates;
    Vec_Ptr_t * vCands;
    Aig_Obj_t * pObjLi, * pObjLo, * pCand, * pCandBest;
    int i, k, nHitsCur, nHitsMax, Counter = 0;
    abctime clk = Abc_Clock();
    int nTransTotal = 0, nTransSaved = 0;
    vGates = Vec_VecStart( Saig_ManRegNum(pAig) );
    pSml = Ssw_SmlSimulateSeq( pAig, 0, nFrames, nWords );
    Saig_ManForEachLiLo( pAig, pObjLi, pObjLo, i )
    {
        nHitsMax = 0;
        pCandBest = NULL;
        vCands = Vec_VecEntry( vGatesAll, i );
        Vec_PtrForEachEntry( Aig_Obj_t *, vCands, pCand, k )
        {
            // check if this is indeed a clock-gate
            if ( nOdcMax == 0 && !Ssw_SmlCheckXorImplication( pSml, pObjLi, pObjLo, pCand ) )
                printf( "Clock gate candidate is invalid!\n" );
            // find its characteristic number
            nHitsCur = Ssw_SmlNodeCountOnesReal( pSml, pCand );
            if ( nHitsMax < nHitsCur )
            {
                nHitsMax = nHitsCur;
                pCandBest = pCand;
            }
        }
        if ( pCandBest != NULL )
        {
            Vec_VecPush( vGates, i, pCandBest );
            Counter++;
            nTransSaved += nHitsMax;
        }
        nTransTotal += 32 * nFrames * nWords;
    }
    Ssw_SmlStop( pSml );
    if ( fVerbose )
    {
        printf( "Gating signals = %6d. Gated flops = %6d. (Total flops = %6d.)\n", 
            Vec_VecSizeSize(vGatesAll), Counter, Saig_ManRegNum(pAig) );
//        printf( "Gated transitions = %5.2f %%. (%5.2f %%.) ", 
//            100.0*nTransSaved/nTransTotal, Cgt_ManComputeCoverage(pAig, vGates) );
        printf( "Gated transitions = %5.2f %%. ", Cgt_ManComputeCoverage(pAig, vGates) );
        ABC_PRT( "Time", Abc_Clock() - clk );
    }
/*
    {
        Vec_Ptr_t * vCompletes;
        vCompletes = Cgt_ManCompleteGates( pAig, vGatesAll, nOdcMax, fVerbose );
        printf( "Complete gates = %d. \n", Vec_PtrSize(vCompletes) );
        Vec_PtrFree( vCompletes );
    }
*/
    return vGates;
}

Aig_Man_t* Cgt_ManDeriveAigForGating

(

Cgt_Man_t *

p

)

Function*************************************************************

Synopsis [Derives AIG for clock-gating.]

Description []

SideEffects []

SeeAlso []

Definition at line 266 of file cgtAig.c.

{
    Aig_Man_t * pNew;
    Aig_Obj_t * pObj, * pObjLi, * pObjLo, * pCare, * pMiter;
    Vec_Ptr_t * vCopy0, * vCopy1;
    int i;
    assert( Aig_ManRegNum(p->pAig) );
    pNew = Aig_ManStart( Aig_ManObjNumMax(p->pAig) );
    pNew->pName = Abc_UtilStrsav( "CG_miter" );
    // build the first frame
    Aig_ManConst1(p->pAig)->pData = Aig_ManConst1(pNew);
    Aig_ManForEachCi( p->pAig, pObj, i )
        pObj->pData = Aig_ObjCreateCi( pNew );
    Aig_ManForEachNode( p->pAig, pObj, i )
        pObj->pData = Aig_And( pNew, Aig_ObjChild0Copy(pObj), Aig_ObjChild1Copy(pObj) );
//    Saig_ManForEachPo( p->pAig, pObj, i )
//        pObj->pData = Aig_ObjCreateCo( pNew, Aig_ObjChild0Copy(pObj) );
    if ( p->pPars->nOdcMax > 0 )
    {
        // create storage for observability conditions
        vCopy0 = Vec_PtrStart( Aig_ManObjNumMax(p->pAig) );
        vCopy1 = Vec_PtrStart( Aig_ManObjNumMax(p->pAig) );
        // initialize register outputs
        Saig_ManForEachLiLo( p->pAig, pObjLi, pObjLo, i )
        {
            Vec_PtrWriteEntry( vCopy0, Aig_ObjId(pObjLo), Aig_ObjChild0Copy(pObjLi) );
            Vec_PtrWriteEntry( vCopy1, Aig_ObjId(pObjLo), Aig_ObjChild0Copy(pObjLi) );
        }
        // compute observability condition for each latch output
        Saig_ManForEachLiLo( p->pAig, pObjLi, pObjLo, i )
        {
            // set the constants
            Vec_PtrWriteEntry( vCopy0, Aig_ObjId(pObjLo), Aig_ManConst0(pNew) );
            Vec_PtrWriteEntry( vCopy1, Aig_ObjId(pObjLo), Aig_ManConst1(pNew) );
            // compute condition
            pCare = Cgt_ManConstructCareCondition( p, pNew, pObjLo, vCopy0, vCopy1 );
            // restore the values
            Vec_PtrWriteEntry( vCopy0, Aig_ObjId(pObjLo), Aig_ObjChild0Copy(pObjLi) );
            Vec_PtrWriteEntry( vCopy1, Aig_ObjId(pObjLo), Aig_ObjChild0Copy(pObjLi) );
            // compute the miter
            pMiter = Aig_Exor( pNew, (Aig_Obj_t *)pObjLo->pData, Aig_ObjChild0Copy(pObjLi) );
            pMiter = Aig_And( pNew, pMiter, pCare );
            pObjLi->pData = Aig_ObjCreateCo( pNew, pMiter );
        }
        Vec_PtrFree( vCopy0 );
        Vec_PtrFree( vCopy1 );
    }
    else
    {
        // construct clock-gating miters for each register input
        Saig_ManForEachLiLo( p->pAig, pObjLi, pObjLo, i )
        {
            pMiter = Aig_Exor( pNew, (Aig_Obj_t *)pObjLo->pData, Aig_ObjChild0Copy(pObjLi) );
            pObjLi->pData = Aig_ObjCreateCo( pNew, pMiter );
        }
    }
    Aig_ManCleanup( pNew );
    Aig_ManSetCioIds( pNew );
    return pNew;
}

Aig_Man_t* Cgt_ManDeriveGatedAig	(	Aig_Man_t *	pAig,
		Vec_Vec_t *	vGates,
		int	fReduce,
		int *	pnUsedNodes
	)

Function*************************************************************

Synopsis [Derives AIG after clock-gating.]

Description [The array contains, for each flop, its gate if present.]

SideEffects []

SeeAlso []

Definition at line 524 of file cgtAig.c.

{
    Aig_Man_t * pNew;
    Aig_Obj_t * pObj, * pObjNew, * pObjLi, * pObjLo, * pGateNew;
    Vec_Ptr_t * vOne;
    int i, k;
    Aig_ManCleanNext( pAig );
    // label nodes
    Vec_VecForEachEntry( Aig_Obj_t *, vGates, pObj, i, k )
    {
        if ( Aig_IsComplement(pObj) )
            Aig_Regular(pObj)->fMarkB = 1;
        else
            Aig_Regular(pObj)->fMarkA = 1;
    }
    // construct AIG
    assert( Aig_ManRegNum(pAig) );
    pNew = Aig_ManStart( Aig_ManObjNumMax(pAig) );
    pNew->pName = Abc_UtilStrsav( pAig->pName );
    pNew->pSpec = Abc_UtilStrsav( pAig->pSpec );
    Aig_ManConst1(pAig)->pData = Aig_ManConst1(pNew);
    Aig_ManForEachCi( pAig, pObj, i )
        pObj->pData = Aig_ObjCreateCi( pNew );
    if ( fReduce )
    {
        Aig_ManForEachNode( pAig, pObj, i )
        {
            assert( !(pObj->fMarkA && pObj->fMarkB) );
            pObj->pData = Aig_And( pNew, Aig_ObjChild0Copy(pObj), Aig_ObjChild1Copy(pObj) );
            if ( pObj->fMarkA )
            {
                pObj->pNext = (Aig_Obj_t *)pObj->pData;
                pObj->pData = Aig_ManConst0(pNew);
            }
            else if ( pObj->fMarkB )
            {
                pObj->pNext = (Aig_Obj_t *)pObj->pData;
                pObj->pData = Aig_ManConst1(pNew);
            }
        }
    }
    else
    {
        Aig_ManForEachNode( pAig, pObj, i )
            pObj->pData = Aig_And( pNew, Aig_ObjChild0Copy(pObj), Aig_ObjChild1Copy(pObj) );
    }
    if ( pnUsedNodes != NULL )
        *pnUsedNodes = Aig_ManNodeNum(pNew);
    Saig_ManForEachPo( pAig, pObj, i )
        pObj->pData = Aig_ObjCreateCo( pNew, Aig_ObjChild0Copy(pObj) );
    Saig_ManForEachLiLo( pAig, pObjLi, pObjLo, i )
    {
        vOne = Vec_VecEntry( vGates, i );
        if ( Vec_PtrSize(vOne) == 0 )
            pObjNew = Aig_ObjChild0Copy(pObjLi);
        else
        {
//            pGateNew = Aig_NotCond( Aig_Regular(pGate)->pData, Aig_IsComplement(pGate) );
            pGateNew = Cgt_ManBuildClockGate( pNew, vOne );
            pObjNew = Aig_Mux( pNew, pGateNew, (Aig_Obj_t *)pObjLo->pData, Aig_ObjChild0Copy(pObjLi) );
        }
        pObjLi->pData = Aig_ObjCreateCo( pNew, pObjNew );
    }
    Aig_ManCleanup( pNew );
    Aig_ManSetRegNum( pNew, Aig_ManRegNum(pAig) );
    // unlabel nodes
    Aig_ManCleanMarkAB( pAig );
    Aig_ManCleanNext( pAig );
    return pNew;
}

void Cgt_ManDetectCandidates	(	Aig_Man_t *	pAig,
		Vec_Int_t *	vUseful,
		Aig_Obj_t *	pObj,
		int	nLevelMax,
		Vec_Ptr_t *	vCands
	)

MACRO DEFINITIONS ///.

FUNCTION DECLARATIONS ///

Function*************************************************************

Synopsis [Computes transitive fanout cone of the node.]

Description []

SideEffects []

SeeAlso []

Definition at line 70 of file cgtAig.c.

{
    Vec_PtrClear( vCands );
    if ( !Aig_ObjIsNode(pObj) )
        return;
    Aig_ManIncrementTravId( pAig );
    Cgt_ManDetectCandidates_rec( pAig, vUseful, pObj, nLevelMax, vCands );
}

Aig_Man_t* Cgt_ManDupPartition	(	Aig_Man_t *	pFrame,
		int	nVarsMin,
		int	nFlopsMin,
		int	iStart,
		Aig_Man_t *	pCare,
		Vec_Vec_t *	vSuppsInv,
		int *	pnOutputs
	)

Function*************************************************************

Synopsis [Duplicates register outputs starting from the given one.]

Description []

SideEffects []

SeeAlso []

Definition at line 441 of file cgtAig.c.

{
    Vec_Ptr_t * vRoots, * vLeaves, * vPos;
    Aig_Man_t * pNew;
    Aig_Obj_t * pObj;
    int i;
    assert( Aig_ManRegNum(pFrame) == 0 );
    vRoots = Vec_PtrAlloc( 100 );
    vLeaves = Vec_PtrAlloc( 100 ); 
    vPos = Vec_PtrAlloc( 100 );
    pNew = Aig_ManStart( nVarsMin );
    pNew->pName = Abc_UtilStrsav( "partition" );
    Aig_ManIncrementTravId( pFrame );
    Aig_ManConst1(pFrame)->pData = Aig_ManConst1(pNew);
    Aig_ObjSetTravIdCurrent( pFrame, Aig_ManConst1(pFrame) );
    for ( i = iStart; i < iStart + nFlopsMin && i < Aig_ManCoNum(pFrame); i++ )
    {
        pObj = Aig_ManCo( pFrame, i );
        Cgt_ManDupPartition_rec( pNew, pFrame, Aig_ObjFanin0(pObj), vLeaves );
        Vec_PtrPush( vRoots, Aig_ObjChild0Copy(pObj) );
        Vec_PtrPush( vPos, pObj );
    }
    for ( ; Aig_ManObjNum(pNew) < nVarsMin && i < Aig_ManCoNum(pFrame); i++ )
    {
        pObj = Aig_ManCo( pFrame, i );
        Cgt_ManDupPartition_rec( pNew, pFrame, Aig_ObjFanin0(pObj), vLeaves );
        Vec_PtrPush( vRoots, Aig_ObjChild0Copy(pObj) );
        Vec_PtrPush( vPos, pObj );
    }
    assert( nFlopsMin >= Vec_PtrSize(vRoots) || Vec_PtrSize(vRoots) >= nFlopsMin );
    // create constaints
    if ( pCare )
        Cgt_ManConstructCare( pNew, pCare, vSuppsInv, vLeaves );
    // create POs
    Vec_PtrForEachEntry( Aig_Obj_t *, vPos, pObj, i )
        pObj->pData = (Aig_Obj_t *)Aig_ObjCreateCo( pNew, (Aig_Obj_t *)Vec_PtrEntry(vRoots, i) );
    if ( pnOutputs != NULL )
        *pnOutputs = Vec_PtrSize( vPos );
    Vec_PtrFree( vRoots );
    Vec_PtrFree( vLeaves );
    Vec_PtrFree( vPos );
    return pNew;
}

void Cgt_ManStop

(

Cgt_Man_t *

p

)

Function*************************************************************

Synopsis [Frees the manager.]

Description []

SideEffects []

SeeAlso []

Definition at line 154 of file cgtMan.c.

{
    if ( p->pPars->fVerbose )
        Cgt_ManPrintStats( p );
    if ( p->pFrame )
        Aig_ManStop( p->pFrame );
    Cgt_ManClean( p );
    Vec_PtrFree( p->vFanout );
    Vec_PtrFree( p->vVisited );
    if ( p->vGates )
        Vec_PtrFree( p->vGates );
    if ( p->vGatesAll )
        Vec_VecFree( p->vGatesAll );
    if ( p->vSuppsInv )
        Vec_VecFree( p->vSuppsInv );
    ABC_FREE( p );
}