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Public Member Functions | Data Fields
OptReduceWorker Struct Reference
+ Collaboration diagram for OptReduceWorker:

Public Member Functions

void opt_reduce (std::set< RTLIL::Cell * > &cells, SigSet< RTLIL::Cell * > &drivers, RTLIL::Cell *cell)
 
void opt_mux (RTLIL::Cell *cell)
 
void opt_mux_bits (RTLIL::Cell *cell)
 
 OptReduceWorker (RTLIL::Design *design, RTLIL::Module *module, bool do_fine)
 

Data Fields

RTLIL::Design * design
 
RTLIL::Module * module
 
SigMap assign_map
 
int total_count
 
bool did_something
 

Detailed Description

Definition at line 31 of file opt_reduce.cc.

Constructor & Destructor Documentation

OptReduceWorker::OptReduceWorker ( RTLIL::Design *  design,
RTLIL::Module *  module,
bool  do_fine 
)
inline

Definition at line 245 of file opt_reduce.cc.

245  :
246  design(design), module(module), assign_map(module)
247  {
248  log(" Optimizing cells in module %s.\n", module->name.c_str());
249 
250  total_count = 0;
251  did_something = true;
252 
253  SigPool mem_wren_sigs;
254  for (auto &cell_it : module->cells_) {
255  RTLIL::Cell *cell = cell_it.second;
256  if (cell->type == "$mem")
257  mem_wren_sigs.add(assign_map(cell->getPort("\\WR_EN")));
258  if (cell->type == "$memwr")
259  mem_wren_sigs.add(assign_map(cell->getPort("\\EN")));
260  }
261  for (auto &cell_it : module->cells_) {
262  RTLIL::Cell *cell = cell_it.second;
263  if (cell->type == "$dff" && mem_wren_sigs.check_any(assign_map(cell->getPort("\\Q"))))
264  mem_wren_sigs.add(assign_map(cell->getPort("\\D")));
265  }
266 
267  bool keep_expanding_mem_wren_sigs = true;
268  while (keep_expanding_mem_wren_sigs) {
269  keep_expanding_mem_wren_sigs = false;
270  for (auto &cell_it : module->cells_) {
271  RTLIL::Cell *cell = cell_it.second;
272  if (cell->type == "$mux" && mem_wren_sigs.check_any(assign_map(cell->getPort("\\Y")))) {
273  if (!mem_wren_sigs.check_all(assign_map(cell->getPort("\\A"))) ||
274  !mem_wren_sigs.check_all(assign_map(cell->getPort("\\B"))))
275  keep_expanding_mem_wren_sigs = true;
276  mem_wren_sigs.add(assign_map(cell->getPort("\\A")));
277  mem_wren_sigs.add(assign_map(cell->getPort("\\B")));
278  }
279  }
280  }
281 
282  while (did_something)
283  {
284  did_something = false;
285 
286  // merge trees of reduce_* cells to one single cell and unify input vectors
287  // (only handle recduce_and and reduce_or for various reasons)
288 
289  const char *type_list[] = { "$reduce_or", "$reduce_and" };
290  for (auto type : type_list)
291  {
292  SigSet<RTLIL::Cell*> drivers;
293  std::set<RTLIL::Cell*> cells;
294 
295  for (auto &cell_it : module->cells_) {
296  RTLIL::Cell *cell = cell_it.second;
297  if (cell->type != type || !design->selected(module, cell))
298  continue;
299  drivers.insert(assign_map(cell->getPort("\\Y")), cell);
300  cells.insert(cell);
301  }
302 
303  while (cells.size() > 0) {
304  RTLIL::Cell *cell = *cells.begin();
305  opt_reduce(cells, drivers, cell);
306  }
307  }
308 
309  // merge identical inputs on $mux and $pmux cells
310 
311  std::vector<RTLIL::Cell*> cells;
312 
313  for (auto &it : module->cells_)
314  if ((it.second->type == "$mux" || it.second->type == "$pmux") && design->selected(module, it.second))
315  cells.push_back(it.second);
316 
317  for (auto cell : cells)
318  {
319  // this optimization is to aggressive for most coarse-grain applications.
320  // but we always want it for multiplexers driving write enable ports.
321  if (do_fine || mem_wren_sigs.check_any(assign_map(cell->getPort("\\Y"))))
322  opt_mux_bits(cell);
323 
324  opt_mux(cell);
325  }
326  }
327  }
RTLIL::IdString::c_str
const char * c_str() const
Definition: rtlil.h:178
RTLIL::Design::selected
bool selected(T1 *module) const
Definition: rtlil.h:551
OptReduceWorker::design
RTLIL::Design * design
Definition: opt_reduce.cc:33
OptReduceWorker::module
RTLIL::Module * module
Definition: opt_reduce.cc:34
OptReduceWorker::opt_mux
void opt_mux(RTLIL::Cell *cell)
Definition: opt_reduce.cc:101
OptReduceWorker::assign_map
SigMap assign_map
Definition: opt_reduce.cc:35
RTLIL::Cell::type
RTLIL::IdString type
Definition: rtlil.h:854
SigPool::check_any
bool check_any(RTLIL::SigSpec sig)
Definition: sigtools.h:100
RTLIL::Cell::getPort
const RTLIL::SigSpec & getPort(RTLIL::IdString portname) const
Definition: rtlil.cc:1809
RTLIL::Module::name
RTLIL::IdString name
Definition: rtlil.h:599
OptReduceWorker::opt_reduce
void opt_reduce(std::set< RTLIL::Cell * > &cells, SigSet< RTLIL::Cell * > &drivers, RTLIL::Cell *cell)
Definition: opt_reduce.cc:40
SigPool::check_all
bool check_all(RTLIL::SigSpec sig)
Definition: sigtools.h:108
OptReduceWorker::opt_mux_bits
void opt_mux_bits(RTLIL::Cell *cell)
Definition: opt_reduce.cc:167
SigPool::add
void add(RTLIL::SigSpec sig)
Definition: sigtools.h:41
RTLIL::Module::cells_
std::map< RTLIL::IdString, RTLIL::Cell * > cells_
Definition: rtlil.h:596
log
void log(const char *format,...)
Definition: log.cc:180
SigSet::insert
void insert(RTLIL::SigSpec sig, T data)
Definition: sigtools.h:152

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Member Function Documentation

void OptReduceWorker::opt_mux ( RTLIL::Cell *  cell)
inline

Definition at line 101 of file opt_reduce.cc.

102  {
103  RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A"));
104  RTLIL::SigSpec sig_b = assign_map(cell->getPort("\\B"));
105  RTLIL::SigSpec sig_s = assign_map(cell->getPort("\\S"));
106 
107  RTLIL::SigSpec new_sig_b, new_sig_s;
108  std::set<RTLIL::SigSpec> handled_sig;
109 
110  handled_sig.insert(sig_a);
111  for (int i = 0; i < sig_s.size(); i++)
112  {
113  RTLIL::SigSpec this_b = sig_b.extract(i*sig_a.size(), sig_a.size());
114  if (handled_sig.count(this_b) > 0)
115  continue;
116 
117  RTLIL::SigSpec this_s = sig_s.extract(i, 1);
118  for (int j = i+1; j < sig_s.size(); j++) {
119  RTLIL::SigSpec that_b = sig_b.extract(j*sig_a.size(), sig_a.size());
120  if (this_b == that_b)
121  this_s.append(sig_s.extract(j, 1));
122  }
123 
124  if (this_s.size() > 1)
125  {
126  RTLIL::Cell *reduce_or_cell = module->addCell(NEW_ID, "$reduce_or");
127  reduce_or_cell->setPort("\\A", this_s);
128  reduce_or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
129  reduce_or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(this_s.size());
130  reduce_or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
131 
132  RTLIL::Wire *reduce_or_wire = module->addWire(NEW_ID);
133  this_s = RTLIL::SigSpec(reduce_or_wire);
134  reduce_or_cell->setPort("\\Y", this_s);
135  }
136 
137  new_sig_b.append(this_b);
138  new_sig_s.append(this_s);
139  handled_sig.insert(this_b);
140  }
141 
142  if (new_sig_s.size() != sig_s.size()) {
143  log(" New ctrl vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_s));
144  did_something = true;
145  total_count++;
146  }
147 
148  if (new_sig_s.size() == 0)
149  {
150  module->connect(RTLIL::SigSig(cell->getPort("\\Y"), cell->getPort("\\A")));
151  assign_map.add(cell->getPort("\\Y"), cell->getPort("\\A"));
152  module->remove(cell);
153  }
154  else
155  {
156  cell->setPort("\\B", new_sig_b);
157  cell->setPort("\\S", new_sig_s);
158  if (new_sig_s.size() > 1) {
159  cell->parameters["\\S_WIDTH"] = RTLIL::Const(new_sig_s.size());
160  } else {
161  cell->type = "$mux";
162  cell->parameters.erase("\\S_WIDTH");
163  }
164  }
165  }
RTLIL::IdString::c_str
const char * c_str() const
Definition: rtlil.h:178
RTLIL::Module::addCell
RTLIL::Cell * addCell(RTLIL::IdString name, RTLIL::IdString type)
Definition: rtlil.cc:1353
OptReduceWorker::module
RTLIL::Module * module
Definition: opt_reduce.cc:34
log_signal
const char * log_signal(const RTLIL::SigSpec &sig, bool autoint)
Definition: log.cc:269
RTLIL::Cell::name
RTLIL::IdString name
Definition: rtlil.h:853
RTLIL::Cell::setPort
void setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
Definition: rtlil.cc:1789
OptReduceWorker::assign_map
SigMap assign_map
Definition: opt_reduce.cc:35
RTLIL::Cell::type
RTLIL::IdString type
Definition: rtlil.h:854
RTLIL::Cell::parameters
std::map< RTLIL::IdString, RTLIL::Const > parameters
Definition: rtlil.h:856
RTLIL::SigSpec::size
int size() const
Definition: rtlil.h:1019
RTLIL::Module::connect
void connect(const RTLIL::SigSig &conn)
Definition: rtlil.cc:1278
RTLIL::Cell::getPort
const RTLIL::SigSpec & getPort(RTLIL::IdString portname) const
Definition: rtlil.cc:1809
RTLIL::Module::addWire
RTLIL::Wire * addWire(RTLIL::IdString name, int width=1)
Definition: rtlil.cc:1331
NEW_ID
#define NEW_ID
Definition: yosys.h:166
RTLIL::Module::remove
void remove(const std::set< RTLIL::Wire * > &wires)
Definition: rtlil.cc:1158
log
void log(const char *format,...)
Definition: log.cc:180
RTLIL::SigSpec::extract
RTLIL::SigSpec extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other=NULL) const
Definition: rtlil.cc:2414
RTLIL::SigSpec::append
void append(const RTLIL::SigSpec &signal)
Definition: rtlil.cc:2523
SigMap::add
void add(RTLIL::SigSpec from, RTLIL::SigSpec to)
Definition: sigtools.h:347
RTLIL::SigSig
std::pair< SigSpec, SigSpec > SigSig
Definition: rtlil.h:71

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void OptReduceWorker::opt_mux_bits ( RTLIL::Cell *  cell)
inline

Definition at line 167 of file opt_reduce.cc.

168  {
169  std::vector<RTLIL::SigBit> sig_a = assign_map(cell->getPort("\\A")).to_sigbit_vector();
170  std::vector<RTLIL::SigBit> sig_b = assign_map(cell->getPort("\\B")).to_sigbit_vector();
171  std::vector<RTLIL::SigBit> sig_y = assign_map(cell->getPort("\\Y")).to_sigbit_vector();
172 
173  std::vector<RTLIL::SigBit> new_sig_y;
174  RTLIL::SigSig old_sig_conn;
175 
176  std::vector<std::vector<RTLIL::SigBit>> consolidated_in_tuples;
177  std::map<std::vector<RTLIL::SigBit>, RTLIL::SigBit> consolidated_in_tuples_map;
178 
179  for (int i = 0; i < int(sig_y.size()); i++)
180  {
181  std::vector<RTLIL::SigBit> in_tuple;
182  bool all_tuple_bits_same = true;
183 
184  in_tuple.push_back(sig_a.at(i));
185  for (int j = i; j < int(sig_b.size()); j += int(sig_a.size())) {
186  if (sig_b.at(j) != sig_a.at(i))
187  all_tuple_bits_same = false;
188  in_tuple.push_back(sig_b.at(j));
189  }
190 
191  if (all_tuple_bits_same)
192  {
193  old_sig_conn.first.append_bit(sig_y.at(i));
194  old_sig_conn.second.append_bit(sig_a.at(i));
195  }
196  else if (consolidated_in_tuples_map.count(in_tuple))
197  {
198  old_sig_conn.first.append_bit(sig_y.at(i));
199  old_sig_conn.second.append_bit(consolidated_in_tuples_map.at(in_tuple));
200  }
201  else
202  {
203  consolidated_in_tuples_map[in_tuple] = sig_y.at(i);
204  consolidated_in_tuples.push_back(in_tuple);
205  new_sig_y.push_back(sig_y.at(i));
206  }
207  }
208 
209  if (new_sig_y.size() != sig_y.size())
210  {
211  log(" Consolidated identical input bits for %s cell %s:\n", cell->type.c_str(), cell->name.c_str());
212  log(" Old ports: A=%s, B=%s, Y=%s\n", log_signal(cell->getPort("\\A")),
213  log_signal(cell->getPort("\\B")), log_signal(cell->getPort("\\Y")));
214 
215  cell->setPort("\\A", RTLIL::SigSpec());
216  for (auto &in_tuple : consolidated_in_tuples) {
217  RTLIL::SigSpec new_a = cell->getPort("\\A");
218  new_a.append(in_tuple.at(0));
219  cell->setPort("\\A", new_a);
220  }
221 
222  cell->setPort("\\B", RTLIL::SigSpec());
223  for (int i = 1; i <= cell->getPort("\\S").size(); i++)
224  for (auto &in_tuple : consolidated_in_tuples) {
225  RTLIL::SigSpec new_b = cell->getPort("\\B");
226  new_b.append(in_tuple.at(i));
227  cell->setPort("\\B", new_b);
228  }
229 
230  cell->parameters["\\WIDTH"] = RTLIL::Const(new_sig_y.size());
231  cell->setPort("\\Y", new_sig_y);
232 
233  log(" New ports: A=%s, B=%s, Y=%s\n", log_signal(cell->getPort("\\A")),
234  log_signal(cell->getPort("\\B")), log_signal(cell->getPort("\\Y")));
235  log(" New connections: %s = %s\n", log_signal(old_sig_conn.first), log_signal(old_sig_conn.second));
236 
237  module->connect(old_sig_conn);
238  module->check();
239 
240  did_something = true;
241  total_count++;
242  }
243  }
RTLIL::IdString::c_str
const char * c_str() const
Definition: rtlil.h:178
OptReduceWorker::module
RTLIL::Module * module
Definition: opt_reduce.cc:34
log_signal
const char * log_signal(const RTLIL::SigSpec &sig, bool autoint)
Definition: log.cc:269
RTLIL::Cell::name
RTLIL::IdString name
Definition: rtlil.h:853
RTLIL::Cell::setPort
void setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
Definition: rtlil.cc:1789
OptReduceWorker::assign_map
SigMap assign_map
Definition: opt_reduce.cc:35
RTLIL::Cell::type
RTLIL::IdString type
Definition: rtlil.h:854
RTLIL::Cell::parameters
std::map< RTLIL::IdString, RTLIL::Const > parameters
Definition: rtlil.h:856
RTLIL::SigSpec::size
int size() const
Definition: rtlil.h:1019
RTLIL::Module::check
virtual void check()
Definition: rtlil.cc:948
RTLIL::Module::connect
void connect(const RTLIL::SigSig &conn)
Definition: rtlil.cc:1278
RTLIL::Cell::getPort
const RTLIL::SigSpec & getPort(RTLIL::IdString portname) const
Definition: rtlil.cc:1809
log
void log(const char *format,...)
Definition: log.cc:180
RTLIL::SigSpec::append
void append(const RTLIL::SigSpec &signal)
Definition: rtlil.cc:2523
RTLIL::SigSig
std::pair< SigSpec, SigSpec > SigSig
Definition: rtlil.h:71

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void OptReduceWorker::opt_reduce ( std::set< RTLIL::Cell * > &  cells,
SigSet< RTLIL::Cell * > &  drivers,
RTLIL::Cell *  cell 
)
inline

Definition at line 40 of file opt_reduce.cc.

41  {
42  if (cells.count(cell) == 0)
43  return;
44  cells.erase(cell);
45 
46  RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A"));
47  std::set<RTLIL::SigBit> new_sig_a_bits;
48 
49  for (auto &bit : sig_a.to_sigbit_set())
50  {
51  if (bit == RTLIL::State::S0) {
52  if (cell->type == "$reduce_and") {
53  new_sig_a_bits.clear();
54  new_sig_a_bits.insert(RTLIL::State::S0);
55  break;
56  }
57  continue;
58  }
59  if (bit == RTLIL::State::S1) {
60  if (cell->type == "$reduce_or") {
61  new_sig_a_bits.clear();
62  new_sig_a_bits.insert(RTLIL::State::S1);
63  break;
64  }
65  continue;
66  }
67  if (bit.wire == NULL) {
68  new_sig_a_bits.insert(bit);
69  continue;
70  }
71 
72  bool imported_children = false;
73  for (auto child_cell : drivers.find(bit)) {
74  if (child_cell->type == cell->type) {
75  opt_reduce(cells, drivers, child_cell);
76  if (child_cell->getPort("\\Y")[0] == bit) {
77  std::set<RTLIL::SigBit> child_sig_a_bits = assign_map(child_cell->getPort("\\A")).to_sigbit_set();
78  new_sig_a_bits.insert(child_sig_a_bits.begin(), child_sig_a_bits.end());
79  } else
80  new_sig_a_bits.insert(RTLIL::State::S0);
81  imported_children = true;
82  }
83  }
84  if (!imported_children)
85  new_sig_a_bits.insert(bit);
86  }
87 
88  RTLIL::SigSpec new_sig_a(new_sig_a_bits);
89 
90  if (new_sig_a != sig_a || sig_a.size() != cell->getPort("\\A").size()) {
91  log(" New input vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_a));
92  did_something = true;
93  total_count++;
94  }
95 
96  cell->setPort("\\A", new_sig_a);
97  cell->parameters["\\A_WIDTH"] = RTLIL::Const(new_sig_a.size());
98  return;
99  }
RTLIL::IdString::c_str
const char * c_str() const
Definition: rtlil.h:178
RTLIL::SigSpec::to_sigbit_set
std::set< RTLIL::SigBit > to_sigbit_set() const
Definition: rtlil.cc:2909
log_signal
const char * log_signal(const RTLIL::SigSpec &sig, bool autoint)
Definition: log.cc:269
SigMap::clear
void clear()
Definition: sigtools.h:263
RTLIL::Cell::name
RTLIL::IdString name
Definition: rtlil.h:853
RTLIL::Cell::setPort
void setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
Definition: rtlil.cc:1789
OptReduceWorker::assign_map
SigMap assign_map
Definition: opt_reduce.cc:35
RTLIL::Cell::type
RTLIL::IdString type
Definition: rtlil.h:854
RTLIL::Cell::parameters
std::map< RTLIL::IdString, RTLIL::Const > parameters
Definition: rtlil.h:856
RTLIL::SigSpec::size
int size() const
Definition: rtlil.h:1019
RTLIL::Cell::getPort
const RTLIL::SigSpec & getPort(RTLIL::IdString portname) const
Definition: rtlil.cc:1809
OptReduceWorker::opt_reduce
void opt_reduce(std::set< RTLIL::Cell * > &cells, SigSet< RTLIL::Cell * > &drivers, RTLIL::Cell *cell)
Definition: opt_reduce.cc:40
NULL
#define NULL
Definition: NumberlikeArray.hh:6
log
void log(const char *format,...)
Definition: log.cc:180
SigSet::find
void find(RTLIL::SigSpec sig, std::set< T > &result)
Definition: sigtools.h:187

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Field Documentation

SigMap OptReduceWorker::assign_map

Definition at line 35 of file opt_reduce.cc.

RTLIL::Design* OptReduceWorker::design

Definition at line 33 of file opt_reduce.cc.

bool OptReduceWorker::did_something

Definition at line 38 of file opt_reduce.cc.

RTLIL::Module* OptReduceWorker::module

Definition at line 34 of file opt_reduce.cc.

int OptReduceWorker::total_count

Definition at line 37 of file opt_reduce.cc.

The documentation for this struct was generated from the following file: