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Public Member Functions | Data Fields
SpliceWorker Struct Reference
+ Collaboration diagram for SpliceWorker:

Public Member Functions

 SpliceWorker (RTLIL::Design *design, RTLIL::Module *module)
 
RTLIL::SigSpec get_sliced_signal (RTLIL::SigSpec sig)
 
RTLIL::SigSpec get_spliced_signal (RTLIL::SigSpec sig)
 
void run ()
 

Data Fields

RTLIL::Design * design
 
RTLIL::Module * module
 
bool sel_by_cell
 
bool sel_by_wire
 
bool sel_any_bit
 
bool no_outputs
 
std::set< RTLIL::IdString > ports
 
std::set< RTLIL::IdString > no_ports
 
CellTypes ct
 
SigMap sigmap
 
std::vector< RTLIL::SigBit > driven_bits
 
std::map< RTLIL::SigBit, int > driven_bits_map
 
std::set< RTLIL::SigSpec > driven_chunks
 
std::map< RTLIL::SigSpec,
RTLIL::SigSpec > 		spliced_signals_cache
 
std::map< RTLIL::SigSpec,
RTLIL::SigSpec > 		sliced_signals_cache
 

Detailed Description

Definition at line 30 of file splice.cc.

Constructor & Destructor Documentation

SpliceWorker::SpliceWorker ( RTLIL::Design *  design,
RTLIL::Module *  module 
)
inline

Definition at line 52 of file splice.cc.

52  : design(design), module(module), ct(design), sigmap(module)
53  {
54  }
SpliceWorker::module
RTLIL::Module * module
Definition: splice.cc:33
SpliceWorker::sigmap
SigMap sigmap
Definition: splice.cc:43
SpliceWorker::ct
CellTypes ct
Definition: splice.cc:42
SpliceWorker::design
RTLIL::Design * design
Definition: splice.cc:32

Member Function Documentation

RTLIL::SigSpec SpliceWorker::get_sliced_signal ( RTLIL::SigSpec  sig)
inline

Definition at line 56 of file splice.cc.

57  {
58  if (sig.size() == 0 || sig.is_fully_const())
59  return sig;
60 
61  if (sliced_signals_cache.count(sig))
62  return sliced_signals_cache.at(sig);
63 
64  int offset = 0;
65  int p = driven_bits_map.at(sig.extract(0, 1).to_single_sigbit()) - 1;
66  while (driven_bits.at(p) != RTLIL::State::Sm)
67  p--, offset++;
68 
69  RTLIL::SigSpec sig_a;
70  for (p++; driven_bits.at(p) != RTLIL::State::Sm; p++)
71  sig_a.append(driven_bits.at(p));
72 
73  RTLIL::SigSpec new_sig = sig;
74 
75  if (sig_a.size() != sig.size()) {
76  RTLIL::Cell *cell = module->addCell(NEW_ID, "$slice");
77  cell->parameters["\\OFFSET"] = offset;
78  cell->parameters["\\A_WIDTH"] = sig_a.size();
79  cell->parameters["\\Y_WIDTH"] = sig.size();
80  cell->setPort("\\A", sig_a);
81  cell->setPort("\\Y", module->addWire(NEW_ID, sig.size()));
82  new_sig = cell->getPort("\\Y");
83  }
84 
85  sliced_signals_cache[sig] = new_sig;
86 
87  return new_sig;
88  }
RTLIL::Module::addCell
RTLIL::Cell * addCell(RTLIL::IdString name, RTLIL::IdString type)
Definition: rtlil.cc:1353
SpliceWorker::sliced_signals_cache
std::map< RTLIL::SigSpec, RTLIL::SigSpec > sliced_signals_cache
Definition: splice.cc:50
RTLIL::Cell::setPort
void setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
Definition: rtlil.cc:1789
RTLIL::Cell::parameters
std::map< RTLIL::IdString, RTLIL::Const > parameters
Definition: rtlil.h:856
RTLIL::SigSpec::size
int size() const
Definition: rtlil.h:1019
SpliceWorker::module
RTLIL::Module * module
Definition: splice.cc:33
RTLIL::Cell::getPort
const RTLIL::SigSpec & getPort(RTLIL::IdString portname) const
Definition: rtlil.cc:1809
RTLIL::SigSpec::is_fully_const
bool is_fully_const() const
Definition: rtlil.cc:2763
RTLIL::Module::addWire
RTLIL::Wire * addWire(RTLIL::IdString name, int width=1)
Definition: rtlil.cc:1331
SpliceWorker::driven_bits
std::vector< RTLIL::SigBit > driven_bits
Definition: splice.cc:45
NEW_ID
#define NEW_ID
Definition: yosys.h:166
RTLIL::SigSpec::to_single_sigbit
RTLIL::SigBit to_single_sigbit() const
Definition: rtlil.cc:2945
SpliceWorker::driven_bits_map
std::map< RTLIL::SigBit, int > driven_bits_map
Definition: splice.cc:46
RTLIL::SigSpec::extract
RTLIL::SigSpec extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other=NULL) const
Definition: rtlil.cc:2414
RTLIL::SigSpec::append
void append(const RTLIL::SigSpec &signal)
Definition: rtlil.cc:2523

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RTLIL::SigSpec SpliceWorker::get_spliced_signal ( RTLIL::SigSpec  sig)
inline

Definition at line 90 of file splice.cc.

91  {
92  if (sig.size() == 0 || sig.is_fully_const())
93  return sig;
94 
95  if (spliced_signals_cache.count(sig))
96  return spliced_signals_cache.at(sig);
97 
98  int last_bit = -1;
99  std::vector<RTLIL::SigSpec> chunks;
100 
101  for (auto &bit : sig.to_sigbit_vector())
102  {
103  if (bit.wire == NULL)
104  {
105  if (last_bit == 0)
106  chunks.back().append(bit);
107  else
108  chunks.push_back(bit);
109  last_bit = 0;
110  continue;
111  }
112 
113  if (driven_bits_map.count(bit))
114  {
115  int this_bit = driven_bits_map.at(bit);
116  if (last_bit+1 == this_bit)
117  chunks.back().append(bit);
118  else
119  chunks.push_back(bit);
120  last_bit = this_bit;
121  continue;
122  }
123 
124  log(" Failed to generate spliced signal %s.\n", log_signal(sig));
125  spliced_signals_cache[sig] = sig;
126  return sig;
127  }
128 
129 
130  RTLIL::SigSpec new_sig = get_sliced_signal(chunks.front());
131  for (size_t i = 1; i < chunks.size(); i++) {
132  RTLIL::SigSpec sig2 = get_sliced_signal(chunks[i]);
133  RTLIL::Cell *cell = module->addCell(NEW_ID, "$concat");
134  cell->parameters["\\A_WIDTH"] = new_sig.size();
135  cell->parameters["\\B_WIDTH"] = sig2.size();
136  cell->setPort("\\A", new_sig);
137  cell->setPort("\\B", sig2);
138  cell->setPort("\\Y", module->addWire(NEW_ID, new_sig.size() + sig2.size()));
139  new_sig = cell->getPort("\\Y");
140  }
141 
142  spliced_signals_cache[sig] = new_sig;
143 
144  log(" Created spliced signal: %s -> %s\n", log_signal(sig), log_signal(new_sig));
145  return new_sig;
146  }
RTLIL::Module::addCell
RTLIL::Cell * addCell(RTLIL::IdString name, RTLIL::IdString type)
Definition: rtlil.cc:1353
log_signal
const char * log_signal(const RTLIL::SigSpec &sig, bool autoint)
Definition: log.cc:269
RTLIL::Cell::setPort
void setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
Definition: rtlil.cc:1789
RTLIL::Cell::parameters
std::map< RTLIL::IdString, RTLIL::Const > parameters
Definition: rtlil.h:856
RTLIL::SigSpec::size
int size() const
Definition: rtlil.h:1019
SpliceWorker::module
RTLIL::Module * module
Definition: splice.cc:33
SpliceWorker::spliced_signals_cache
std::map< RTLIL::SigSpec, RTLIL::SigSpec > spliced_signals_cache
Definition: splice.cc:49
RTLIL::Cell::getPort
const RTLIL::SigSpec & getPort(RTLIL::IdString portname) const
Definition: rtlil.cc:1809
RTLIL::SigSpec::is_fully_const
bool is_fully_const() const
Definition: rtlil.cc:2763
RTLIL::Module::addWire
RTLIL::Wire * addWire(RTLIL::IdString name, int width=1)
Definition: rtlil.cc:1331
NEW_ID
#define NEW_ID
Definition: yosys.h:166
SpliceWorker::get_sliced_signal
RTLIL::SigSpec get_sliced_signal(RTLIL::SigSpec sig)
Definition: splice.cc:56
NULL
#define NULL
Definition: NumberlikeArray.hh:6
SpliceWorker::driven_bits_map
std::map< RTLIL::SigBit, int > driven_bits_map
Definition: splice.cc:46
log
void log(const char *format,...)
Definition: log.cc:180
RTLIL::SigSpec::to_sigbit_vector
std::vector< RTLIL::SigBit > to_sigbit_vector() const
Definition: rtlil.cc:2921

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void SpliceWorker::run ( )
inline

Definition at line 148 of file splice.cc.

149  {
150  log("Splicing signals in module %s:\n", RTLIL::id2cstr(module->name));
151 
152  driven_bits.push_back(RTLIL::State::Sm);
153  driven_bits.push_back(RTLIL::State::Sm);
154 
155  for (auto &it : module->wires_)
156  if (it.second->port_input) {
157  RTLIL::SigSpec sig = sigmap(it.second);
158  driven_chunks.insert(sig);
159  for (auto &bit : sig.to_sigbit_vector())
160  driven_bits.push_back(bit);
161  driven_bits.push_back(RTLIL::State::Sm);
162  }
163 
164  for (auto &it : module->cells_)
165  for (auto &conn : it.second->connections())
166  if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first)) {
167  RTLIL::SigSpec sig = sigmap(conn.second);
168  driven_chunks.insert(sig);
169  for (auto &bit : sig.to_sigbit_vector())
170  driven_bits.push_back(bit);
171  driven_bits.push_back(RTLIL::State::Sm);
172  }
173 
174  driven_bits.push_back(RTLIL::State::Sm);
175 
176  for (size_t i = 0; i < driven_bits.size(); i++)
177  driven_bits_map[driven_bits[i]] = i;
178 
179  SigPool selected_bits;
180  if (!sel_by_cell)
181  for (auto &it : module->wires_)
182  if (design->selected(module, it.second))
183  selected_bits.add(sigmap(it.second));
184 
185  for (auto &it : module->cells_) {
186  if (!sel_by_wire && !design->selected(module, it.second))
187  continue;
188  for (auto &conn : it.second->connections_)
189  if (ct.cell_input(it.second->type, conn.first)) {
190  if (ports.size() > 0 && !ports.count(conn.first))
191  continue;
192  if (no_ports.size() > 0 && no_ports.count(conn.first))
193  continue;
194  RTLIL::SigSpec sig = sigmap(conn.second);
195  if (!sel_by_cell) {
196  if (!sel_any_bit && !selected_bits.check_all(sig))
197  continue;
198  if (sel_any_bit && !selected_bits.check_any(sig))
199  continue;
200  }
201  if (driven_chunks.count(sig) > 0)
202  continue;
203  conn.second = get_spliced_signal(sig);
204  }
205  }
206 
207  std::vector<std::pair<RTLIL::Wire*, RTLIL::SigSpec>> rework_wires;
208 
209  for (auto &it : module->wires_)
210  if (!no_outputs && it.second->port_output) {
211  if (!design->selected(module, it.second))
212  continue;
213  RTLIL::SigSpec sig = sigmap(it.second);
214  if (driven_chunks.count(sig) > 0)
215  continue;
216  RTLIL::SigSpec new_sig = get_spliced_signal(sig);
217  if (new_sig != sig)
218  rework_wires.push_back(std::pair<RTLIL::Wire*, RTLIL::SigSpec>(it.second, new_sig));
219  } else
220  if (!it.second->port_input) {
221  RTLIL::SigSpec sig = sigmap(it.second);
222  if (spliced_signals_cache.count(sig) && spliced_signals_cache.at(sig) != sig)
223  rework_wires.push_back(std::pair<RTLIL::Wire*, RTLIL::SigSpec>(it.second, spliced_signals_cache.at(sig)));
224  else if (sliced_signals_cache.count(sig) && sliced_signals_cache.at(sig) != sig)
225  rework_wires.push_back(std::pair<RTLIL::Wire*, RTLIL::SigSpec>(it.second, sliced_signals_cache.at(sig)));
226  }
227 
228  for (auto &it : rework_wires)
229  {
230  RTLIL::IdString orig_name = it.first->name;
231  module->rename(it.first, NEW_ID);
232 
233  RTLIL::Wire *new_port = module->addWire(orig_name, it.first);
234  it.first->port_id = 0;
235  it.first->port_input = false;
236  it.first->port_output = false;
237 
238  module->connect(RTLIL::SigSig(new_port, it.second));
239  }
240  }
RTLIL::Design::selected
bool selected(T1 *module) const
Definition: rtlil.h:551
SpliceWorker::sel_by_cell
bool sel_by_cell
Definition: splice.cc:35
SpliceWorker::sliced_signals_cache
std::map< RTLIL::SigSpec, RTLIL::SigSpec > sliced_signals_cache
Definition: splice.cc:50
RTLIL::Module::wires_
std::map< RTLIL::IdString, RTLIL::Wire * > wires_
Definition: rtlil.h:595
SpliceWorker::get_spliced_signal
RTLIL::SigSpec get_spliced_signal(RTLIL::SigSpec sig)
Definition: splice.cc:90
SpliceWorker::ports
std::set< RTLIL::IdString > ports
Definition: splice.cc:39
RTLIL::Wire::port_id
int port_id
Definition: rtlil.h:826
SpliceWorker::no_outputs
bool no_outputs
Definition: splice.cc:38
SpliceWorker::module
RTLIL::Module * module
Definition: splice.cc:33
SpliceWorker::driven_chunks
std::set< RTLIL::SigSpec > driven_chunks
Definition: splice.cc:48
CellTypes::cell_known
bool cell_known(RTLIL::IdString type)
Definition: celltypes.h:188
SigPool::check_any
bool check_any(RTLIL::SigSpec sig)
Definition: sigtools.h:100
RTLIL::Module::connect
void connect(const RTLIL::SigSig &conn)
Definition: rtlil.cc:1278
SpliceWorker::spliced_signals_cache
std::map< RTLIL::SigSpec, RTLIL::SigSpec > spliced_signals_cache
Definition: splice.cc:49
CellTypes::cell_output
bool cell_output(RTLIL::IdString type, RTLIL::IdString port)
Definition: celltypes.h:193
SpliceWorker::sigmap
SigMap sigmap
Definition: splice.cc:43
RTLIL::Module::addWire
RTLIL::Wire * addWire(RTLIL::IdString name, int width=1)
Definition: rtlil.cc:1331
SpliceWorker::driven_bits
std::vector< RTLIL::SigBit > driven_bits
Definition: splice.cc:45
RTLIL::Module::name
RTLIL::IdString name
Definition: rtlil.h:599
NEW_ID
#define NEW_ID
Definition: yosys.h:166
SigPool::check_all
bool check_all(RTLIL::SigSpec sig)
Definition: sigtools.h:108
RTLIL::id2cstr
static const char * id2cstr(const RTLIL::IdString &str)
Definition: rtlil.h:267
SigPool::add
void add(RTLIL::SigSpec sig)
Definition: sigtools.h:41
RTLIL::Module::cells_
std::map< RTLIL::IdString, RTLIL::Cell * > cells_
Definition: rtlil.h:596
SpliceWorker::no_ports
std::set< RTLIL::IdString > no_ports
Definition: splice.cc:40
SpliceWorker::driven_bits_map
std::map< RTLIL::SigBit, int > driven_bits_map
Definition: splice.cc:46
SpliceWorker::sel_by_wire
bool sel_by_wire
Definition: splice.cc:36
log
void log(const char *format,...)
Definition: log.cc:180
SpliceWorker::ct
CellTypes ct
Definition: splice.cc:42
CellTypes::cell_input
bool cell_input(RTLIL::IdString type, RTLIL::IdString port)
Definition: celltypes.h:199
SpliceWorker::sel_any_bit
bool sel_any_bit
Definition: splice.cc:37
SpliceWorker::design
RTLIL::Design * design
Definition: splice.cc:32
RTLIL::SigSig
std::pair< SigSpec, SigSpec > SigSig
Definition: rtlil.h:71
RTLIL::SigSpec::to_sigbit_vector
std::vector< RTLIL::SigBit > to_sigbit_vector() const
Definition: rtlil.cc:2921
RTLIL::Module::rename
void rename(RTLIL::Wire *wire, RTLIL::IdString new_name)
Definition: rtlil.cc:1185

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Field Documentation

CellTypes SpliceWorker::ct

Definition at line 42 of file splice.cc.

RTLIL::Design* SpliceWorker::design

Definition at line 32 of file splice.cc.

std::vector<RTLIL::SigBit> SpliceWorker::driven_bits

Definition at line 45 of file splice.cc.

std::map<RTLIL::SigBit, int> SpliceWorker::driven_bits_map

Definition at line 46 of file splice.cc.

std::set<RTLIL::SigSpec> SpliceWorker::driven_chunks

Definition at line 48 of file splice.cc.

RTLIL::Module* SpliceWorker::module

Definition at line 33 of file splice.cc.

bool SpliceWorker::no_outputs

Definition at line 38 of file splice.cc.

std::set<RTLIL::IdString> SpliceWorker::no_ports

Definition at line 40 of file splice.cc.

std::set<RTLIL::IdString> SpliceWorker::ports

Definition at line 39 of file splice.cc.

bool SpliceWorker::sel_any_bit

Definition at line 37 of file splice.cc.

bool SpliceWorker::sel_by_cell

Definition at line 35 of file splice.cc.

bool SpliceWorker::sel_by_wire

Definition at line 36 of file splice.cc.

SigMap SpliceWorker::sigmap

Definition at line 43 of file splice.cc.

std::map<RTLIL::SigSpec, RTLIL::SigSpec> SpliceWorker::sliced_signals_cache

Definition at line 50 of file splice.cc.

std::map<RTLIL::SigSpec, RTLIL::SigSpec> SpliceWorker::spliced_signals_cache

Definition at line 49 of file splice.cc.

The documentation for this struct was generated from the following file: