read_netlist.h File Reference

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Functions
void	read_netlist (INP const char *net_file, INP const t_arch *arch, OUTP int *L_num_blocks, OUTP struct s_block *block_list[], OUTP int *L_num_nets, OUTP struct s_net *net_list[])
void	free_logical_blocks (void)
void	free_logical_nets (void)

Function Documentation

void free_logical_blocks

(

void

)

Definition at line 1305 of file read_netlist.c.

                               {
    int iblk, i;
    t_model_ports *port;
    struct s_linked_vptr *tvptr, *next;

    for (iblk = 0; iblk < num_logical_blocks; iblk++) {
        port = logical_block[iblk].model->inputs;
        i = 0;
        while (port) {
            if (!port->is_clock) {
                free(logical_block[iblk].input_nets[i]);
                if (logical_block[iblk].input_net_tnodes) {
                    if (logical_block[iblk].input_net_tnodes[i])
                        free(logical_block[iblk].input_net_tnodes[i]);
                }
                i++;
            }
            port = port->next;
        }
        if (logical_block[iblk].input_net_tnodes) 
            free(logical_block[iblk].input_net_tnodes);
        
        tvptr = logical_block[iblk].packed_molecules;
        while (tvptr != NULL) {
            next = tvptr->next;
            free(tvptr);
            tvptr = next;
        }

        free(logical_block[iblk].input_nets);
        port = logical_block[iblk].model->outputs;
        i = 0;
        while (port) {
            free(logical_block[iblk].output_nets[i]);
            if (logical_block[iblk].output_net_tnodes) {
                if (logical_block[iblk].output_net_tnodes[i])
                    free(logical_block[iblk].output_net_tnodes[i]);
            }
            i++;
            port = port->next;
        }
        if (logical_block[iblk].output_net_tnodes) {
            free(logical_block[iblk].output_net_tnodes);
        }
        free(logical_block[iblk].output_nets);
        free(logical_block[iblk].name);
        tvptr = logical_block[iblk].truth_table;
        while (tvptr != NULL) {
            if (tvptr->data_vptr)
                free(tvptr->data_vptr);
            next = tvptr->next;
            free(tvptr);
            tvptr = next;
        }
    }
    free(logical_block);
    logical_block = NULL;
}

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void free_logical_nets

(

void

)

Definition at line 1365 of file read_netlist.c.

                             {
    int inet;

    for (inet = 0; inet < num_logical_nets; inet++) {
        free(vpack_net[inet].name);
        free(vpack_net[inet].node_block);
        free(vpack_net[inet].node_block_port);
        free(vpack_net[inet].node_block_pin);
    }
    free(vpack_net);
    vpack_net = NULL;
}

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void read_netlist	(	INP const char *	net_file,
		INP const t_arch *	arch,
		OUTP int *	L_num_blocks,
		OUTP struct s_block *	block_list[],
		OUTP int *	L_num_nets,
		OUTP struct s_net *	net_list[]
	)

Author: Jason Luu Date: May 2009

Read a circuit netlist in XML format and populate the netlist data structures for VPR

Initializes the block_list with info from a netlist net_file - Name of the netlist file to read num_blocks - number of CLBs in netlist block_list - array of blocks in netlist [0..num_blocks - 1] num_nets - number of nets in netlist net_list - nets in netlist [0..num_nets - 1]

Definition at line 72 of file read_netlist.c.

                                                             {
    ezxml_t Cur, Prev, Top;
    int i;
    const char *Prop;
    int bcount;
    struct s_block *blist;
    int ext_ncount;
    struct s_net *ext_nlist;
    struct s_hash **vpack_net_hash, **logical_block_hash, *temp_hash;
    char **circuit_inputs, **circuit_outputs, **circuit_clocks;
    int Count, Len;

    int num_primitives = 0;

    /* Parse the file */
    vpr_printf(TIO_MESSAGE_INFO, "Begin parsing packed FPGA netlist file.\n");
    Top = ezxml_parse_file(net_file);
    if (NULL == Top) {
        vpr_printf(TIO_MESSAGE_ERROR, "Unable to load netlist file '%s'.\n", net_file);
        exit(1);
    }
    vpr_printf(TIO_MESSAGE_INFO, "Finished parsing packed FPGA netlist file.\n");

    /* Root node should be block */
    CheckElement(Top, "block");

    /* Check top-level netlist attributes */
    Prop = FindProperty(Top, "name", TRUE);
    vpr_printf(TIO_MESSAGE_INFO, "Netlist generated from file '%s'.\n", Prop);
    ezxml_set_attr(Top, "name", NULL);

    Prop = FindProperty(Top, "instance", TRUE);
    if (strcmp(Prop, "FPGA_packed_netlist[0]") != 0) {
        vpr_printf(TIO_MESSAGE_ERROR, "[Line %d] Expected instance to be \"FPGA_packed_netlist[0]\", found %s.",
                Top->line, Prop);
        exit(1);
    }
    ezxml_set_attr(Top, "instance", NULL);

    /* Parse top-level netlist I/Os */
    Cur = FindElement(Top, "inputs", TRUE);
    circuit_inputs = GetNodeTokens(Cur);
    FreeNode(Cur);
    Cur = FindElement(Top, "outputs", TRUE);
    circuit_outputs = GetNodeTokens(Cur);
    FreeNode(Cur);

    Cur = FindElement(Top, "clocks", TRUE);
    CountTokensInString(Cur->txt, &Count, &Len);
    if (Count > 0) {
        circuit_clocks = GetNodeTokens(Cur);
    } else {
        circuit_clocks = NULL;
    }
    FreeNode(Cur);

    /* Parse all CLB blocks and all nets*/
    bcount = CountChildren(Top, "block", 1);
    blist = (struct s_block *) my_calloc(bcount, sizeof(t_block));

    /* create quick hash look up for vpack_net and logical_block 
        Also reset logical block data structure for pb
    */
    vpack_net_hash = alloc_hash_table();
    logical_block_hash = alloc_hash_table();
    for (i = 0; i < num_logical_nets; i++) {
        temp_hash = insert_in_hash_table(vpack_net_hash, vpack_net[i].name, i);
        assert(temp_hash->count == 1);
    }
    for (i = 0; i < num_logical_blocks; i++) {
        temp_hash = insert_in_hash_table(logical_block_hash, logical_block[i].name, i);
        logical_block[i].pb = NULL;
        assert(temp_hash->count == 1);
    }
    
    /* Prcoess netlist */

    Cur = Top->child;
    i = 0;
    while (Cur) {
        if (0 == strcmp(Cur->name, "block")) {
            CheckElement(Cur, "block");
            processComplexBlock(Cur, blist, i, &num_primitives, arch, vpack_net_hash, logical_block_hash);
            Prev = Cur;
            Cur = Cur->next;
            FreeNode(Prev);
            i++;
        } else {
            Cur = Cur->next;
        }
    }
    assert(i == bcount);
    assert(num_primitives == num_logical_blocks);

    /* Error check */
    for (i = 0; i < num_logical_blocks; i++) {
        if (logical_block[i].pb == NULL) {
            vpr_printf(TIO_MESSAGE_ERROR, ".blif file and .net file do not match, .net file missing atom %s.\n", 
                logical_block[i].name);
            exit(1);
        }
    }
    /* TODO: Add additional check to make sure net connections match */

    
    mark_constant_generators(bcount, blist, num_logical_nets, vpack_net);
    load_external_nets_and_cb(bcount, blist, num_logical_nets, vpack_net, &ext_ncount,
            &ext_nlist, circuit_clocks);

    /* TODO: create this function later
     check_top_IO_matches_IO_blocks(circuit_inputs, circuit_outputs, circuit_clocks, blist, bcount);
     */

    FreeTokens(&circuit_inputs);
    FreeTokens(&circuit_outputs);
    if (circuit_clocks)
        FreeTokens(&circuit_clocks);
    FreeNode(Top);

    /* load mapping between external nets and all nets */
    /* jluu TODO: Should use local variables here then assign to globals later, clean up later */
    clb_to_vpack_net_mapping = (int *) my_malloc(ext_ncount * sizeof(int));
    vpack_to_clb_net_mapping = (int *) my_malloc(num_logical_nets * sizeof(int));
    for (i = 0; i < num_logical_nets; i++) {
        vpack_to_clb_net_mapping[i] = OPEN;
    }

    for (i = 0; i < ext_ncount; i++) {
        temp_hash = get_hash_entry(vpack_net_hash, ext_nlist[i].name);
        assert(temp_hash != NULL);
        clb_to_vpack_net_mapping[i] = temp_hash->index;
        vpack_to_clb_net_mapping[temp_hash->index] = i;
    }

    /* Return blocks and nets */
    *L_num_blocks = bcount;
    *block_list = blist;
    *L_num_nets = ext_ncount;
    *net_list = ext_nlist;

    free_hash_table(logical_block_hash);
    free_hash_table(vpack_net_hash);
}

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