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power_sizing.c
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1 /*********************************************************************
2  * The following code is part of the power modelling feature of VTR.
3  *
4  * For support:
5  * http://code.google.com/p/vtr-verilog-to-routing/wiki/Power
6  *
7  * or email:
8  * vtr.power.estimation@gmail.com
9  *
10  * If you are using power estimation for your researach please cite:
11  *
12  * Jeffrey Goeders and Steven Wilton. VersaPower: Power Estimation
13  * for Diverse FPGA Architectures. In International Conference on
14  * Field Programmable Technology, 2012.
15  *
16  ********************************************************************/
17 
18 /**
19  * The functions in this file are used to count the transistors in the
20  * FPGA, for physical size estimations
21  */
22 
23 /************************* INCLUDES *********************************/
24 #include <cstring>
25 using namespace std;
26 
27 #include <assert.h>
28 
29 #include "power_sizing.h"
30 #include "power.h"
31 #include "globals.h"
32 #include "power_util.h"
33 /************************* GLOBALS **********************************/
34 static double g_MTA_area;
35 
36 /************************* FUNCTION DELCARATIONS ********************/
37 static double power_count_transistors_connectionbox(void);
38 static double power_count_transistors_mux(t_mux_arch * mux_arch);
39 static double power_count_transistors_mux_node(t_mux_node * mux_node,
40  float transistor_size);
41 static void power_mux_node_max_inputs(t_mux_node * mux_node,
42  float * max_inputs);
43 static double power_count_transistors_interc(t_interconnect * interc);
44 static double power_count_transistors_pb_node(t_pb_graph_node * pb_node);
45 static double power_count_transistors_switchbox(t_arch * arch);
46 static double power_count_transistors_primitive(t_pb_type * pb_type);
47 static double power_count_transistors_LUT(int LUT_inputs,
48  float transistor_size);
49 static double power_count_transistors_FF(float size);
50 static double power_count_transistor_SRAM_bit(void);
51 static double power_count_transistors_inv(float size);
52 static double power_count_transistors_trans_gate(float size);
53 static double power_count_transistors_levr();
54 static double power_MTAs(float size);
56  boolean pin_is_an_input);
57 static double power_transistors_for_pb_node(t_pb_graph_node * pb_node);
58 static double power_transistors_per_tile(t_arch * arch);
59 static void power_size_pb(void);
60 static void power_size_pb_rec(t_pb_graph_node * pb_node);
62  int * fanout, float * wirelength);
63 static double power_MTAs(float W_size);
64 static double power_MTAs_L(float L_size);
65 /************************* FUNCTION DEFINITIONS *********************/
66 
67 /**
68  * Counts the number of transistors in the largest connection box
69  */
71  double transistor_cnt = 0.;
72  int CLB_inputs;
73  float buffer_size;
74 
76  CLB_inputs = FILL_TYPE->pb_graph_head->num_input_pins[0];
77 
78  /* Buffers from Tracks */
83  buffer_size = max(1.0F, buffer_size);
84  transistor_cnt += g_solution_inf.channel_width
85  * power_count_transistors_buffer(buffer_size);
86 
87  /* Muxes to IPINs */
88  transistor_cnt += CLB_inputs
92 
93  return transistor_cnt;
94 }
95 
96 /**
97  * Counts the number of transistors in a buffer.
98  * - buffer_size: The final stage size of the buffer, relative to a minimum sized inverter
99  */
100 double power_count_transistors_buffer(float buffer_size) {
101  int stages;
102  float effort;
103  float stage_size;
104  int stage_idx;
105  double transistor_cnt = 0.;
106 
107  stages = power_calc_buffer_num_stages(buffer_size,
109  effort = calc_buffer_stage_effort(stages, buffer_size);
110 
111  stage_size = 1;
112  for (stage_idx = 0; stage_idx < stages; stage_idx++) {
113  transistor_cnt += power_count_transistors_inv(stage_size);
114  stage_size *= effort;
115  }
116 
117  return transistor_cnt;
118 }
119 
120 /**
121  * Counts the number of transistors in a multiplexer
122  * - mux_arch: The architecture of the multiplexer
123  */
124 static double power_count_transistors_mux(t_mux_arch * mux_arch) {
125  double transistor_cnt = 0.;
126  int lvl_idx;
127  float * max_inputs;
128 
129  /* SRAM bits */
130  max_inputs = (float*) my_calloc(mux_arch->levels, sizeof(float));
131  for (lvl_idx = 0; lvl_idx < mux_arch->levels; lvl_idx++) {
132  max_inputs[lvl_idx] = 0.;
133  }
134  power_mux_node_max_inputs(mux_arch->mux_graph_head, max_inputs);
135 
136  for (lvl_idx = 0; lvl_idx < mux_arch->levels; lvl_idx++) {
137  /* Assume there is decoder logic */
138  transistor_cnt += ceil(log(max_inputs[lvl_idx]) / log((double) 2.0))
140 
141  /*
142  if (mux_arch->encoding_types[lvl_idx] == ENCODING_DECODER) {
143  transistor_cnt += ceil(log2((float)max_inputs[lvl_idx]))
144  * power_cnt_transistor_SRAM_bit();
145  // TODO - Size of decoder
146  } else if (mux_arch->encoding_types[lvl_idx] == ENCODING_ONE_HOT) {
147  transistor_cnt += max_inputs[lvl_idx]
148  * power_cnt_transistor_SRAM_bit();
149  } else {
150  assert(0);
151  }
152  */
153  }
154 
155  transistor_cnt += power_count_transistors_mux_node(mux_arch->mux_graph_head,
156  mux_arch->transistor_size);
157  free(max_inputs);
158  return transistor_cnt;
159 }
160 
161 /**
162  * This function is used recursively to determine the largest single-level
163  * multiplexer at each level of a multi-level multiplexer
164  */
165 static void power_mux_node_max_inputs(t_mux_node * mux_node,
166  float * max_inputs) {
167 
168  max_inputs[mux_node->level] = max(max_inputs[mux_node->level],
169  static_cast<float>(mux_node->num_inputs));
170 
171  if (mux_node->level != 0) {
172  int child_idx;
173 
174  for (child_idx = 0; child_idx < mux_node->num_inputs; child_idx++) {
175  power_mux_node_max_inputs(&mux_node->children[child_idx],
176  max_inputs);
177  }
178  }
179 }
180 
181 /**
182  * This function is used recursively to count the number of transistors in a multiplexer
183  */
185  float transistor_size) {
186  int input_idx;
187  double transistor_cnt = 0.;
188 
189  if (mux_node->num_inputs != 1) {
190  for (input_idx = 0; input_idx < mux_node->num_inputs; input_idx++) {
191  /* Single Pass transistor */
192  transistor_cnt += power_MTAs(transistor_size);
193 
194  /* Child MUX */
195  if (mux_node->level != 0) {
196  transistor_cnt += power_count_transistors_mux_node(
197  &mux_node->children[input_idx], transistor_size);
198  }
199  }
200  }
201 
202  return transistor_cnt;
203 }
204 
205 /**
206  * This function returns the number of transistors in an interconnect structure
207  */
209  double transistor_cnt = 0.;
210 
211  switch (interc->type) {
212  case DIRECT_INTERC:
213  /* No transistors */
214  break;
215  case MUX_INTERC:
216  case COMPLETE_INTERC:
217  /* Bus based interconnect:
218  * - Each output port requires a (num_input_ports:1) bus-based multiplexor.
219  * - The number of muxes required for bus based multiplexors is equivalent to
220  * the width of the bus (num_pins_per_port).
221  */
222  transistor_cnt += interc->interconnect_power->num_output_ports
228  break;
229  default:
230  assert(0);
231  }
232 
233  interc->interconnect_power->transistor_cnt = transistor_cnt;
234  return transistor_cnt;
235 }
236 
237 void power_sizing_init(t_arch * arch) {
238  float transistors_per_tile;
239 
240  // tech size = 2 lambda, so lambda^2/4.0 = tech^2
242  (float) 2.0);
243 
244  // Determines physical size of different PBs
245  power_size_pb();
246 
247  /* Find # of transistors in each tile type */
248  transistors_per_tile = power_transistors_per_tile(arch);
249 
250  /* Calculate CLB tile size
251  * - Assume a square tile
252  * - Assume min transistor size is Wx6L
253  * - Assume an overhead to space transistors
254  */
256  power_transistor_area(transistors_per_tile));
257 }
258 
259 /**
260  * This functions counts the number of transistors in all structures in the FPGA.
261  * It returns the number of transistors in a grid of the FPGA (logic block,
262  * switch box, 2 connection boxes)
263  */
264 static double power_transistors_per_tile(t_arch * arch) {
265  double transistor_cnt = 0.;
266 
268 
269  transistor_cnt += 2 * power_count_transistors_switchbox(arch);
270 
271  transistor_cnt += 2 * power_count_transistors_connectionbox();
272 
273  return transistor_cnt;
274 }
275 
277  return pb_node->pb_node_power->transistor_cnt_interc
280 }
281 
282 /**
283  * This function counts the number of transistors for a given physical block type
284  */
286  int mode_idx;
287  int interc;
288  int child;
289  int pb_idx;
290 
291  double tc_children_max = 0;
292  double tc_interc_max = 0;
293  boolean ignore_interc = FALSE;
294 
295  t_pb_type * pb_type = pb_node->pb_type;
296 
297  /* Check if this is a leaf node, or whether it has children */
298  if (pb_type->num_modes == 0) {
299  /* Leaf node */
300  tc_interc_max = 0;
301  tc_children_max = power_count_transistors_primitive(pb_type);
302  } else {
303  /* Find max transistor count between all modes */
304  for (mode_idx = 0; mode_idx < pb_type->num_modes; mode_idx++) {
305 
306  double tc_children = 0;
307  double tc_interc = 0;
308 
309  t_mode * mode = &pb_type->modes[mode_idx];
310 
311  if (pb_type->class_type == LUT_CLASS) {
312  /* LUTs will have a child node that is used for routing purposes
313  * For the routing algorithms it is completely connected; however,
314  * this interconnect does not exist in FPGA hardware and should
315  * be ignored for power calculations. */
316  ignore_interc = TRUE;
317  }
318 
319  /* Count Interconnect Transistors */
320  if (!ignore_interc) {
321  for (interc = 0; interc < mode->num_interconnect; interc++) {
322  tc_interc += power_count_transistors_interc(
323  &mode->interconnect[interc]);
324  }
325  }
326  tc_interc_max = max(tc_interc_max, tc_interc);
327 
328  /* Count Child PB Types */
329  for (child = 0; child < mode->num_pb_type_children; child++) {
330  t_pb_type * child_type = &mode->pb_type_children[child];
331 
332  for (pb_idx = 0; pb_idx < child_type->num_pb; pb_idx++) {
333  tc_children +=
335  &pb_node->child_pb_graph_nodes[mode_idx][child][pb_idx]);
336  }
337  }
338 
339  tc_children_max = max(tc_children_max, tc_children);
340  }
341  }
342 
343  pb_node->pb_node_power->transistor_cnt_interc = tc_interc_max;
344  pb_node->pb_node_power->transistor_cnt_pb_children = tc_children_max;
345 
346  return (tc_interc_max + tc_children_max);
347 }
348 
349 /**
350  * This function counts the maximum number of transistors in a switch box
351  */
353  double transistor_cnt = 0.;
354  double transistors_per_buf_mux = 0.;
355  int seg_idx;
356 
357  /* Buffer */
358  transistors_per_buf_mux += power_count_transistors_buffer(
361 
362  /* Multiplexor */
363  transistors_per_buf_mux += power_count_transistors_mux(
366 
367  for (seg_idx = 0; seg_idx < arch->num_segments; seg_idx++) {
368  /* In each switchbox, the different types of segments occur with relative freqencies.
369  * Thus the total number of wires of each segment type is (#tracks * freq * 2).
370  * The (x2) factor accounts for vertical and horizontal tracks.
371  * Of the wires of each segment type only (1/seglength) will have a mux&buffer.
372  */
373  float freq_frac = (float) arch->Segments[seg_idx].frequency
374  / (float) MAX_CHANNEL_WIDTH;
375 
376  transistor_cnt += transistors_per_buf_mux * 2 * freq_frac
378  * (1 / (float) arch->Segments[seg_idx].length);
379  }
380 
381  return transistor_cnt;
382 }
383 
384 /**
385  * This function calculates the number of transistors for a primitive physical block
386  */
388  double transistor_cnt;
389 
390  if (strcmp(pb_type->blif_model, ".names") == 0) {
391  /* LUT */
392  transistor_cnt = power_count_transistors_LUT(pb_type->num_input_pins,
394  } else if (strcmp(pb_type->blif_model, ".latch") == 0) {
395  /* Latch */
397  } else {
398  /* Other */
399  char msg[BUFSIZE];
400 
401  sprintf(msg, "No transistor counter function for BLIF model: %s",
402  pb_type->blif_model);
404  transistor_cnt = 0;
405  }
406 
407  return transistor_cnt;
408 }
409 
410 /**
411  * Returns the transistor count of an SRAM cell
412  */
413 static double power_count_transistor_SRAM_bit(void) {
415 }
416 
418  double transistor_cnt = 0.;
419 
420  /* Each level restorer has a P/N=1/2 inverter and a W/L=1/2 PMOS */
421 
422  /* Inverter */
423  transistor_cnt += power_MTAs(2); // NMOS
424  transistor_cnt += 1.0; // PMOS
425 
426  /* Pull-up */
427  transistor_cnt += power_MTAs_L(2.0); // Double length
428 
429  return transistor_cnt;
430 }
431 
432 /**
433  * Returns the transistor count for a LUT
434  */
435 static double power_count_transistors_LUT(int LUT_inputs,
436  float transistor_size) {
437  double transistor_cnt = 0.;
438  int level_idx;
439 
440  /* Each input driver has 1-1X and 2-2X inverters */
441  transistor_cnt += (double) LUT_inputs
443  + 2 * power_count_transistors_inv(2.0));
444 
445  /* SRAM bits */
446  transistor_cnt += power_count_transistor_SRAM_bit() * (1 << LUT_inputs);
447 
448  for (level_idx = 0; level_idx < LUT_inputs; level_idx++) {
449 
450  /* Pass transistors */
451  transistor_cnt += (1 << (LUT_inputs - level_idx))
452  * power_MTAs(transistor_size);
453 
454  /* Add level restorer after every 2 stages (level_idx %2 == 1)
455  * But if there is an odd # of stages, just put one at the last
456  * stage (level_idx == LUT_size - 1) and not at the stage just before
457  * the last stage (level_idx != LUT_size - 2)
458  */
459  if (((level_idx % 2 == 1) && (level_idx != LUT_inputs - 2))
460  || (level_idx == LUT_inputs - 1)) {
461  transistor_cnt += power_count_transistors_levr();
462  }
463  }
464 
465  return transistor_cnt;
466 }
467 
468 static double power_count_transistors_trans_gate(float size) {
469  double transistor_cnt = 0.;
470 
471  transistor_cnt += power_MTAs(size);
472  transistor_cnt += power_MTAs(size * g_power_tech->PN_ratio);
473 
474  return transistor_cnt;
475 }
476 
477 static double power_count_transistors_inv(float size) {
478  double transistor_cnt = 0.;
479 
480  /* NMOS */
481  transistor_cnt += power_MTAs(size);
482 
483  /* PMOS */
484  transistor_cnt += power_MTAs(g_power_tech->PN_ratio * size);
485 
486  return transistor_cnt;
487 }
488 
489 /**
490  * Returns the transistor count for a flip-flop
491  */
492 static double power_count_transistors_FF(float size) {
493  double transistor_cnt = 0.;
494 
495  /* 4 1X Inverters */
496  transistor_cnt += 4 * power_count_transistors_inv(size);
497 
498  /* 2 Muxes = 4 transmission gates */
499  transistor_cnt += 4 * power_count_transistors_trans_gate(size);
500 
501  return transistor_cnt;
502 }
503 
504 double power_transistor_area(double num_MTAs) {
505  return num_MTAs * g_MTA_area;
506 }
507 
508 static double power_MTAs(float W_size) {
509  return 1 + (W_size - 1) * (POWER_DRC_MIN_W / POWER_MTA_W);
510 }
511 
512 static double power_MTAs_L(float L_size) {
513  return 1 + (L_size - 1) * (POWER_DRC_MIN_L / POWER_MTA_L);
514 }
515 
516 static void power_size_pb(void) {
517  int type_idx;
518 
519  for (type_idx = 0; type_idx < num_types; type_idx++) {
520  if (type_descriptors[type_idx].pb_graph_head) {
521  power_size_pb_rec(type_descriptors[type_idx].pb_graph_head);
522  }
523  }
524 }
525 
526 static void power_size_pb_rec(t_pb_graph_node * pb_node) {
527  int port_idx, pin_idx;
528  int mode_idx, type_idx, pb_idx;
529  boolean size_buffers_and_wires = TRUE;
530 
533  && pb_node != FILL_TYPE->pb_graph_head) {
534  /* Area information is only needed for:
535  * 1. Transistor-level estimation methods
536  * 2. the FILL_TYPE for tile size calculations
537  */
538  return;
539  }
540 
541  /* Recursive call for all child pb nodes */
542  for (mode_idx = 0; mode_idx < pb_node->pb_type->num_modes; mode_idx++) {
543  t_mode * mode = &pb_node->pb_type->modes[mode_idx];
544 
545  for (type_idx = 0; type_idx < mode->num_pb_type_children; type_idx++) {
546  int num_pb = mode->pb_type_children[type_idx].num_pb;
547 
548  for (pb_idx = 0; pb_idx < num_pb; pb_idx++) {
549 
551  &pb_node->child_pb_graph_nodes[mode_idx][type_idx][pb_idx]);
552  }
553  }
554  }
555 
556  /* Determine # of transistors for this node */
558 
559  if (pb_node->pb_type->class_type == LUT_CLASS) {
560  /* LUTs will have a child node that is used for routing purposes
561  * For the routing algorithms it is completely connected; however,
562  * this interconnect does not exist in FPGA hardware and should
563  * be ignored for power calculations. */
564  size_buffers_and_wires = FALSE;
565  }
566 
569  size_buffers_and_wires = FALSE;
570  }
571 
572  /* Size all local buffers and wires */
573  if (size_buffers_and_wires) {
574  for (port_idx = 0; port_idx < pb_node->num_input_ports; port_idx++) {
575  for (pin_idx = 0; pin_idx < pb_node->num_input_pins[port_idx];
576  pin_idx++) {
578  &pb_node->input_pins[port_idx][pin_idx], TRUE);
579  }
580  }
581 
582  for (port_idx = 0; port_idx < pb_node->num_output_ports; port_idx++) {
583  for (pin_idx = 0; pin_idx < pb_node->num_output_pins[port_idx];
584  pin_idx++) {
586  &pb_node->output_pins[port_idx][pin_idx], FALSE);
587  }
588  }
589 
590  for (port_idx = 0; port_idx < pb_node->num_clock_ports; port_idx++) {
591  for (pin_idx = 0; pin_idx < pb_node->num_clock_pins[port_idx];
592  pin_idx++) {
594  &pb_node->clock_pins[port_idx][pin_idx], TRUE);
595  }
596  }
597  }
598 
599 }
600 
601 /* Provides statistics about the connection between the pin and interconnect */
603  int * fanout, float * wirelength) {
604 
605  float this_interc_sidelength;
606 
607  /* Pin to interconnect wirelength */
608  switch (interc->type) {
609  case DIRECT_INTERC:
610  *wirelength = 0;
611  *fanout = 1;
612  break;
613  case MUX_INTERC:
614 
615  case COMPLETE_INTERC:
616  /* The sidelength of this crossbar */
617  this_interc_sidelength = sqrt(
620 
621  /* Assume that inputs to the crossbar have a structure like this:
622  *
623  * A B|-----
624  * -----|---C-
625  * |-----
626  *
627  * A - wire from pin to point of fanout (grows pb interconnect area)
628  * B - fanout wire (sidelength of this crossbar)
629  * C - fanouts to crossbar muxes (grows with pb interconnect area)
630  */
631 
632  *fanout = interc->interconnect_power->num_output_ports;
633  *wirelength = this_interc_sidelength;
634  //*wirelength = ((1 + *fanout) / 2.0) * g_power_arch->local_interc_factor
635  // * pb_interc_sidelength + this_interc_sidelength;
636  break;
637  default:
638  assert(0);
639  break;
640  }
641 
642 }
643 
645  boolean pin_is_an_input) {
646  int edge_idx;
647  int list_cnt;
648  t_interconnect ** list;
649  boolean found;
650  int i;
651 
652  float C_load;
653  float this_pb_length;
654 
655  int fanout;
656  float wirelength_out = 0;
657  float wirelength_in = 0;
658 
659  int fanout_tmp;
660  float wirelength_tmp;
661 
662  float this_pb_interc_sidelength = 0;
663  float parent_pb_interc_sidelength = 0;
664  boolean top_level_pb;
665 
666  t_pb_type * this_pb_type = pin->parent_node->pb_type;
667 
668  /*
669  if (strcmp(pin->parent_node->pb_type->name, "clb") == 0) {
670  //printf("here\n");
671  }*/
672 
673  this_pb_interc_sidelength = sqrt(
676  if (pin->parent_node->parent_pb_graph_node == NULL) {
677  top_level_pb = TRUE;
678  parent_pb_interc_sidelength = 0.;
679  } else {
680  top_level_pb = FALSE;
681  parent_pb_interc_sidelength =
682  sqrt(
685  }
686 
687  /* Pins are connected to a wire that is connected to:
688  * 1. Interconnect structures belonging its pb_node, and/or
689  * - The pb_node may have one or more modes, each with a set of
690  * interconnect. The capacitance is the worst-case capacitance
691  * between the different modes.
692  *
693  * 2. Interconnect structures belonging to its parent pb_node
694  */
695 
696  /* We want to estimate the physical pin fan-out, unfortunately it is not defined in the architecture file.
697  * Instead, we know the modes of operation, and the fanout may differ depending on the mode. We assume
698  * that the physical fanout is the max of the connections to the various modes (although in reality it could
699  * be higher)*/
700 
701  /* Loop through all edges, building a list of interconnect that this pin drives */
702  list = NULL;
703  list_cnt = 0;
704  for (edge_idx = 0; edge_idx < pin->num_output_edges; edge_idx++) {
705  /* Check if its already in the list */
706  found = FALSE;
707  for (i = 0; i < list_cnt; i++) {
708  if (list[i] == pin->output_edges[edge_idx]->interconnect) {
709  found = TRUE;
710  break;
711  }
712  }
713 
714  if (!found) {
715  list_cnt++;
716  list = (t_interconnect**) my_realloc(list,
717  list_cnt * sizeof(t_interconnect*));
718  list[list_cnt - 1] = pin->output_edges[edge_idx]->interconnect;
719  }
720  }
721 
722  /* Determine the:
723  * 1. Wirelength connected to the pin
724  * 2. Fanout of the pin
725  */
726  if (pin_is_an_input) {
727  /* Pin is an input to the PB.
728  * Thus, all interconnect it drives belong to the modes of the PB.
729  */
730  int * fanout_per_mode;
731  float * wirelength_out_per_mode;
732 
733  fanout_per_mode = (int*) my_calloc(this_pb_type->num_modes,
734  sizeof(int));
735  wirelength_out_per_mode = (float *) my_calloc(this_pb_type->num_modes,
736  sizeof(float));
737 
738  for (i = 0; i < list_cnt; i++) {
739  int mode_idx = list[i]->parent_mode_index;
740 
741  power_size_pin_to_interconnect(list[i], &fanout_tmp,
742  &wirelength_tmp);
743 
744  fanout_per_mode[mode_idx] += fanout_tmp;
745  wirelength_out_per_mode[mode_idx] += wirelength_tmp;
746  }
747 
748  fanout = 0;
749  wirelength_out = 0.;
750 
751  /* Find worst-case between modes*/
752  for (i = 0; i < this_pb_type->num_modes; i++) {
753  fanout = max(fanout, fanout_per_mode[i]);
754  wirelength_out = max(wirelength_out, wirelength_out_per_mode[i]);
755  }
756  if (wirelength_out != 0) {
757  wirelength_out += g_power_arch->local_interc_factor
758  * this_pb_interc_sidelength;
759  }
760 
761  free(fanout_per_mode);
762  free(wirelength_out_per_mode);
763 
764  /* Input wirelength - from parent PB */
765  if (!top_level_pb) {
766  wirelength_in = g_power_arch->local_interc_factor
767  * parent_pb_interc_sidelength;
768  }
769 
770  } else {
771  /* Pin is an output of the PB.
772  * Thus, all interconnect it drives belong to the parent PB.
773  */
774  fanout = 0;
775  wirelength_out = 0.;
776 
777  if (top_level_pb) {
778  /* Outputs of top-level pb should not drive interconnect */
779  assert(list_cnt == 0);
780  }
781 
782  /* Loop through all interconnect that this pin drives */
783 
784  for (i = 0; i < list_cnt; i++) {
785  power_size_pin_to_interconnect(list[i], &fanout_tmp,
786  &wirelength_tmp);
787  fanout += fanout_tmp;
788  wirelength_out += wirelength_tmp;
789  }
790  if (wirelength_out != 0) {
791  wirelength_out += g_power_arch->local_interc_factor
792  * parent_pb_interc_sidelength;
793  }
794 
795  /* Input wirelength - from this PB */
796  wirelength_in = g_power_arch->local_interc_factor
797  * this_pb_interc_sidelength;
798 
799  }
800  free(list);
801 
802  /* Wirelength */
803  switch (pin->port->port_power->wire_type) {
805  /* User is ignoring this wirelength */
806  pin->pin_power->C_wire = 0.;
807  break;
808  case POWER_WIRE_TYPE_C:
809  pin->pin_power->C_wire = pin->port->port_power->wire.C;
810  break;
814  break;
816  this_pb_length = sqrt(
820  * this_pb_length * g_power_arch->C_wire_local;
821  break;
822 
825  * (wirelength_in + wirelength_out);
826  break;
828  default:
829  assert(0);
830  break;
831  }
832 
833  /* Buffer */
834  switch (pin->port->port_power->buffer_type) {
836  /* User assumes no buffer */
837  pin->pin_power->buffer_size = 0.;
838  break;
841  break;
843  /* Asume the buffer drives the wire & fanout muxes */
844  C_load = pin->pin_power->C_wire
845  + (fanout) * g_power_commonly_used->INV_1X_C_in; //g_power_commonly_used->NMOS_1X_C_d;
846  if (C_load > g_power_commonly_used->INV_1X_C_in) {
848  C_load);
849  } else {
850  pin->pin_power->buffer_size = 0.;
851  }
852  break;
854  default:
855  assert(0);
856  }
857 
860 }
#define POWER_MTA_L
Definition: power_sizing.h:39
t_type_ptr FILL_TYPE
Definition: globals.c:42
t_interconnect * interconnect
t_pb_graph_pin ** clock_pins
t_power_tech * g_power_tech
Definition: power.c:67
static double g_MTA_area
Definition: power_sizing.c:34
enum e_pb_type_class class_type
t_power_arch * g_power_arch
Definition: power.c:68
t_port_power * port_power
struct s_pb_type * pb_type_children
union s_port_power::@5 wire
#define POWER_DRC_MIN_L
Definition: power_sizing.h:32
struct s_pb_graph_node * parent_pb_graph_node
e_power_estimation_method estimation_method
static double power_count_transistors_mux_node(t_mux_node *mux_node, float transistor_size)
Definition: power_sizing.c:184
t_mode * modes
static void power_size_pb_rec(t_pb_graph_node *pb_node)
Definition: power_sizing.c:526
float logical_effort_factor
float power_buffer_size_from_logical_effort(float C_load)
Definition: power_util.c:469
int num_interconnect
struct s_pb_graph_edge ** output_edges
float tech_size
Definition: power.h:134
t_power_commonly_used * g_power_commonly_used
Definition: power.c:66
static double power_transistors_per_tile(t_arch *arch)
Definition: power_sizing.c:264
t_pb_graph_node_power * pb_node_power
void * my_calloc(size_t nelem, size_t size)
Definition: util.c:132
t_pb_type_power * pb_type_power
int power_calc_buffer_num_stages(float final_stage_size, float desired_stage_effort)
Definition: power_util.c:179
static double power_MTAs(float size)
Definition: power_sizing.c:508
float PN_ratio
Definition: power.h:131
void power_sizing_init(t_arch *arch)
Definition: power_sizing.c:237
double power_transistor_area(double num_MTAs)
Definition: power_sizing.c:504
char * blif_model
t_pb_graph_pin ** output_pins
#define BUFSIZE
Definition: graphics.c:184
float transistors_per_SRAM_bit
t_interconnect * interconnect
Definition: util.h:12
int channel_width
Definition: power.h:84
float relative_length
t_solution_inf g_solution_inf
Definition: power.c:64
float local_interc_factor
int max_routing_mux_size
Definition: power.h:248
t_mux_arch * power_get_mux_arch(int num_mux_inputs, float transistor_size)
Definition: power_util.c:490
int max_seg_to_IPIN_fanout
Definition: power.h:251
boolean power_method_is_transistor_level(e_power_estimation_method estimation_method)
Definition: power_util.c:576
static double power_count_transistors_mux(t_mux_arch *mux_arch)
Definition: power_sizing.c:124
double power_count_transistors_buffer(float buffer_size)
Definition: power_sizing.c:100
int level
Definition: power.h:295
#define MAX_CHANNEL_WIDTH
Definition: arch_types.h:25
#define max(a, b)
Definition: graphics.c:171
static double power_count_transistors_FF(float size)
Definition: power_sizing.c:492
struct s_pb_graph_node * parent_node
static double power_count_transistors_pb_node(t_pb_graph_node *pb_node)
Definition: power_sizing.c:285
enum e_interconnect type
t_segment_inf * Segments
float transistor_size
Definition: power.h:282
struct s_pb_graph_node *** child_pb_graph_nodes
int num_pb_type_children
static double power_count_transistors_switchbox(t_arch *arch)
Definition: power_sizing.c:352
static double power_count_transistors_levr()
Definition: power_sizing.c:417
float absolute_length
int levels
Definition: power.h:280
float LUT_transistor_size
struct s_pb_type * pb_type
static void power_size_pin_to_interconnect(t_interconnect *interc, int *fanout, float *wirelength)
Definition: power_sizing.c:602
static double power_count_transistor_SRAM_bit(void)
Definition: power_sizing.c:413
static void power_size_pin_buffers_and_wires(t_pb_graph_pin *pin, boolean pin_is_an_input)
Definition: power_sizing.c:644
static void power_size_pb(void)
Definition: power_sizing.c:516
int num_types
Definition: globals.c:37
static void * my_realloc(void *memblk, int ibytes)
Definition: graphics.c:512
e_power_buffer_type buffer_type
static double power_count_transistors_interc(t_interconnect *interc)
Definition: power_sizing.c:208
static double power_transistors_for_pb_node(t_pb_graph_node *pb_node)
Definition: power_sizing.c:276
static double power_count_transistors_LUT(int LUT_inputs, float transistor_size)
Definition: power_sizing.c:435
int num_inputs
Definition: power.h:292
#define POWER_MTA_W
Definition: power_sizing.h:38
int num_segments
t_pb_graph_node * pb_graph_head
struct s_type_descriptor * type_descriptors
Definition: globals.c:38
e_power_wire_type wire_type
static double power_count_transistors_inv(float size)
Definition: power_sizing.c:477
t_mux_node * mux_graph_head
Definition: power.h:284
#define POWER_DRC_MIN_W
Definition: power_sizing.h:33
float mux_transistor_size
int num_input_pins
static void power_mux_node_max_inputs(t_mux_node *mux_node, float *max_inputs)
Definition: power_sizing.c:165
t_interconnect_power * interconnect_power
static double power_MTAs_L(float L_size)
Definition: power_sizing.c:512
static double power_count_transistors_trans_gate(float size)
Definition: power_sizing.c:468
t_pb_graph_pin_power * pin_power
static double power_count_transistors_primitive(t_pb_type *pb_type)
Definition: power_sizing.c:387
t_pb_graph_pin ** input_pins
float calc_buffer_stage_effort(int N, float final_stage_size)
Definition: power_util.c:204
t_mux_node * children
Definition: power.h:293
Definition: util.h:12
void power_log_msg(e_power_log_type log_type, char *msg)
Definition: power_util.c:67
static double power_count_transistors_connectionbox(void)
Definition: power_sizing.c:70