abc-master
 All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Friends Macros
fpgaCutUtils.c
Go to the documentation of this file.
1 /**CFile****************************************************************
2 
3  FileName [fpgaCutUtils.c]
4 
5  PackageName [MVSIS 1.3: Multi-valued logic synthesis system.]
6 
7  Synopsis [Generic technology mapping engine.]
8 
9  Author [MVSIS Group]
10 
11  Affiliation [UC Berkeley]
12 
13  Date [Ver. 2.0. Started - August 18, 2004.]
14 
15  Revision [$Id: fpgaCutUtils.h,v 1.0 2003/09/08 00:00:00 alanmi Exp $]
16 
17 ***********************************************************************/
18 
19 #include "fpgaInt.h"
20 
22 
23 
24 ////////////////////////////////////////////////////////////////////////
25 /// DECLARATIONS ///
26 ////////////////////////////////////////////////////////////////////////
27 
28 ////////////////////////////////////////////////////////////////////////
29 /// FUNCTION DEFINITIONS ///
30 ////////////////////////////////////////////////////////////////////////
31 
32 /**Function*************************************************************
33 
34  Synopsis [Allocates the cut.]
35 
36  Description []
37 
38  SideEffects []
39 
40  SeeAlso []
41 
42 ***********************************************************************/
44 {
45  Fpga_Cut_t * pCut;
47  memset( pCut, 0, sizeof(Fpga_Cut_t) );
48  return pCut;
49 }
50 
51 /**Function*************************************************************
52 
53  Synopsis [Duplicates the cut.]
54 
55  Description []
56 
57  SideEffects []
58 
59  SeeAlso []
60 
61 ***********************************************************************/
63 {
64  Fpga_Cut_t * pCutNew;
65  int i;
66  pCutNew = Fpga_CutAlloc( p );
67  pCutNew->pRoot = pCutOld->pRoot;
68  pCutNew->nLeaves = pCutOld->nLeaves;
69  for ( i = 0; i < pCutOld->nLeaves; i++ )
70  pCutNew->ppLeaves[i] = pCutOld->ppLeaves[i];
71  return pCutNew;
72 }
73 
74 /**Function*************************************************************
75 
76  Synopsis [Deallocates the cut.]
77 
78  Description []
79 
80  SideEffects []
81 
82  SeeAlso []
83 
84 ***********************************************************************/
86 {
87  if ( pCut )
88  Extra_MmFixedEntryRecycle( p->mmCuts, (char *)pCut );
89 }
90 
91 /**Function*************************************************************
92 
93  Synopsis []
94 
95  Description []
96 
97  SideEffects []
98 
99  SeeAlso []
100 
101 ***********************************************************************/
102 void Fpga_CutPrint( Fpga_Man_t * p, Fpga_Node_t * pRoot, Fpga_Cut_t * pCut )
103 {
104  int i;
105  printf( "CUT: Delay = %4.2f. Area = %4.2f. Nodes = %d -> {",
106  pCut->tArrival, pCut->aFlow, pRoot->Num );
107  for ( i = 0; i < pCut->nLeaves; i++ )
108  printf( " %d", pCut->ppLeaves[i]->Num );
109  printf( " } \n" );
110 }
111 
112 /**Function*************************************************************
113 
114  Synopsis []
115 
116  Description []
117 
118  SideEffects []
119 
120  SeeAlso []
121 
122 ***********************************************************************/
124 {
125  Fpga_Cut_t * pCut;
126  pCut = Fpga_CutAlloc( p );
127  pCut->pRoot = pNode;
128  pCut->nLeaves = 1;
129  pCut->ppLeaves[0] = pNode;
130  pCut->uSign = FPGA_SEQ_SIGN(pCut->ppLeaves[0]);
131  return pCut;
132 }
133 
134 
135 /**function*************************************************************
136 
137  synopsis [Computes the exact area associated with the cut.]
138 
139  description []
140 
141  sideeffects []
142 
143  seealso []
144 
145 ***********************************************************************/
147 {
148  return p->pLutLib->pLutAreas[(int)pCut->nLeaves];
149 }
150 
151 /**Function*************************************************************
152 
153  Synopsis []
154 
155  Description []
156 
157  SideEffects []
158 
159  SeeAlso []
160 
161 ***********************************************************************/
163 {
164  Fpga_Cut_t * pPrev = NULL; // Suppress "might be used uninitialized"
165  Fpga_Cut_t * pTemp;
166  if ( pSetAll == NULL )
167  return pSets;
168  if ( pSets == NULL )
169  return pSetAll;
170  // find the last one
171  for ( pTemp = pSets; pTemp; pTemp = pTemp->pNext )
172  pPrev = pTemp;
173  // append all the end of the current set
174  assert( pPrev->pNext == NULL );
175  pPrev->pNext = pSetAll;
176  return pSets;
177 }
178 
179 /**Function*************************************************************
180 
181  Synopsis []
182 
183  Description []
184 
185  SideEffects []
186 
187  SeeAlso []
188 
189 ***********************************************************************/
190 void Fpga_CutListRecycle( Fpga_Man_t * p, Fpga_Cut_t * pSetList, Fpga_Cut_t * pSave )
191 {
192  Fpga_Cut_t * pNext, * pTemp;
193  for ( pTemp = pSetList, pNext = pTemp? pTemp->pNext : NULL;
194  pTemp;
195  pTemp = pNext, pNext = pNext? pNext->pNext : NULL )
196  if ( pTemp != pSave )
197  Extra_MmFixedEntryRecycle( p->mmCuts, (char *)pTemp );
198 }
199 
200 /**Function*************************************************************
201 
202  Synopsis []
203 
204  Description []
205 
206  SideEffects []
207 
208  SeeAlso []
209 
210 ***********************************************************************/
212 {
213  Fpga_Cut_t * pTemp;
214  int i;
215  for ( i = 0, pTemp = pSets; pTemp; pTemp = pTemp->pNext, i++ );
216  return i;
217 }
218 
219 #if 0
220 
221 /**function*************************************************************
222 
223  synopsis [Removes the fanouts of the cut.]
224 
225  description []
226 
227  sideeffects []
228 
229  seealso []
230 
231 ***********************************************************************/
232 void Fpga_CutRemoveFanouts( Fpga_Man_t * p, Fpga_Node_t * pNode, Fpga_Cut_t * pCut )
233 {
234  Fpga_NodeVec_t * vFanouts;
235  int i, k;
236  for ( i = 0; i < pCut->nLeaves; i++ )
237  {
238  vFanouts = pCut->ppLeaves[i]->vFanouts;
239  for ( k = 0; k < vFanouts->nSize; k++ )
240  if ( vFanouts->pArray[k] == pNode )
241  break;
242  assert( k != vFanouts->nSize );
243  for ( k++; k < vFanouts->nSize; k++ )
244  vFanouts->pArray[k-1] = vFanouts->pArray[k];
245  vFanouts->nSize--;
246  }
247 }
248 
249 /**function*************************************************************
250 
251  synopsis [Removes the fanouts of the cut.]
252 
253  description []
254 
255  sideeffects []
256 
257  seealso []
258 
259 ***********************************************************************/
260 void Fpga_CutInsertFanouts( Fpga_Man_t * p, Fpga_Node_t * pNode, Fpga_Cut_t * pCut )
261 {
262  int i;
263  for ( i = 0; i < pCut->nLeaves; i++ )
264  Fpga_NodeVecPush( pCut->ppLeaves[i]->vFanouts, pNode );
265 }
266 #endif
267 
268 /**Function*************************************************************
269 
270  Synopsis [Computes the arrival time and the area flow of the cut.]
271 
272  Description []
273 
274  SideEffects []
275 
276  SeeAlso []
277 
278 ***********************************************************************/
280 {
281  Fpga_Cut_t * pFaninCut;
282  int i;
283  pCut->tArrival = -FPGA_FLOAT_LARGE;
284  pCut->aFlow = pMan->pLutLib->pLutAreas[(int)pCut->nLeaves];
285  for ( i = 0; i < pCut->nLeaves; i++ )
286  {
287  pFaninCut = pCut->ppLeaves[i]->pCutBest;
288  if ( pCut->tArrival < pFaninCut->tArrival )
289  pCut->tArrival = pFaninCut->tArrival;
290  // if the fanout count is not set, assume it to be 1
291  if ( pCut->ppLeaves[i]->nRefs == 0 )
292  pCut->aFlow += pFaninCut->aFlow;
293  else
294 // pCut->aFlow += pFaninCut->aFlow / pCut->ppLeaves[i]->nRefs;
295  pCut->aFlow += pFaninCut->aFlow / pCut->ppLeaves[i]->aEstFanouts;
296  }
297  // use the first pin to compute the delay of the LUT
298  // (this mapper does not support the variable pin delay model)
299  pCut->tArrival += pMan->pLutLib->pLutDelays[(int)pCut->nLeaves][0];
300 }
301 
302 
303 /**function*************************************************************
304 
305  synopsis [Computes the area flow of the cut.]
306 
307  description []
308 
309  sideeffects []
310 
311  seealso []
312 
313 ***********************************************************************/
315 {
316  Fpga_Cut_t * pCutFanin;
317  int i;
318  pCut->aFlow = pMan->pLutLib->pLutAreas[(int)pCut->nLeaves];
319  for ( i = 0; i < pCut->nLeaves; i++ )
320  {
321  // get the cut implementing this phase of the fanin
322  pCutFanin = pCut->ppLeaves[i]->pCutBest;
323  assert( pCutFanin );
324  pCut->aFlow += pCutFanin->aFlow / pCut->ppLeaves[i]->nRefs;
325  }
326  return pCut->aFlow;
327 }
328 
329 /**function*************************************************************
330 
331  synopsis [Computes the exact area associated with the cut.]
332 
333  description []
334 
335  sideeffects []
336 
337  seealso []
338 
339 ***********************************************************************/
341 {
342  float aResult, aResult2;
343  if ( pCut->nLeaves == 1 )
344  return 0;
345  aResult = Fpga_CutDeref( pMan, NULL, pCut, 0 );
346  aResult2 = Fpga_CutRef( pMan, NULL, pCut, 0 );
347  assert( Fpga_FloatEqual( pMan, aResult, aResult2 ) );
348  return aResult;
349 }
350 
351 /**function*************************************************************
352 
353  synopsis [Computes the exact area associated with the cut.]
354 
355  description []
356 
357  sideeffects []
358 
359  seealso []
360 
361 ***********************************************************************/
363 {
364  float aResult, aResult2;
365  if ( pCut->nLeaves == 1 )
366  return 0;
367  aResult2 = Fpga_CutRef( pMan, NULL, pCut, 0 );
368  aResult = Fpga_CutDeref( pMan, NULL, pCut, 0 );
369  assert( Fpga_FloatEqual( pMan, aResult, aResult2 ) );
370  return aResult;
371 }
372 
373 /**function*************************************************************
374 
375  synopsis [References the cut.]
376 
377  description [This procedure is similar to the procedure NodeReclaim.]
378 
379  sideeffects []
380 
381  seealso []
382 
383 ***********************************************************************/
384 float Fpga_CutRef( Fpga_Man_t * pMan, Fpga_Node_t * pNode, Fpga_Cut_t * pCut, int fFanouts )
385 {
386  Fpga_Node_t * pNodeChild;
387  float aArea;
388  int i;
389 
390  // deref the fanouts
391 // if ( fFanouts )
392 // Fpga_CutInsertFanouts( pMan, pNode, pCut );
393 
394  // start the area of this cut
395  aArea = pMan->pLutLib->pLutAreas[(int)pCut->nLeaves];
396  // go through the children
397  for ( i = 0; i < pCut->nLeaves; i++ )
398  {
399  pNodeChild = pCut->ppLeaves[i];
400  assert( pNodeChild->nRefs >= 0 );
401  if ( pNodeChild->nRefs++ > 0 )
402  continue;
403  if ( !Fpga_NodeIsAnd(pNodeChild) )
404  continue;
405  aArea += Fpga_CutRef( pMan, pNodeChild, pNodeChild->pCutBest, fFanouts );
406  }
407  return aArea;
408 }
409 
410 /**function*************************************************************
411 
412  synopsis [Dereferences the cut.]
413 
414  description [This procedure is similar to the procedure NodeRecusiveDeref.]
415 
416  sideeffects []
417 
418  seealso []
419 
420 ***********************************************************************/
421 float Fpga_CutDeref( Fpga_Man_t * pMan, Fpga_Node_t * pNode, Fpga_Cut_t * pCut, int fFanouts )
422 {
423  Fpga_Node_t * pNodeChild;
424  float aArea;
425  int i;
426 
427  // deref the fanouts
428 // if ( fFanouts )
429 // Fpga_CutRemoveFanouts( pMan, pNode, pCut );
430 
431  // start the area of this cut
432  aArea = pMan->pLutLib->pLutAreas[(int)pCut->nLeaves];
433  // go through the children
434  for ( i = 0; i < pCut->nLeaves; i++ )
435  {
436  pNodeChild = pCut->ppLeaves[i];
437  assert( pNodeChild->nRefs > 0 );
438  if ( --pNodeChild->nRefs > 0 )
439  continue;
440  if ( !Fpga_NodeIsAnd(pNodeChild) )
441  continue;
442  aArea += Fpga_CutDeref( pMan, pNodeChild, pNodeChild->pCutBest, fFanouts );
443  }
444  return aArea;
445 }
446 
447 
448 /**Function*************************************************************
449 
450  Synopsis [Sets the used cuts to be the currently selected ones.]
451 
452  Description []
453 
454  SideEffects []
455 
456  SeeAlso []
457 
458 ***********************************************************************/
460 {
461  int i;
462  for ( i = 0; i < pMan->vNodesAll->nSize; i++ )
463  if ( pMan->vNodesAll->pArray[i]->pCutOld )
464  {
465  pMan->vNodesAll->pArray[i]->pCutBest = pMan->vNodesAll->pArray[i]->pCutOld;
466  pMan->vNodesAll->pArray[i]->pCutOld = NULL;
467  }
468 }
469 
470 ////////////////////////////////////////////////////////////////////////
471 /// END OF FILE ///
472 ////////////////////////////////////////////////////////////////////////
473 
474 
476 
char * memset()
#define FPGA_SEQ_SIGN(p)
Definition: fpgaInt.h:70
float Fpga_CutRef(Fpga_Man_t *pMan, Fpga_Node_t *pNode, Fpga_Cut_t *pCut, int fFanouts)
Definition: fpgaCutUtils.c:384
void Fpga_CutInsertFanouts(Fpga_Man_t *p, Fpga_Node_t *pNode, Fpga_Cut_t *pCut)
void Fpga_CutFree(Fpga_Man_t *p, Fpga_Cut_t *pCut)
Definition: fpgaCutUtils.c:85
static Llb_Mgr_t * p
Definition: llb3Image.c:950
float pLutDelays[FPGA_MAX_LUTSIZE+1][FPGA_MAX_LUTSIZE+1]
Definition: fpgaInt.h:176
Fpga_Cut_t * Fpga_CutListAppend(Fpga_Cut_t *pSetAll, Fpga_Cut_t *pSets)
Definition: fpgaCutUtils.c:162
void Fpga_CutGetParameters(Fpga_Man_t *pMan, Fpga_Cut_t *pCut)
Definition: fpgaCutUtils.c:279
float Fpga_CutGetAreaRefed(Fpga_Man_t *pMan, Fpga_Cut_t *pCut)
Definition: fpgaCutUtils.c:340
void Fpga_CutPrint(Fpga_Man_t *p, Fpga_Node_t *pRoot, Fpga_Cut_t *pCut)
Definition: fpgaCutUtils.c:102
#define FPGA_FLOAT_LARGE
Definition: fpgaInt.h:65
void Fpga_MappingSetUsedCuts(Fpga_Man_t *pMan)
Definition: fpgaCutUtils.c:459
Fpga_Cut_t * Fpga_CutDup(Fpga_Man_t *p, Fpga_Cut_t *pCutOld)
Definition: fpgaCutUtils.c:62
float pLutAreas[FPGA_MAX_LUTSIZE+1]
Definition: fpgaInt.h:175
static int Fpga_FloatEqual(Fpga_Man_t *p, float Arg1, float Arg2)
Definition: fpgaInt.h:283
void Fpga_CutRemoveFanouts(Fpga_Man_t *p, Fpga_Node_t *pNode, Fpga_Cut_t *pCut)
for(p=first;p->value< newval;p=p->next)
char * Extra_MmFixedEntryFetch(Extra_MmFixed_t *p)
Fpga_Node_t * ppLeaves[FPGA_MAX_LEAVES+1]
Definition: fpgaInt.h:237
Fpga_Cut_t * pCutOld
Definition: fpgaInt.h:223
Fpga_NodeVec_t * vNodesAll
Definition: fpgaInt.h:111
float Fpga_CutGetRootArea(Fpga_Man_t *p, Fpga_Cut_t *pCut)
Definition: fpgaCutUtils.c:146
unsigned uSign
Definition: fpgaInt.h:239
ABC_NAMESPACE_IMPL_START Fpga_Cut_t * Fpga_CutAlloc(Fpga_Man_t *p)
DECLARATIONS ///.
Definition: fpgaCutUtils.c:43
#define ABC_NAMESPACE_IMPL_END
Definition: abc_global.h:108
float Fpga_CutGetAreaDerefed(Fpga_Man_t *pMan, Fpga_Cut_t *pCut)
Definition: fpgaCutUtils.c:362
#define ABC_NAMESPACE_IMPL_START
Definition: abc_global.h:107
float Fpga_CutGetAreaFlow(Fpga_Man_t *pMan, Fpga_Cut_t *pCut)
Definition: fpgaCutUtils.c:314
int Fpga_NodeIsAnd(Fpga_Node_t *p)
Definition: fpgaCreate.c:127
int Fpga_CutListCount(Fpga_Cut_t *pSets)
Definition: fpgaCutUtils.c:211
Extra_MmFixed_t * mmCuts
Definition: fpgaInt.h:141
STRUCTURE DEFINITIONS ///.
Definition: fpgaInt.h:99
float Fpga_CutDeref(Fpga_Man_t *pMan, Fpga_Node_t *pNode, Fpga_Cut_t *pCut, int fFanouts)
Definition: fpgaCutUtils.c:421
Fpga_Node_t * pRoot
Definition: fpgaInt.h:236
#define assert(ex)
Definition: util_old.h:213
Fpga_LutLib_t * pLutLib
Definition: fpgaInt.h:137
void Extra_MmFixedEntryRecycle(Extra_MmFixed_t *p, char *pEntry)
Fpga_Node_t ** pArray
Definition: fpgaInt.h:252
Fpga_Cut_t * pCutBest
Definition: fpgaInt.h:222
Fpga_Cut_t * pNext
Definition: fpgaInt.h:246
Fpga_Cut_t * Fpga_CutCreateSimple(Fpga_Man_t *p, Fpga_Node_t *pNode)
Definition: fpgaCutUtils.c:123
void Fpga_NodeVecPush(Fpga_NodeVec_t *p, Fpga_Node_t *Entry)
Definition: fpgaVec.c:169
void Fpga_CutListRecycle(Fpga_Man_t *p, Fpga_Cut_t *pSetList, Fpga_Cut_t *pSave)
Definition: fpgaCutUtils.c:190