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ioReadVerilog.c File Reference
#include "ioAbc.h"
#include "base/ver/ver.h"

Go to the source code of this file.

Functions

ABC_NAMESPACE_IMPL_START
Abc_Ntk_t
Io_ReadVerilog (char *pFileName, int fCheck)
 DECLARATIONS ///. More...
 

Function Documentation

ABC_NAMESPACE_IMPL_START Abc_Ntk_t* Io_ReadVerilog ( char *  pFileName,
int  fCheck 
)

DECLARATIONS ///.

CFile****************************************************************

FileName [ioReadVerilog.c]

SystemName [ABC: Logic synthesis and verification system.]

PackageName [Command processing package.]

Synopsis [Procedure to read network from file.]

Author [Alan Mishchenko]

Affiliation [UC Berkeley]

Date [Ver. 1.0. Started - June 20, 2005.]

Revision [

Id:
ioReadVerilog.c,v 1.00 2005/06/20 00:00:00 alanmi Exp

]FUNCTION DEFINITIONS /// Function*************************************************************

Synopsis [Reads hierarchical design from the Verilog file.]

Description []

SideEffects []

SeeAlso []

Definition at line 48 of file ioReadVerilog.c.

49 {
50  Abc_Ntk_t * pNtk, * pTemp;
51  Abc_Des_t * pDesign;
52  int i, RetValue;
53 
54  // parse the verilog file
55  pDesign = Ver_ParseFile( pFileName, NULL, fCheck, 1 );
56  if ( pDesign == NULL )
57  return NULL;
58 
59  // detect top-level model
60  RetValue = Abc_DesFindTopLevelModels( pDesign );
61  pNtk = (Abc_Ntk_t *)Vec_PtrEntry( pDesign->vTops, 0 );
62  if ( RetValue > 1 )
63  {
64  printf( "Warning: The design has %d root-level modules: ", Vec_PtrSize(pDesign->vTops) );
65  Vec_PtrForEachEntry( Abc_Ntk_t *, pDesign->vTops, pTemp, i )
66  printf( " %s", Abc_NtkName(pTemp) );
67  printf( "\n" );
68  printf( "The first one (%s) will be used.\n", pNtk->pName );
69  }
70 
71  // extract the master network
72  pNtk->pDesign = pDesign;
73  pDesign->pManFunc = NULL;
74 
75  // verify the design for cyclic dependence
76  assert( Vec_PtrSize(pDesign->vModules) > 0 );
77  if ( Vec_PtrSize(pDesign->vModules) == 1 )
78  {
79 // printf( "Warning: The design is not hierarchical.\n" );
80  Abc_DesFree( pDesign, pNtk );
81  pNtk->pDesign = NULL;
82  pNtk->pSpec = Extra_UtilStrsav( pFileName );
83  }
84  else
85  {
86  // check that there is no cyclic dependency
88  }
89 
90 //Io_WriteVerilog( pNtk, "_temp.v" );
91 // Abc_NtkPrintBoxInfo( pNtk );
92  return pNtk;
93 }
static int Vec_PtrSize(Vec_Ptr_t *p)
Definition: vecPtr.h:295
ABC_DLL int Abc_DesFindTopLevelModels(Abc_Des_t *p)
Definition: abcLib.c:293
char * Extra_UtilStrsav(const char *s)
ABC_DLL void Abc_DesFree(Abc_Des_t *p, Abc_Ntk_t *pNtk)
Definition: abcLib.c:94
static DdNode * one
Definition: cuddDecomp.c:112
ABC_DLL int Abc_NtkIsAcyclicHierarchy(Abc_Ntk_t *pNtk)
Definition: abcCheck.c:809
if(last==0)
Definition: sparse_int.h:34
Vec_Ptr_t * vTops
Definition: abc.h:222
static void * Vec_PtrEntry(Vec_Ptr_t *p, int i)
Definition: vecPtr.h:362
char * pSpec
Definition: abc.h:159
static char * Abc_NtkName(Abc_Ntk_t *pNtk)
Definition: abc.h:270
#define assert(ex)
Definition: util_old.h:213
#define Vec_PtrForEachEntry(Type, vVec, pEntry, i)
MACRO DEFINITIONS ///.
Definition: vecPtr.h:55
Abc_Des_t * pDesign
Definition: abc.h:180
Abc_Des_t * Ver_ParseFile(char *pFileName, Abc_Des_t *pGateLib, int fCheck, int fUseMemMan)
MACRO DEFINITIONS ///.
Definition: verCore.c:165