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fpgaSwitch.c
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1 /**CFile****************************************************************
2 
3  FileName [fpgaSwitch.c]
4 
5  PackageName [MVSIS 1.3: Multi-valued logic synthesis system.]
6 
7  Synopsis [Generic technology mapping engine.]
8 
9  Author [MVSIS Group]
10 
11  Affiliation [UC Berkeley]
12 
13  Date [Ver. 1.0. Started - September 8, 2003.]
14 
15  Revision [$Id: fpgaSwitch.h,v 1.0 2003/09/08 00:00:00 alanmi Exp $]
16 
17 ***********************************************************************/
18 
19 #include "fpgaInt.h"
20 
22 
23 
24 ////////////////////////////////////////////////////////////////////////
25 /// DECLARATIONS ///
26 ////////////////////////////////////////////////////////////////////////
27 
28 ////////////////////////////////////////////////////////////////////////
29 /// FUNCTION DEFINITIONS ///
30 ////////////////////////////////////////////////////////////////////////
31 
32 /**function*************************************************************
33 
34  synopsis [Computes the exact area associated with the cut.]
35 
36  description []
37 
38  sideeffects []
39 
40  seealso []
41 
42 ***********************************************************************/
44 {
45  float aResult, aResult2;
46  aResult2 = Fpga_CutRefSwitch( pMan, pNode, pCut, 0 );
47  aResult = Fpga_CutDerefSwitch( pMan, pNode, pCut, 0 );
48 // assert( aResult == aResult2 );
49  return aResult;
50 }
51 
52 /**function*************************************************************
53 
54  synopsis [References the cut.]
55 
56  description [This procedure is similar to the procedure NodeReclaim.]
57 
58  sideeffects []
59 
60  seealso []
61 
62 ***********************************************************************/
63 float Fpga_CutRefSwitch( Fpga_Man_t * pMan, Fpga_Node_t * pNode, Fpga_Cut_t * pCut, int fFanouts )
64 {
65  Fpga_Node_t * pNodeChild;
66  float aArea;
67  int i;
68  // start the area of this cut
69  aArea = pNode->Switching;
70  if ( pCut->nLeaves == 1 )
71  return aArea;
72  // go through the children
73  for ( i = 0; i < pCut->nLeaves; i++ )
74  {
75  pNodeChild = pCut->ppLeaves[i];
76  assert( pNodeChild->nRefs >= 0 );
77  if ( pNodeChild->nRefs++ > 0 )
78  continue;
79  aArea += Fpga_CutRefSwitch( pMan, pNodeChild, pNodeChild->pCutBest, fFanouts );
80  }
81  return aArea;
82 }
83 
84 /**function*************************************************************
85 
86  synopsis [Dereferences the cut.]
87 
88  description [This procedure is similar to the procedure NodeRecusiveDeref.]
89 
90  sideeffects []
91 
92  seealso []
93 
94 ***********************************************************************/
95 float Fpga_CutDerefSwitch( Fpga_Man_t * pMan, Fpga_Node_t * pNode, Fpga_Cut_t * pCut, int fFanouts )
96 {
97  Fpga_Node_t * pNodeChild;
98  float aArea;
99  int i;
100  // start the area of this cut
101  aArea = pNode->Switching;
102  if ( pCut->nLeaves == 1 )
103  return aArea;
104  // go through the children
105  for ( i = 0; i < pCut->nLeaves; i++ )
106  {
107  pNodeChild = pCut->ppLeaves[i];
108  assert( pNodeChild->nRefs > 0 );
109  if ( --pNodeChild->nRefs > 0 )
110  continue;
111  aArea += Fpga_CutDerefSwitch( pMan, pNodeChild, pNodeChild->pCutBest, fFanouts );
112  }
113  return aArea;
114 }
115 
116 /**Function*************************************************************
117 
118  Synopsis [Computes the array of mapping.]
119 
120  Description []
121 
122  SideEffects []
123 
124  SeeAlso []
125 
126 ***********************************************************************/
128 {
129  Fpga_Node_t * pNode;
130  float Switch;
131  int i;
132  Switch = 0.0;
133  for ( i = 0; i < vMapping->nSize; i++ )
134  {
135  pNode = vMapping->pArray[i];
136  // at least one phase has the best cut assigned
137  assert( !Fpga_NodeIsAnd(pNode) || pNode->pCutBest != NULL );
138  // at least one phase is used in the mapping
139  assert( pNode->nRefs > 0 );
140  // compute the array due to the supergate
141  Switch += pNode->Switching;
142  }
143  // add buffer for each CO driven by a CI
144  for ( i = 0; i < pMan->nOutputs; i++ )
145  if ( Fpga_NodeIsVar(Fpga_Regular(pMan->pOutputs[i])) && !Fpga_IsComplement(pMan->pOutputs[i]) )
146  Switch += Fpga_Regular(pMan->pOutputs[i])->Switching;
147  return Switch;
148 }
149 
150 ////////////////////////////////////////////////////////////////////////
151 /// END OF FILE ///
152 ////////////////////////////////////////////////////////////////////////
153 
154 
156 
Fpga_Node_t ** pOutputs
Definition: fpgaInt.h:106
float Fpga_CutDerefSwitch(Fpga_Man_t *pMan, Fpga_Node_t *pNode, Fpga_Cut_t *pCut, int fFanouts)
Definition: fpgaSwitch.c:95
ABC_NAMESPACE_IMPL_START float Fpga_CutGetSwitchDerefed(Fpga_Man_t *pMan, Fpga_Node_t *pNode, Fpga_Cut_t *pCut)
DECLARATIONS ///.
Definition: fpgaSwitch.c:43
Fpga_Node_t * ppLeaves[FPGA_MAX_LEAVES+1]
Definition: fpgaInt.h:237
#define ABC_NAMESPACE_IMPL_END
Definition: abc_global.h:108
float Fpga_MappingGetSwitching(Fpga_Man_t *pMan, Fpga_NodeVec_t *vMapping)
Definition: fpgaSwitch.c:127
#define ABC_NAMESPACE_IMPL_START
Definition: abc_global.h:107
int Fpga_NodeIsAnd(Fpga_Node_t *p)
Definition: fpgaCreate.c:127
int Fpga_NodeIsVar(Fpga_Node_t *p)
Definition: fpgaCreate.c:126
STRUCTURE DEFINITIONS ///.
Definition: fpgaInt.h:99
#define Fpga_Regular(p)
Definition: fpga.h:58
#define assert(ex)
Definition: util_old.h:213
Fpga_Node_t ** pArray
Definition: fpgaInt.h:252
float Fpga_CutRefSwitch(Fpga_Man_t *pMan, Fpga_Node_t *pNode, Fpga_Cut_t *pCut, int fFanouts)
Definition: fpgaSwitch.c:63
Fpga_Cut_t * pCutBest
Definition: fpgaInt.h:222
#define Fpga_IsComplement(p)
GLOBAL VARIABLES ///.
Definition: fpga.h:57