VTR-to-Bitstream

V2.0 published at FPL 2015, PDF

VTR-to-Bitstream is supplied as a patch for VTR version 7.0:

Unpack VTR (into the vtr_release/ directory), copy the patch file inside, and then apply the patch by typing: Currently, this release supports only the xc6vlx240tff1156-1ffg1156 Virtex-6 device found on the popular ML605 evaluation kit.
Other devices may be supported in the future, but if you're an eager one, then I'd be happy to assist you in doing so.

Dependencies:

Xilinx ISE supporting the ML605 device (full license; WebPack won't cut it, I'm afraid)
Torc (and its dependencies)
Yosys (and its dependencies)

Once successfully patched, ensure that the Xilinx tools are accessible from the command-line (e.g. xdl),
and that the Torc and Yosys dependencies are satisfied, then you should be able to just type:

and it should start compiling VTR, download the Torc & Yosys sources and compile those too,
and then generate build the routing graph for the supported architectures.

To run the entire flow from Verilog to Bitstream, use VTR's own ./run_vtr_flow.pl script,
which has been augmented with a new "bitstream" stage, as well as other nice things.
After fully placing and routing the design, this new stage performs VTR->XDL translation,
using a C++ application based on Torc, and then calls Xilinx bitgen to generate the bitstream.

Example usage (with the regular VTR (Odin II) front-end) executed from the "vtr_flow/scripts" subdirectory:

Example usage (with the new Yosys front-end):

The secret sauce of this project is mainly in three places:

bnpr2xdl/bnpr2xdl.{c,h}pp
A C++ application which reads in the .blif (LUT masks, RAM/DSP instantiations),
.net (packed netlist), .place (placement locations) and .route (routing switches used)
output files from VTR and transforms them into precisely into a Xilinx XDL netlist
that can re-enter the vendor flow.
xdlrc2vpr/xdlrc2vpr.{c,h}pp
A different C++ application which reads extracts the Xilinx routing resource graph
from Torc, and transform that into the VPR coordinate space and data format, so that
it can be imported directly into memory by VPR
vtr_flow/arch/xilinx/xc6vlx240tff1156.xml
VPR7.0 architecture file that describes the Virtex-6 CLB, the precise location of all
I/O, RAM and DSP columns, as well as empty regions in the fabric.
Timing numbers for the logic was inferred from the Xilinx STA trce tool,
and wire/LUT inpin delays have been estimated through linear regression.

DOWNLOAD

Changelog:

v2.1 -- September 2015: Major public release as described in FPL2015 paper;
The small difference to that which is published in this paper is that the
"VTB v1" and "route2xdl" parts of the flow (Fig. 3) have been merged and
completely rewritten to depend on Torc only.
v2.0 -- April 2015: Internal release with Yosys and Xilinx routing support
v1.1 -- October 2013: Minor release;
- Add example benchmark 'counter.v' (simple fast/slow up/down 8 bit counter)
  To build the counter.v design, enter vtr_flow/scripts and enter:
  
  ./run_vtr_flow.pl ../benchmarks/verilog/counter.v ../arch/xilinx/xc6vlx240tff1156.xml -vpr_fix_pins ../arch/xilinx/ml605.ioplace
- Add support for translating UCF pin constraints to VPR constraints
  Example usage:
  
  ./ucf2ioplace.py ML605.ucf ../arch/xilinx/xc6vlx240tff1156.ioplace > ../arch/xilinx/ml605.ioplace
  (ML605.ucf available from Xilinx here)
- Add support for RAMB18 36x512 mode
v1.0 -- April 2013: Initial release